From 3b9cb66b0965b3308c2aa138083ae462f2ca996b Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sat, 4 Dec 2021 18:25:56 +0100 Subject: [PATCH 1/5] PLATFORM_IDENT: Remove underscores and duplicate chars Underscores are used to decipher /dev/serial/by-id/ names. --- src/platforms/f4discovery/platform.h | 2 +- src/platforms/hydrabus/platform.h | 2 +- src/platforms/stlink/platform.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/platforms/f4discovery/platform.h b/src/platforms/f4discovery/platform.h index dbec2214151..cfe3645b308 100644 --- a/src/platforms/f4discovery/platform.h +++ b/src/platforms/f4discovery/platform.h @@ -32,7 +32,7 @@ #define PLATFORM_HAS_TRACESWO #ifdef BLACKPILL -#define PLATFORM_IDENT "(F4Discovery/BlackPillV2) " +#define PLATFORM_IDENT "(F4Discovery-BlackPillV2) " /* Important pin mappings for STM32 implementation: * JTAG/SWD * PA1: TDI
diff --git a/src/platforms/hydrabus/platform.h b/src/platforms/hydrabus/platform.h index 93ccc75de97..8a97c223310 100644 --- a/src/platforms/hydrabus/platform.h +++ b/src/platforms/hydrabus/platform.h @@ -32,7 +32,7 @@ #include #define PLATFORM_HAS_TRACESWO -#define PLATFORM_IDENT " (HydraBus))" +#define PLATFORM_IDENT " (HydraBus)" /* Important pin mappings for STM32 implementation: * diff --git a/src/platforms/stlink/platform.h b/src/platforms/stlink/platform.h index f848ae79fd7..bc72755c46b 100644 --- a/src/platforms/stlink/platform.h +++ b/src/platforms/stlink/platform.h @@ -39,7 +39,7 @@ extern bool debug_bmp; int usbuart_debug_write(const char *buf, size_t len); #endif -#define PLATFORM_IDENT "(STLINK/V2) " +#define PLATFORM_IDENT "(STLINK-V2) " /* Hardware definitions... */ #define TDI_PORT GPIOA From 107f65d02def555dc022f07c2b0ce2e48ded4f75 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Fri, 19 Nov 2021 00:01:33 +0100 Subject: [PATCH 2/5] cortexm: When detaching remove C_HALT from DHCSR. Writing only the debug key seems not enough. --- src/target/cortexm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/target/cortexm.c b/src/target/cortexm.c index f7ad4e0c012..2eb31a84dcc 100644 --- a/src/target/cortexm.c +++ b/src/target/cortexm.c @@ -557,6 +557,9 @@ void cortexm_detach(target *t) /* Restort DEMCR*/ ADIv5_AP_t *ap = cortexm_ap(t); target_mem_write32(t, CORTEXM_DEMCR, ap->ap_cortexm_demcr); + /* Resume from halt */ + target_mem_write32(t, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY | + CORTEXM_DHCSR_C_DEBUGEN); /* Disable debug */ target_mem_write32(t, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY); } From cf41a60bfe234947ac4dc2b4250747eb2265e7ae Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Fri, 19 Nov 2021 00:02:39 +0100 Subject: [PATCH 3/5] STM32F4: Move DBGMCU_handling to target specific code. Apply for F4 too. --- src/target/adiv5.c | 17 ----------------- src/target/stm32f4.c | 28 +++++++++++++++++++++++----- 2 files changed, 23 insertions(+), 22 deletions(-) diff --git a/src/target/adiv5.c b/src/target/adiv5.c index 4cc528fda48..58929ff752d 100644 --- a/src/target/adiv5.c +++ b/src/target/adiv5.c @@ -429,23 +429,6 @@ static bool cortexm_prepare(ADIv5_AP_t *ap) return false; } } - /* Apply device specific settings for successfull Romtable scan - * - * STM32F7 in WFI will not read ROMTABLE when using WFI - */ - if ((ap->dp->targetid >> 1 & 0x7ff) == 0x20) { - uint32_t dbgmcu_cr = 7; - uint32_t dbgmcu_cr_addr = 0xE0042004; - switch ((ap->dp->targetid >> 16) & 0xfff) { - case 0x449: - case 0x451: - case 0x452: - ap->ap_storage = adiv5_mem_read32(ap, dbgmcu_cr_addr); - dbgmcu_cr = ap->ap_storage | 7; - adiv5_mem_write(ap, dbgmcu_cr_addr, &dbgmcu_cr, sizeof(dbgmcu_cr)); - break; - } - } return true; } diff --git a/src/target/stm32f4.c b/src/target/stm32f4.c index a2bd45b2b14..d23652a0022 100644 --- a/src/target/stm32f4.c +++ b/src/target/stm32f4.c @@ -110,6 +110,10 @@ static int stm32f4_flash_write(struct target_flash *f, #define AXIM_BASE 0x8000000 #define ITCM_BASE 0x0200000 +#define DBGMCU_CR_DBG_SLEEP (0x1U << 0U) +#define DBGMCU_CR_DBG_STOP (0x1U << 1U) +#define DBGMCU_CR_DBG_STANDBY (0x1U << 2U) + struct stm32f4_flash { struct target_flash f; enum align psize; @@ -117,6 +121,10 @@ struct stm32f4_flash { uint8_t bank_split; }; +struct stm32f4_priv_s { + uint32_t dbgmcu_cr; +}; + enum IDS_STM32F247 { ID_STM32F20X = 0x411, ID_STM32F40X = 0x413, @@ -194,10 +202,12 @@ static char *stm32f4_get_chip_name(uint32_t idcode) } } -static void stm32f7_detach(target *t) +static void stm32f4_detach(target *t) { - ADIv5_AP_t *ap = cortexm_ap(t); - target_mem_write32(t, DBGMCU_CR, ap->ap_storage); + struct stm32f4_priv_s *ps = (struct stm32f4_priv_s*)t->target_storage; + + /*reverse all changes to DBGMCU_CR*/ + target_mem_write32(t, DBGMCU_CR, ps->dbgmcu_cr); cortexm_detach(t); } @@ -214,8 +224,6 @@ bool stm32f4_probe(target *t) case ID_STM32F74X: /* F74x RM0385 Rev.4 */ case ID_STM32F76X: /* F76x F77x RM0410 */ case ID_STM32F72X: /* F72x F73x RM0431 */ - t->detach = stm32f7_detach; - /* fall through */ case ID_STM32F40X: case ID_STM32F42X: /* 427/437 */ case ID_STM32F46X: /* 469/479 */ @@ -226,6 +234,7 @@ bool stm32f4_probe(target *t) case ID_STM32F412: /* F412 RM0402 Rev.4, 256 kB Ram */ case ID_STM32F401E: /* F401 D/E RM0368 Rev.3 */ case ID_STM32F413: /* F413 RM0430 Rev.2, 320 kB Ram, 1.5 MB flash. */ + t->detach = stm32f4_detach; t->driver = stm32f4_get_chip_name(t->idcode); t->attach = stm32f4_attach; target_add_commands(t, stm32f4_cmd_list, t->driver); @@ -295,6 +304,15 @@ static bool stm32f4_attach(target *t) return false; } bool use_dual_bank = false; + /* Save DBGMCU_CR to restore it when detaching*/ + struct stm32f4_priv_s *priv_storage = calloc(1, sizeof(*priv_storage)); + priv_storage->dbgmcu_cr = target_mem_read32(t, DBGMCU_CR); + t->target_storage = (void*)priv_storage; + /* Enable debugging during all low power modes*/ + target_mem_write32(t, DBGMCU_CR, DBGMCU_CR_DBG_SLEEP | + DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_DBG_STOP); + + /* Free previously loaded memory map */ target_mem_map_free(t); if (is_f7) { target_add_ram(t, 0x00000000, 0x4000); /* 16 k ITCM Ram */ From 062f7f28e8a089b8e5428c65f8c58adbf817c840 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sat, 20 Nov 2021 13:13:55 +0100 Subject: [PATCH 4/5] cortexm: Use forced halt when attaching With recent changes, in probe we do no special handling for special targets. E.g. for STM32F7, DBGMCU is not yet changed in probe(). So after probe, target may again be in WFI. So use forced halt to regain control for attaching. --- src/target/adiv5.c | 4 ++-- src/target/cortexm.c | 8 ++++++-- src/target/cortexm.h | 2 +- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/target/adiv5.c b/src/target/adiv5.c index 58929ff752d..672167be63f 100644 --- a/src/target/adiv5.c +++ b/src/target/adiv5.c @@ -314,7 +314,7 @@ uint64_t adiv5_ap_read_pidr(ADIv5_AP_t *ap, uint32_t addr) * Repeat the write command with the highest possible value * of the trannsaction counter, if not on MINDP */ -static uint32_t cortexm_initial_halt(ADIv5_AP_t *ap) +uint32_t cortexm_forced_halt(ADIv5_AP_t *ap) { platform_timeout to ; uint32_t ctrlstat = adiv5_dp_read(ap->dp, ADIV5_DP_CTRLSTAT); @@ -401,7 +401,7 @@ static bool cortexm_prepare(ADIv5_AP_t *ap) #if ((PC_HOSTED == 1) || (ENABLE_DEBUG == 1)) uint32_t start_time = platform_time_ms(); #endif - uint32_t dhcsr = cortexm_initial_halt(ap); + uint32_t dhcsr = cortexm_forced_halt(ap); if (!dhcsr) { DEBUG_WARN("Halt via DHCSR: Failure DHCSR %08" PRIx32 " after % " PRId32 "ms\nTry again, evt. with longer timeout or " diff --git a/src/target/cortexm.c b/src/target/cortexm.c index 2eb31a84dcc..a24d7f88d40 100644 --- a/src/target/cortexm.c +++ b/src/target/cortexm.c @@ -487,8 +487,12 @@ bool cortexm_attach(target *t) /* Clear any pending fault condition */ target_check_error(t); - - target_halt_request(t); + /* With recent changes, we do no special handling for special target. + * E.g. for STM32F7, DBGMCU is not changes yet. + * So after probe, target may again be in WFI. + * Use forced halt to regain control. + */ + cortexm_forced_halt(ap); /* Request halt on reset */ target_mem_write32(t, CORTEXM_DEMCR, priv->demcr); diff --git a/src/target/cortexm.h b/src/target/cortexm.h index 8bd95d368f3..e6c5b40efbb 100644 --- a/src/target/cortexm.h +++ b/src/target/cortexm.h @@ -194,6 +194,6 @@ int cortexm_run_stub(target *t, uint32_t loadaddr, uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3); int cortexm_mem_write_sized( target *t, target_addr dest, const void *src, size_t len, enum align align); - +uint32_t cortexm_forced_halt(ADIv5_AP_t *ap); #endif From 17c5ae28135854f70c9928859763a4b7582e7c0d Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 23 Dec 2021 21:50:39 +0100 Subject: [PATCH 5/5] hosted/jtag: Fix error introduced with da15cc3cb75cc2a9f. Write in ending independant way. --- src/platforms/hosted/remote_jtagtap.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/src/platforms/hosted/remote_jtagtap.c b/src/platforms/hosted/remote_jtagtap.c index a5aa3b6cc6c..3874da0b3d8 100644 --- a/src/platforms/hosted/remote_jtagtap.c +++ b/src/platforms/hosted/remote_jtagtap.c @@ -126,26 +126,19 @@ static void jtagtap_tdi_tdo_seq( chunk = 64; } ticks -= chunk; - uint8_t di[8]; - memset(di, 0, 8); + uint64_t di = 0; int bytes = (chunk + 7) >> 3; - if (DI) { - memcpy(&di, DI, bytes); - int remainder = chunk & 7; - DI += bytes; - DI += bytes; - if (remainder) { - uint8_t rem = *DI; - rem &= (1 << remainder) - 1; - *di = rem; - } + int i = 0; + for (; i < bytes; i++) { + di = di | (*DI << (i * 8)); + DI ++; }; /* PRIx64 differs with system. Use it explicit in the format string*/ s = snprintf((char *)construct, REMOTE_MAX_MSG_SIZE, "!J%c%02x%" PRIx64 "%c", (!ticks && final_tms) ? REMOTE_TDITDO_TMS : REMOTE_TDITDO_NOTMS, - chunk, *(uint64_t*)di, REMOTE_EOM); + chunk, di, REMOTE_EOM); platform_buffer_write(construct,s); s = platform_buffer_read(construct, REMOTE_MAX_MSG_SIZE); @@ -156,7 +149,7 @@ static void jtagtap_tdi_tdo_seq( } if (DO) { uint64_t res = remotehston(-1, (char *)&construct[1]); - memcpy(DO, &res, bytes); + memcpy(DO, &res, bytes); /* Fixme: Endian dependant!*/ DO += bytes; } }