Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
Switch branches/tags
Nothing to show
Clone or download
Fetching latest commit…
Cannot retrieve the latest commit at this time.
Permalink
Type Name Latest commit message Commit time
Failed to load latest commit information.
images
README.md
assembled.jpg
bml_pmod_to_hyperram_02_fixed_02.png
bml_pmod_to_hyperram_02_fixed_02.rrpcb
bml_pmod_to_hyperram_02_fixed_02.zip
hr_pll.zip
hyper_dword.v
hyper_xface.v
hyperram.core

README.md

hyperram

Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC

This is an open-source RTL project for a simple DWORD burst interface to a Cypress S27KL0641DABHI020 64Mbit HyperRAM.

hr_pll.zip is the version for Xilinx 7-Series that runs at full FPGA fabric clock rate. The normal clear RTL version runs at FPGA fabric clock divided by 4 to achieve the 90 degrees phase shift for clock and the DDR data rates. The Xilinx 7-Series uses Xilinx specific primitives ( ODDRs, IDDRs ) and has a slightly different core interface.

Also included is a dual-PMOD PCB adapter design.

pinout

@OSHPark Shared Project: https://oshpark.com/shared_projects/oZ3pCvob

Kevin Hubbard - Black Mesa Labs 2018.04.28