• RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

    Verilog 12 3 Apache-2.0 Updated Aug 21, 2018
  • Shell Updated Aug 9, 2018
  • C 1 GPL-2.0 Updated Jun 26, 2018
  • RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

    3 Apache-2.0 Updated May 30, 2018
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