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Add support for v850E2 and v850E2V3

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1 parent 5dd76b2 commit 68539b472b9f6a8e6779bce7b0bd505203cef9b3 nickc committed
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38 bfd/ChangeLog
@@ -1,3 +1,41 @@
+2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
+ Ina Pandit <ina.pandit@kpitcummins.com>
+
+ * archures.c (DESCRIPTION): Define bfd_mach_v850e2 and
+ bfd_mach_v850e2v3.
+ * reloc.c (bfd_architecture): Define bfd_mach_v850e2 and
+ bfd_mach_v850e2v3.
+ (BFD_RELOC_V850_16_PCREL, BFD_RELOC_V850_17_PCREL,
+ BFD_RELOC_V850_22_PCREL, BFD_RELOC_V850_23,
+ BFD_RELOC_V850_32_PCREL, BFD_RELOC_V850_32_ABS,
+ BFD_RELOC_V850_16_SPLIT_OFFSET, BFD_RELOC_V850_16_S1,
+ BFD_RELOC_V850_LO16_SPLIT_OFFSET, BFD_RELOC_V850_SDA_15_16_OFFSET,
+ BFD_RELOC_V850_ZDA_16_16_OFFSET, BFD_RELOC_V850_CALLT_15_16_OFFSET,
+ BFD_RELOC_V850_32_GOTPCREL, BFD_RELOC_V850_16_GOT,
+ BFD_RELOC_V850_32_GOT, BFD_RELOC_V850_22_PLT_PCREL,
+ BFD_RELOC_V850_32_PLT_PCREL, BFD_RELOC_V850_COPY,
+ BFD_RELOC_V850_GLOB_DAT, BFD_RELOC_V850_JMP_SLOT,
+ BFD_RELOC_V850_RELATIVE, BFD_RELOC_V850_16_GOTOFF,
+ BFD_RELOC_V850_32_GOTOFF, BFD_RELOC_V850_CODE,
+ BFD_RELOC_V850_DATA): New relocations for V850 target.
+ * config.bfd: Match all v850 targets.
+ * cpu-v850.c (arch_info_struct): Define V850e2 and V850e2v3.
+ * elf32-v850.c (v850_elf_check_relocs): Check the newly added
+ relocations.
+ (v850_elf_perform_relocation ): Update the newly added
+ relocations.
+ (v850_elf_howto_t): Update the specifications of added
+ relocations.
+ (v850_elf_reloc_map): Update the relocation mappings.
+ (v850_elf_final_link_relocate): Maps added relocation into the
+ appropriate howto structure.
+ (v850_elf_object_p): Add support for V850E2 and V850E2V3.
+ (v850_elf_final_write_processing): Likewise.
+ (v850_elf_merge_private_bfd_data): Likewise.
+ (v850_elf_print_private_bfd_data): Likewise.
+ * libbfd.h: Regenerate.
+ * bfd-in2.h: Regenerate.
+
2010-07-23 Alan Modra <amodra@gmail.com>
* archive.c (_bfd_archive_bsd44_construct_extended_name_table):
View
9 bfd/archures.c
@@ -310,7 +310,9 @@ DESCRIPTION
. bfd_arch_v850, {* NEC V850 *}
.#define bfd_mach_v850 1
.#define bfd_mach_v850e 'E'
-.#define bfd_mach_v850e1 '1'
+.#define bfd_mach_v850e1 '1'
+.#define bfd_mach_v850e2 0x4532
+.#define bfd_mach_v850e2v3 0x45325633
. bfd_arch_arc, {* ARC Cores *}
.#define bfd_mach_arc_5 5
.#define bfd_mach_arc_6 6
@@ -417,9 +419,6 @@ DESCRIPTION
.#define bfd_mach_xc16xs 3
. bfd_arch_xtensa, {* Tensilica's Xtensa cores. *}
.#define bfd_mach_xtensa 1
-. bfd_arch_maxq, {* Dallas MAXQ 10/20 *}
-.#define bfd_mach_maxq10 10
-.#define bfd_mach_maxq20 20
. bfd_arch_z80,
.#define bfd_mach_z80strict 1 {* No undocumented opcodes. *}
.#define bfd_mach_z80 3 {* With ixl, ixh, iyl, and iyh. *}
@@ -498,7 +497,6 @@ extern const bfd_arch_info_type bfd_m68hc11_arch;
extern const bfd_arch_info_type bfd_m68hc12_arch;
extern const bfd_arch_info_type bfd_m68k_arch;
extern const bfd_arch_info_type bfd_m88k_arch;
-extern const bfd_arch_info_type bfd_maxq_arch;
extern const bfd_arch_info_type bfd_mcore_arch;
extern const bfd_arch_info_type bfd_mep_arch;
extern const bfd_arch_info_type bfd_mips_arch;
@@ -576,7 +574,6 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_m68hc12_arch,
&bfd_m68k_arch,
&bfd_m88k_arch,
- &bfd_maxq_arch,
&bfd_mcore_arch,
&bfd_mep_arch,
&bfd_microblaze_arch,
View
71 bfd/bfd-in2.h
@@ -1977,6 +1977,8 @@ enum bfd_architecture
#define bfd_mach_v850 1
#define bfd_mach_v850e 'E'
#define bfd_mach_v850e1 '1'
+#define bfd_mach_v850e2 0x4532 /* ('E'<<8|'2') */
+#define bfd_mach_v850e2v3 0x45325633 /* ('E'<<24|'2'<<16|'V'<<8|'3') */
bfd_arch_arc, /* ARC Cores */
#define bfd_mach_arc_5 5
#define bfd_mach_arc_6 6
@@ -2083,9 +2085,6 @@ enum bfd_architecture
#define bfd_mach_xc16xs 3
bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
#define bfd_mach_xtensa 1
- bfd_arch_maxq, /* Dallas MAXQ 10/20 */
-#define bfd_mach_maxq10 10
-#define bfd_mach_maxq20 20
bfd_arch_z80,
#define bfd_mach_z80strict 1 /* No undocumented opcodes. */
#define bfd_mach_z80 3 /* With ixl, ixh, iyl, and iyh. */
@@ -3608,6 +3607,72 @@ bits placed non-contiguously in the instruction. */
instructions. */
BFD_RELOC_V850_LO16_SPLIT_OFFSET,
+/* This is a 16-bit reloc. */
+ BFD_RELOC_V850_16_PCREL,
+
+/* This is a 17-bit reloc. */
+ BFD_RELOC_V850_17_PCREL,
+
+/* This is a 23-bit reloc. */
+ BFD_RELOC_V850_23,
+
+/* This is a 32-bit reloc. */
+ BFD_RELOC_V850_32_PCREL,
+
+/* This is a 32-bit reloc. */
+ BFD_RELOC_V850_32_ABS,
+
+/* This is a 16-bit reloc. */
+ BFD_RELOC_V850_16_SPLIT_OFFSET,
+
+/* This is a 16-bit reloc. */
+ BFD_RELOC_V850_16_S1,
+
+/* Low 16 bits. 16 bit shifted by 1. */
+ BFD_RELOC_V850_LO16_S1,
+
+/* This is a 16 bit offset from the call table base pointer. */
+ BFD_RELOC_V850_CALLT_15_16_OFFSET,
+
+/* DSO relocations. */
+ BFD_RELOC_V850_32_GOTPCREL,
+
+/* DSO relocations. */
+ BFD_RELOC_V850_16_GOT,
+
+/* DSO relocations. */
+ BFD_RELOC_V850_32_GOT,
+
+/* DSO relocations. */
+ BFD_RELOC_V850_22_PLT_PCREL,
+
+/* DSO relocations. */
+ BFD_RELOC_V850_32_PLT_PCREL,
+
+/* DSO relocations. */
+ BFD_RELOC_V850_COPY,
+
+/* DSO relocations. */
+ BFD_RELOC_V850_GLOB_DAT,
+
+/* DSO relocations. */
+ BFD_RELOC_V850_JMP_SLOT,
+
+/* DSO relocations. */
+ BFD_RELOC_V850_RELATIVE,
+
+/* DSO relocations. */
+ BFD_RELOC_V850_16_GOTOFF,
+
+/* DSO relocations. */
+ BFD_RELOC_V850_32_GOTOFF,
+
+/* start code. */
+ BFD_RELOC_V850_CODE,
+
+/* start data in text. */
+ BFD_RELOC_V850_DATA,
+
/* This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
instruction. */
BFD_RELOC_MN10300_32_PCREL,
View
15 bfd/config.bfd
@@ -31,7 +31,6 @@ targ_underscore=no
# Catch obsolete configurations.
case $targ in
- maxq-*-coff | \
null)
if test "x$enable_obsolete" != xyes; then
echo "*** Configuration $targ is obsolete." >&2
@@ -47,6 +46,7 @@ case $targ in
m68*-apollo-* | \
m68*-bull-sysv* | \
m68*-*-rtemscoff* | \
+ maxq-*-coff | \
i960-*-rtems* | \
or32-*-rtems* | \
m68*-*-lynxos* | \
@@ -90,7 +90,6 @@ m6811*|m68hc11*) targ_archs="bfd_m68hc11_arch bfd_m68hc12_arch" ;;
m6812*|m68hc12*) targ_archs="bfd_m68hc12_arch bfd_m68hc11_arch" ;;
m68*) targ_archs=bfd_m68k_arch ;;
m88*) targ_archs=bfd_m88k_arch ;;
-maxq*) targ_archs=bfd_maxq_arch ;;
microblaze*) targ_archs=bfd_microblaze_arch ;;
mips*) targ_archs=bfd_mips_arch ;;
or32*) targ_archs=bfd_or32_arch ;;
@@ -880,10 +879,6 @@ case "${targ}" in
targ_underscore=yes
;;
- maxq-*-coff)
- targ_defvec=maxqcoff_vec
- ;;
-
mcore-*-elf)
targ_defvec=bfd_elf32_mcore_big_vec
targ_selvecs="bfd_elf32_mcore_big_vec bfd_elf32_mcore_little_vec"
@@ -1473,13 +1468,7 @@ case "${targ}" in
targ_underscore=yes
;;
- v850-*-*)
- targ_defvec=bfd_elf32_v850_vec
- ;;
- v850e-*-*)
- targ_defvec=bfd_elf32_v850_vec
- ;;
- v850ea-*-*)
+ v850*-*-*)
targ_defvec=bfd_elf32_v850_vec
;;
View
10 bfd/cpu-v850.c
@@ -1,6 +1,6 @@
/* BFD support for the NEC V850 processor
- Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2007
- Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2007,
+ 2010 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
@@ -32,8 +32,10 @@
static const bfd_arch_info_type arch_info_struct[] =
{
- N (bfd_mach_v850e1, "v850e1", FALSE, & arch_info_struct[1]),
- N (bfd_mach_v850e, "v850e", FALSE, NULL)
+ N (bfd_mach_v850e2v3, "v850e2v3", FALSE, & arch_info_struct[1]),
+ N (bfd_mach_v850e2, "v850e2", FALSE, & arch_info_struct[2]),
+ N (bfd_mach_v850e1, "v850e1", FALSE, & arch_info_struct[3]),
+ N (bfd_mach_v850e, "v850e", FALSE, NULL)
};
#undef NEXT
View
766 bfd/elf32-v850.c
@@ -31,8 +31,11 @@
#include "elf/v850.h"
#include "libiberty.h"
-/* Sign-extend a 24-bit number. */
-#define SEXT24(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000)
+/* Sign-extend a 17-bit number. */
+#define SEXT17(x) ((((x) & 0x1ffff) ^ 0x10000) - 0x10000)
+
+/* Sign-extend a 22-bit number. */
+#define SEXT22(x) ((((x) & 0x3fffff) ^ 0x200000) - 0x200000)
static reloc_howto_type v850_elf_howto_table[];
@@ -89,16 +92,25 @@ v850_elf_check_relocs (bfd *abfd,
default:
case R_V850_NONE:
case R_V850_9_PCREL:
+ case R_V850_16_PCREL:
+ case R_V850_17_PCREL:
case R_V850_22_PCREL:
- case R_V850_HI16_S:
+ case R_V850_32_PCREL:
+ case R_V850_32_ABS:
case R_V850_HI16:
+ case R_V850_HI16_S:
case R_V850_LO16:
+ case R_V850_LO16_S1:
case R_V850_LO16_SPLIT_OFFSET:
+ case R_V850_23:
case R_V850_ABS32:
case R_V850_REL32:
case R_V850_16:
+ case R_V850_16_S1:
+ case R_V850_16_SPLIT_OFFSET:
case R_V850_8:
case R_V850_CALLT_6_7_OFFSET:
+ case R_V850_CALLT_15_16_OFFSET:
case R_V850_CALLT_16_16_OFFSET:
break;
@@ -132,11 +144,11 @@ v850_elf_check_relocs (bfd *abfd,
common = ".zcommon";
goto small_data_common;
- case R_V850_TDA_4_5_OFFSET:
case R_V850_TDA_4_4_OFFSET:
+ case R_V850_TDA_4_5_OFFSET:
+ case R_V850_TDA_7_7_OFFSET:
case R_V850_TDA_6_8_OFFSET:
case R_V850_TDA_7_8_OFFSET:
- case R_V850_TDA_7_7_OFFSET:
case R_V850_TDA_16_16_OFFSET:
other = V850_OTHER_TDA;
common = ".tcommon";
@@ -315,15 +327,15 @@ find_remembered_hi16s_reloc (bfd_vma addend, bfd_boolean *already_found)
will store 0 in the value fields for the MOVHI and MOVEA instructions
and addend will be the address of fred, but for these instructions:
- movhi hi( fred + 0x123456), r0, r1
- movea lo( fred + 0x123456), r1, r1
+ movhi hi( fred + 0x123456 ), r0, r1
+ movea lo( fred + 0x123456 ), r1, r1
the value stored in the MOVHI instruction will be 0x12 and the value
stored in the MOVEA instruction will be 0x3456. If however the
instructions were:
- movhi hi( fred + 0x10ffff), r0, r1
- movea lo( fred + 0x10ffff), r1, r1
+ movhi hi( fred + 0x10ffff ), r0, r1
+ movea lo( fred + 0x10ffff ), r1, r1
then the value stored in the MOVHI instruction would be 0x11 (not
0x10) and the value stored in the MOVEA instruction would be 0xffff.
@@ -332,8 +344,8 @@ find_remembered_hi16s_reloc (bfd_vma addend, bfd_boolean *already_found)
adds 0xffffffff (sign extension!) producing 0x10ffff. Similarly if
the instructions were:
- movhi hi( fred - 1), r0, r1
- movea lo( fred - 1), r1, r1
+ movhi hi( fred - 1 ), r0, r1
+ movea lo( fred - 1 ), r1, r1
then 0 is stored in the MOVHI instruction and -1 is stored in the
MOVEA instruction.
@@ -345,8 +357,8 @@ find_remembered_hi16s_reloc (bfd_vma addend, bfd_boolean *already_found)
clear, the assembler will not have added 1 to the previous HI16S reloc
to compensate for this effect. For example:
- movhi hi( fred + 0x123456), r0, r1
- movea lo( fred + 0x123456), r1, r1
+ movhi hi( fred + 0x123456 ), r0, r1
+ movea lo( fred + 0x123456 ), r1, r1
The value stored in HI16S reloc is 0x12, the value stored in the LO16
reloc is 0x3456. If we assume that the address of fred is 0x00007000
@@ -366,8 +378,8 @@ find_remembered_hi16s_reloc (bfd_vma addend, bfd_boolean *already_found)
Note that if the 15th bit was set in the value stored in the LO16
reloc, then we do not have to do anything:
- movhi hi( fred + 0x10ffff), r0, r1
- movea lo( fred + 0x10ffff), r1, r1
+ movhi hi( fred + 0x10ffff ), r0, r1
+ movea lo( fred + 0x10ffff ), r1, r1
HI16S: 0x0011 + (0x00007000 >> 16) = 0x11
LO16: 0xffff + (0x00007000 & 0xffff) = 0x6fff
@@ -387,8 +399,8 @@ find_remembered_hi16s_reloc (bfd_vma addend, bfd_boolean *already_found)
So, for example if fred is at address 0xf000:
- movhi hi( fred + 0xffff), r0, r1 [bit 15 of the offset is set]
- movea lo( fred + 0xffff), r1, r1
+ movhi hi( fred + 0xffff ), r0, r1 [bit 15 of the offset is set]
+ movea lo( fred + 0xffff ), r1, r1
HI16S: 0x0001 + (0x0000f000 >> 16) = 0x0001
LO16: 0xffff + (0x0000f000 & 0xffff) = 0xefff (carry into bit 16 is lost)
@@ -401,8 +413,8 @@ find_remembered_hi16s_reloc (bfd_vma addend, bfd_boolean *already_found)
Similarly, if the 15th bit remains clear, but overflow occurs into
the 16th bit then (assuming the address of fred is 0xf000):
- movhi hi( fred + 0x7000), r0, r1 [bit 15 of the offset is clear]
- movea lo( fred + 0x7000), r1, r1
+ movhi hi( fred + 0x7000 ), r0, r1 [bit 15 of the offset is clear]
+ movea lo( fred + 0x7000 ), r1, r1
HI16S: 0x0000 + (0x0000f000 >> 16) = 0x0000
LO16: 0x7000 + (0x0000f000 & 0xffff) = 0x6fff (carry into bit 16 is lost)
@@ -416,8 +428,8 @@ find_remembered_hi16s_reloc (bfd_vma addend, bfd_boolean *already_found)
15th bit changes its value from being set to being clear, as the HI16S
reloc will have already added in 1 to the high part for us:
- movhi hi( fred + 0xffff), r0, r1 [bit 15 of the offset is set]
- movea lo( fred + 0xffff), r1, r1
+ movhi hi( fred + 0xffff ), r0, r1 [bit 15 of the offset is set]
+ movea lo( fred + 0xffff ), r1, r1
HI16S: 0x0001 + (0x00007000 >> 16)
LO16: 0xffff + (0x00007000 & 0xffff) = 0x6fff (carry into bit 16 is lost)
@@ -430,8 +442,8 @@ find_remembered_hi16s_reloc (bfd_vma addend, bfd_boolean *already_found)
but if the 15th bit goes from being clear to being set, then we must
once again handle overflow:
- movhi hi( fred + 0x7000), r0, r1 [bit 15 of the offset is clear]
- movea lo( fred + 0x7000), r1, r1
+ movhi hi( fred + 0x7000 ), r0, r1 [bit 15 of the offset is clear]
+ movea lo( fred + 0x7000 ), r1, r1
HI16S: 0x0000 + (0x0000ffff >> 16)
LO16: 0x7000 + (0x0000ffff & 0xffff) = 0x6fff (carry into bit 16)
@@ -504,6 +516,13 @@ v850_elf_perform_relocation (bfd *abfd,
bfd_put_32 (abfd, addend, address);
return bfd_reloc_ok;
+ case R_V850_23:
+ insn = bfd_get_32 (abfd, address);
+ insn &= ~((0x7f << 4) | (0x7fff80 << (16-7)));
+ insn |= ((addend & 0x7f) << 4) | ((addend & 0x7fff80) << (16-7));
+ bfd_put_32 (abfd, (bfd_vma) insn, address);
+ return bfd_reloc_ok;
+
case R_V850_22_PCREL:
if (saddend > 0x1fffff || saddend < -0x200000)
return bfd_reloc_overflow;
@@ -517,6 +536,30 @@ v850_elf_perform_relocation (bfd *abfd,
bfd_put_32 (abfd, (bfd_vma) insn, address);
return bfd_reloc_ok;
+ case R_V850_17_PCREL:
+ if (saddend > 0xffff || saddend < -0x10000)
+ return bfd_reloc_overflow;
+
+ if ((addend % 2) != 0)
+ return bfd_reloc_dangerous;
+
+ insn = bfd_get_32 (abfd, address);
+ insn &= ~ 0xfffe0010;
+ insn |= ((addend & 0xfffe) << 16) | ((addend & 0x10000) >> (16-4));
+ break;
+
+ case R_V850_16_PCREL:
+ if ((saddend < -0xffff) || (saddend > 0))
+ return bfd_reloc_overflow;
+
+ if ((addend % 2) != 0)
+ return bfd_reloc_dangerous;
+
+ insn = bfd_get_16 (abfd, address);
+ insn &= ~0xfffe;
+ insn |= (-addend & 0xfffe);
+ break;
+
case R_V850_9_PCREL:
if (saddend > 0xff || saddend < -0x100)
return bfd_reloc_overflow;
@@ -577,6 +620,36 @@ v850_elf_perform_relocation (bfd *abfd,
insn = addend;
break;
+ case R_V850_CALLT_15_16_OFFSET:
+ insn = bfd_get_16 (abfd, address);
+
+ addend += insn & 0xfffe;;
+
+ saddend = (bfd_signed_vma) addend;
+
+ if (saddend > 0xffff || saddend < 0)
+ return bfd_reloc_overflow;
+
+ insn = (0xfffe & addend)
+ | (insn & ~0xfffe);
+ break;
+
+ case R_V850_CALLT_6_7_OFFSET:
+ insn = bfd_get_16 (abfd, address);
+ addend += ((insn & 0x3f) << 1);
+
+ saddend = (bfd_signed_vma) addend;
+
+ if (saddend > 0x7e || saddend < 0)
+ return bfd_reloc_overflow;
+
+ if (addend & 1)
+ return bfd_reloc_dangerous;
+
+ insn &= 0xff80;
+ insn |= (addend >> 1);
+ break;
+
case R_V850_16:
case R_V850_SDA_16_16_OFFSET:
case R_V850_ZDA_16_16_OFFSET:
@@ -591,6 +664,7 @@ v850_elf_perform_relocation (bfd *abfd,
insn = addend;
break;
+ case R_V850_16_S1:
case R_V850_SDA_15_16_OFFSET:
case R_V850_ZDA_15_16_OFFSET:
insn = bfd_get_16 (abfd, address);
@@ -681,6 +755,18 @@ v850_elf_perform_relocation (bfd *abfd,
insn |= addend;
break;
+ case R_V850_LO16_S1:
+ insn = bfd_get_16 (abfd, address);
+ result = insn & 0xfffe;
+ if (! v850_elf_perform_lo16_relocation (abfd, &result, addend))
+ return bfd_reloc_overflow;
+ if (result & 1)
+ return bfd_reloc_overflow;
+ insn = (result & 0xfffe)
+ | (insn & ~0xfffe);
+ bfd_put_16 (abfd, insn, address);
+ return bfd_reloc_ok;
+
case R_V850_LO16_SPLIT_OFFSET:
insn = bfd_get_32 (abfd, address);
result = ((insn & 0xfffe0000) >> 16) | ((insn & 0x20) >> 5);
@@ -692,8 +778,9 @@ v850_elf_perform_relocation (bfd *abfd,
bfd_put_32 (abfd, insn, address);
return bfd_reloc_ok;
- case R_V850_ZDA_16_16_SPLIT_OFFSET:
+ case R_V850_16_SPLIT_OFFSET:
case R_V850_SDA_16_16_SPLIT_OFFSET:
+ case R_V850_ZDA_16_16_SPLIT_OFFSET:
insn = bfd_get_32 (abfd, address);
addend += ((insn & 0xfffe0000) >> 16) + ((insn & 0x20) >> 5);
@@ -709,22 +796,6 @@ v850_elf_perform_relocation (bfd *abfd,
bfd_put_32 (abfd, (bfd_vma) insn, address);
return bfd_reloc_ok;
- case R_V850_CALLT_6_7_OFFSET:
- insn = bfd_get_16 (abfd, address);
- addend += ((insn & 0x3f) << 1);
-
- saddend = (bfd_signed_vma) addend;
-
- if (saddend > 0x7e || saddend < 0)
- return bfd_reloc_overflow;
-
- if (addend & 1)
- return bfd_reloc_dangerous;
-
- insn &= 0xff80;
- insn |= (addend >> 1);
- break;
-
case R_V850_GNU_VTINHERIT:
case R_V850_GNU_VTENTRY:
return bfd_reloc_ok;
@@ -813,7 +884,8 @@ v850_elf_ignore_reloc (bfd *abfd ATTRIBUTE_UNUSED,
return bfd_reloc_ok;
}
/* Note: It is REQUIRED that the 'type' value of each entry
- in this array match the index of the entry in the array. */
+ in this array match the index of the entry in the array.
+ SeeAlso: RELOC_NUBMER in include/elf/v850.h */
static reloc_howto_type v850_elf_howto_table[] =
{
/* This reloc does nothing. */
@@ -833,9 +905,9 @@ static reloc_howto_type v850_elf_howto_table[] =
/* A PC relative 9 bit branch. */
HOWTO (R_V850_9_PCREL, /* Type. */
- 2, /* Rightshift. */
- 2, /* Size (0 = byte, 1 = short, 2 = long). */
- 26, /* Bitsize. */
+ 0, /* Rightshift. */
+ 1, /* Size (0 = byte, 1 = short, 2 = long). */
+ 9, /* Bitsize. */
TRUE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_bitfield, /* Complain_on_overflow. */
@@ -848,11 +920,11 @@ static reloc_howto_type v850_elf_howto_table[] =
/* A PC relative 22 bit branch. */
HOWTO (R_V850_22_PCREL, /* Type. */
- 2, /* Rightshift. */
+ 0, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
22, /* Bitsize. */
TRUE, /* PC_relative. */
- 7, /* Bitpos. */
+ 0, /* Bitpos. */
complain_overflow_signed, /* Complain_on_overflow. */
v850_elf_reloc, /* Special_function. */
"R_V850_22_PCREL", /* Name. */
@@ -1161,82 +1233,83 @@ static reloc_howto_type v850_elf_howto_table[] =
0xffff, /* Dst_mask. */
FALSE), /* PCrel_offset. */
+
/* GNU extension to record C++ vtable hierarchy */
HOWTO (R_V850_GNU_VTINHERIT, /* Type. */
- 0, /* Rightshift. */
- 2, /* Size (0 = byte, 1 = short, 2 = long). */
- 0, /* Bitsize. */
- FALSE, /* PC_relative. */
- 0, /* Bitpos. */
- complain_overflow_dont, /* Complain_on_overflow. */
- NULL, /* Special_function. */
- "R_V850_GNU_VTINHERIT", /* Name. */
- FALSE, /* Partial_inplace. */
- 0, /* Src_mask. */
- 0, /* Dst_mask. */
- FALSE), /* PCrel_offset. */
-
- /* GNU extension to record C++ vtable member usage */
+ 0, /* Rightshift. */
+ 2, /* Size (0 = byte, 1 = short, 2 = long). */
+ 0, /* Bitsize. */
+ FALSE, /* PC_relative. */
+ 0, /* Bitpos. */
+ complain_overflow_dont, /* Complain_on_overflow. */
+ NULL, /* Special_function. */
+ "R_V850_GNU_VTINHERIT", /* Name. */
+ FALSE, /* Partial_inplace. */
+ 0, /* Src_mask. */
+ 0, /* Dst_mask. */
+ FALSE), /* PCrel_offset. */
+
+ /* GNU extension to record C++ vtable member usage. */
HOWTO (R_V850_GNU_VTENTRY, /* Type. */
- 0, /* Rightshift. */
- 2, /* Size (0 = byte, 1 = short, 2 = long). */
- 0, /* Bitsize. */
- FALSE, /* PC_relative. */
- 0, /* Bitpos. */
- complain_overflow_dont, /* Complain_on_overflow. */
- _bfd_elf_rel_vtable_reloc_fn, /* Special_function. */
- "R_V850_GNU_VTENTRY", /* Name. */
- FALSE, /* Partial_inplace. */
- 0, /* Src_mask. */
- 0, /* Dst_mask. */
- FALSE), /* PCrel_offset. */
+ 0, /* Rightshift. */
+ 2, /* Size (0 = byte, 1 = short, 2 = long). */
+ 0, /* Bitsize. */
+ FALSE, /* PC_relative. */
+ 0, /* Bitpos. */
+ complain_overflow_dont, /* Complain_on_overflow. */
+ _bfd_elf_rel_vtable_reloc_fn, /* Special_function. */
+ "R_V850_GNU_VTENTRY", /* Name. */
+ FALSE, /* Partial_inplace. */
+ 0, /* Src_mask. */
+ 0, /* Dst_mask. */
+ FALSE), /* PCrel_offset. */
/* Indicates a .longcall pseudo-op. The compiler will generate a .longcall
pseudo-op when it finds a function call which can be relaxed. */
HOWTO (R_V850_LONGCALL, /* Type. */
- 0, /* Rightshift. */
- 2, /* Size (0 = byte, 1 = short, 2 = long). */
- 32, /* Bitsize. */
- TRUE, /* PC_relative. */
- 0, /* Bitpos. */
- complain_overflow_signed, /* Complain_on_overflow. */
- v850_elf_ignore_reloc, /* Special_function. */
- "R_V850_LONGCALL", /* Name. */
- FALSE, /* Partial_inplace. */
- 0, /* Src_mask. */
- 0, /* Dst_mask. */
- TRUE), /* PCrel_offset. */
+ 0, /* Rightshift. */
+ 2, /* Size (0 = byte, 1 = short, 2 = long). */
+ 32, /* Bitsize. */
+ TRUE, /* PC_relative. */
+ 0, /* Bitpos. */
+ complain_overflow_signed, /* Complain_on_overflow. */
+ v850_elf_ignore_reloc, /* Special_function. */
+ "R_V850_LONGCALL", /* Name. */
+ FALSE, /* Partial_inplace. */
+ 0, /* Src_mask. */
+ 0, /* Dst_mask. */
+ TRUE), /* PCrel_offset. */
/* Indicates a .longjump pseudo-op. The compiler will generate a
.longjump pseudo-op when it finds a branch which can be relaxed. */
HOWTO (R_V850_LONGJUMP, /* Type. */
- 0, /* Rightshift. */
- 2, /* Size (0 = byte, 1 = short, 2 = long). */
- 32, /* Bitsize. */
- TRUE, /* PC_relative. */
- 0, /* Bitpos. */
- complain_overflow_signed, /* Complain_on_overflow. */
- v850_elf_ignore_reloc, /* Special_function. */
- "R_V850_LONGJUMP", /* Name. */
- FALSE, /* Partial_inplace. */
- 0, /* Src_mask. */
- 0, /* Dst_mask. */
- TRUE), /* PCrel_offset. */
+ 0, /* Rightshift. */
+ 2, /* Size (0 = byte, 1 = short, 2 = long). */
+ 32, /* Bitsize. */
+ TRUE, /* PC_relative. */
+ 0, /* Bitpos. */
+ complain_overflow_signed, /* Complain_on_overflow. */
+ v850_elf_ignore_reloc, /* Special_function. */
+ "R_V850_LONGJUMP", /* Name. */
+ FALSE, /* Partial_inplace. */
+ 0, /* Src_mask. */
+ 0, /* Dst_mask. */
+ TRUE), /* PCrel_offset. */
HOWTO (R_V850_ALIGN, /* Type. */
- 0, /* Rightshift. */
- 1, /* Size (0 = byte, 1 = short, 2 = long). */
- 0, /* Bitsize. */
- FALSE, /* PC_relative. */
- 0, /* Bitpos. */
- complain_overflow_unsigned, /* Complain_on_overflow. */
- v850_elf_ignore_reloc, /* Special_function. */
- "R_V850_ALIGN", /* Name. */
- FALSE, /* Partial_inplace. */
- 0, /* Src_mask. */
- 0, /* Dst_mask. */
- TRUE), /* PCrel_offset. */
-
+ 0, /* Rightshift. */
+ 1, /* Size (0 = byte, 1 = short, 2 = long). */
+ 0, /* Bitsize. */
+ FALSE, /* PC_relative. */
+ 0, /* Bitpos. */
+ complain_overflow_unsigned, /* Complain_on_overflow. */
+ v850_elf_ignore_reloc, /* Special_function. */
+ "R_V850_ALIGN", /* Name. */
+ FALSE, /* Partial_inplace. */
+ 0, /* Src_mask. */
+ 0, /* Dst_mask. */
+ TRUE), /* PCrel_offset. */
+
/* Simple pc-relative 32bit reloc. */
HOWTO (R_V850_REL32, /* Type. */
0, /* Rightshift. */
@@ -1266,6 +1339,341 @@ static reloc_howto_type v850_elf_howto_table[] =
0xfffe0020, /* Src_mask. */
0xfffe0020, /* Dst_mask. */
FALSE), /* PCrel_offset. */
+
+ /* A unsigned PC relative 16 bit loop. */
+ HOWTO (R_V850_16_PCREL, /* Type. */
+ 0, /* Rightshift. */
+ 1, /* Size (0 = byte, 1 = short, 2 = long). */
+ 16, /* Bitsize. */
+ TRUE, /* PC_relative. */
+ 0, /* Bitpos. */
+ complain_overflow_bitfield, /* Complain_on_overflow. */
+ v850_elf_reloc, /* Special_function. */
+ "R_V850_16_PCREL", /* Name. */
+ FALSE, /* Partial_inplace. */
+ 0xfffe, /* Src_mask. */
+ 0xfffe, /* Dst_mask. */
+ TRUE), /* PCrel_offset. */
+
+ /* A PC relative 17 bit branch. */
+ HOWTO (R_V850_17_PCREL, /* Type. */
+ 0, /* Rightshift. */
+ 2, /* Size (0 = byte, 1 = short, 2 = long). */
+ 17, /* Bitsize. */
+ TRUE, /* PC_relative. */
+ 0, /* Bitpos. */
+ complain_overflow_bitfield, /* Complain_on_overflow. */
+ v850_elf_reloc, /* Special_function. */
+ "R_V850_17_PCREL", /* Name. */
+ FALSE, /* Partial_inplace. */
+ 0x0010fffe, /* Src_mask. */
+ 0x0010fffe, /* Dst_mask. */
+ TRUE), /* PCrel_offset. */
+
+ /* A 23bit offset ld/st. */
+ HOWTO (R_V850_23, /* type. */
+ 0, /* rightshift. */
+ 2, /* size (0 = byte, 1 = short, 2 = long). */
+ 23, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_dont, /* complain_on_overflow. */
+ v850_elf_reloc, /* special_function. */
+ "R_V850_23", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xffff07f0, /* src_mask. */
+ 0xffff07f0, /* dst_mask. */
+ FALSE), /* pcrel_offset. */
+
+ /* A PC relative 32 bit branch. */
+ HOWTO (R_V850_32_PCREL, /* type. */
+ 1, /* rightshift. */
+ 2, /* size (0 = byte, 1 = short, 2 = long). */
+ 32, /* bitsize. */
+ TRUE, /* pc_relative. */
+ 1, /* bitpos. */
+ complain_overflow_signed, /* complain_on_overflow. */
+ v850_elf_reloc, /* special_function. */
+ "R_V850_32_PCREL", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xfffffffe, /* src_mask. */
+ 0xfffffffe, /* dst_mask. */
+ TRUE), /* pcrel_offset. */
+
+ /* A absolute 32 bit branch. */
+ HOWTO (R_V850_32_ABS, /* type. */
+ 1, /* rightshift. */
+ 2, /* size (0 = byte, 1 = short, 2 = long). */
+ 32, /* bitsize. */
+ TRUE, /* pc_relative. */
+ 1, /* bitpos. */
+ complain_overflow_signed, /* complain_on_overflow. */
+ v850_elf_reloc, /* special_function. */
+ "R_V850_32_ABS", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xfffffffe, /* src_mask. */
+ 0xfffffffe, /* dst_mask. */
+ FALSE), /* pcrel_offset. */
+
+ /* High 16 bits of symbol value. */
+ HOWTO (R_V850_HI16, /* Type. */
+ 0, /* Rightshift. */
+ 1, /* Size (0 = byte, 1 = short, 2 = long). */
+ 16, /* Bitsize. */
+ FALSE, /* PC_relative. */
+ 0, /* Bitpos. */
+ complain_overflow_dont, /* Complain_on_overflow. */
+ v850_elf_reloc, /* Special_function. */
+ "R_V850_HI16", /* Name. */
+ FALSE, /* Partial_inplace. */
+ 0xffff, /* Src_mask. */
+ 0xffff, /* Dst_mask. */
+ FALSE), /* PCrel_offset. */
+
+ /* Low 16 bits of symbol value. */
+ HOWTO (R_V850_16_S1, /* type. */
+ 1, /* rightshift. */
+ 1, /* size (0 = byte, 1 = short, 2 = long). */
+ 16, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 1, /* bitpos. */
+ complain_overflow_dont, /* complain_on_overflow. */
+ v850_elf_reloc, /* special_function. */
+ "R_V850_16_S1", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xfffe, /* src_mask. */
+ 0xfffe, /* dst_mask. */
+ FALSE), /* pcrel_offset. */
+
+ /* Low 16 bits of symbol value. */
+ HOWTO (R_V850_LO16_S1, /* type. */
+ 1, /* rightshift. */
+ 1, /* size (0 = byte, 1 = short, 2 = long). */
+ 16, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 1, /* bitpos. */
+ complain_overflow_dont, /* complain_on_overflow. */
+ v850_elf_reloc, /* special_function. */
+ "R_V850_LO16_S1", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xfffe, /* src_mask. */
+ 0xfffe, /* dst_mask. */
+ FALSE), /* pcrel_offset. */
+
+ /* 16 bit offset from the call table base pointer. */
+ HOWTO (R_V850_CALLT_15_16_OFFSET, /* type. */
+ 1, /* rightshift. */
+ 1, /* size (0 = byte, 1 = short, 2 = long). */
+ 16, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 1, /* bitpos. */
+ complain_overflow_dont, /* complain_on_overflow. */
+ v850_elf_reloc, /* special_function. */
+ "R_V850_CALLT_15_16_OFFSET", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xfffe, /* src_mask. */
+ 0xfffe, /* dst_mask. */
+ FALSE), /* pcrel_offset. */
+
+ /* Like R_V850_32 PCREL, but referring to the GOT table entry for
+ the symbol. */
+ HOWTO (R_V850_32_GOTPCREL, /* type. */
+ 0, /* rightshift. */
+ 2, /* size (0 = byte, 1 = short, 2 = long). */
+ 32, /* bitsize. */
+ TRUE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_unsigned, /* complain_on_overflow. */
+ v850_elf_reloc, /* special_function. */
+ "R_V850_32_GOTPCREL", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xffffffff, /* src_mask. */
+ 0xffffffff, /* dst_mask. */
+ TRUE), /* pcrel_offset. */
+
+ /* Like R_V850_SDA_, but referring to the GOT table entry for
+ the symbol. */
+ HOWTO (R_V850_16_GOT, /* type. */
+ 0, /* rightshift. */
+ 2, /* size (0 = byte, 1 = short, 2 = long). */
+ 16, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_unsigned, /* complain_on_overflow. */
+ bfd_elf_generic_reloc, /* special_function. */
+ "R_V850_16_GOT", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xffff, /* src_mask. */
+ 0xffff, /* dst_mask. */
+ FALSE), /* pcrel_offset. */
+
+ HOWTO (R_V850_32_GOT, /* type. */
+ 0, /* rightshift. */
+ 2, /* size (0 = byte, 1 = short, 2 = long). */
+ 32, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_unsigned, /* complain_on_overflow. */
+ bfd_elf_generic_reloc, /* special_function. */
+ "R_V850_32_GOT", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xffffffff, /* src_mask. */
+ 0xffffffff, /* dst_mask. */
+ FALSE), /* pcrel_offset. */
+
+ /* Like R_V850_22_PCREL, but referring to the procedure linkage table
+ entry for the symbol. */
+ HOWTO (R_V850_22_PLT, /* type. */
+ 1, /* rightshift. */
+ 2, /* size (0 = byte, 1 = short, 2 = long). */
+ 22, /* bitsize. */
+ TRUE, /* pc_relative. */
+ 7, /* bitpos. */
+ complain_overflow_signed, /* complain_on_overflow. */
+ bfd_elf_generic_reloc, /* special_function. */
+ "R_V850_22_PLT", /* name. */
+ FALSE, /* partial_inplace. */
+ 0x07ffff80, /* src_mask. */
+ 0x07ffff80, /* dst_mask. */
+ TRUE), /* pcrel_offset. */
+
+ HOWTO (R_V850_32_PLT, /* type. */
+ 1, /* rightshift. */
+ 2, /* size (0 = byte, 1 = short, 2 = long). */
+ 32, /* bitsize. */
+ TRUE, /* pc_relative. */
+ 1, /* bitpos. */
+ complain_overflow_signed, /* complain_on_overflow. */
+ bfd_elf_generic_reloc, /* special_function. */
+ "R_V850_32_PLT", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xffffffff, /* src_mask. */
+ 0xffffffff, /* dst_mask. */
+ TRUE), /* pcrel_offset. */
+
+ /* This is used only by the dynamic linker. The symbol should exist
+ both in the object being run and in some shared library. The
+ dynamic linker copies the data addressed by the symbol from the
+ shared library into the object, because the object being
+ run has to have the data at some particular address. */
+ HOWTO (R_V850_COPY, /* type. */
+ 0, /* rightshift. */
+ 2, /* size (0 = byte, 1 = short, 2 = long). */
+ 32, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_bitfield, /* complain_on_overflow. */
+ bfd_elf_generic_reloc, /* special_function. */
+ "R_V850_COPY", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xffffffff, /* src_mask. */
+ 0xffffffff, /* dst_mask. */
+ FALSE), /* pcrel_offset. */
+
+ /* Like R_M32R_24, but used when setting global offset table
+ entries. */
+ HOWTO (R_V850_GLOB_DAT, /* type. */
+ 0, /* rightshift. */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_bitfield, /* complain_on_overflow. */
+ bfd_elf_generic_reloc, /* special_function. */
+ "R_V850_GLOB_DAT", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xffffffff, /* src_mask. */
+ 0xffffffff, /* dst_mask. */
+ FALSE), /* pcrel_offset. */
+
+ /* Marks a procedure linkage table entry for a symbol. */
+ HOWTO (R_V850_JMP_SLOT, /* type. */
+ 0, /* rightshift. */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_bitfield, /* complain_on_overflow. */
+ bfd_elf_generic_reloc, /* special_function. */
+ "R_V850_JMP_SLOT", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xffffffff, /* src_mask. */
+ 0xffffffff, /* dst_mask. */
+ FALSE), /* pcrel_offset. */
+
+ /* Used only by the dynamic linker. When the object is run, this
+ longword is set to the load address of the object, plus the
+ addend. */
+ HOWTO (R_V850_RELATIVE, /* type. */
+ 0, /* rightshift. */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_bitfield, /* complain_on_overflow. */
+ bfd_elf_generic_reloc, /* special_function. */
+ "R_V850_RELATIVE", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xffffffff, /* src_mask. */
+ 0xffffffff, /* dst_mask. */
+ FALSE), /* pcrel_offset. */
+
+ HOWTO (R_V850_16_GOTOFF, /* type. */
+ 0, /* rightshift. */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_bitfield, /* complain_on_overflow. */
+ bfd_elf_generic_reloc, /* special_function. */
+ "R_V850_16_GOTOFF", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xffff, /* src_mask. */
+ 0xffff, /* dst_mask. */
+ FALSE), /* pcrel_offset. */
+
+ HOWTO (R_V850_32_GOTOFF, /* type. */
+ 0, /* rightshift. */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_bitfield, /* complain_on_overflow. */
+ bfd_elf_generic_reloc, /* special_function. */
+ "R_V850_32_GOTOFF", /* name. */
+ FALSE, /* partial_inplace. */
+ 0xffffffff, /* src_mask. */
+ 0xffffffff, /* dst_mask. */
+ FALSE), /* pcrel_offset. */
+
+ HOWTO (R_V850_CODE, /* type. */
+ 0, /* rightshift. */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_unsigned, /* complain_on_overflow. */
+ v850_elf_ignore_reloc, /* special_function. */
+ "R_V850_CODE", /* name. */
+ FALSE, /* partial_inplace. */
+ 0, /* src_mask. */
+ 0, /* dst_mask. */
+ TRUE), /* pcrel_offset. */
+
+ HOWTO (R_V850_DATA, /* type. */
+ 0, /* rightshift. */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 0, /* bitsize. */
+ FALSE, /* pc_relative. */
+ 0, /* bitpos. */
+ complain_overflow_unsigned, /* complain_on_overflow. */
+ v850_elf_ignore_reloc, /* special_function. */
+ "R_V850_DATA", /* name. */
+ FALSE, /* partial_inplace. */
+ 0, /* src_mask. */
+ 0, /* dst_mask. */
+ TRUE), /* pcrel_offset. */
+
};
/* Map BFD reloc types to V850 ELF reloc types. */
@@ -1280,16 +1688,16 @@ struct v850_elf_reloc_map
static const struct v850_elf_reloc_map v850_elf_reloc_map[] =
{
- { BFD_RELOC_NONE, R_V850_NONE },
- { BFD_RELOC_V850_9_PCREL, R_V850_9_PCREL },
- { BFD_RELOC_V850_22_PCREL, R_V850_22_PCREL },
- { BFD_RELOC_HI16_S, R_V850_HI16_S },
- { BFD_RELOC_HI16, R_V850_HI16 },
- { BFD_RELOC_LO16, R_V850_LO16 },
- { BFD_RELOC_32, R_V850_ABS32 },
- { BFD_RELOC_32_PCREL, R_V850_REL32 },
- { BFD_RELOC_16, R_V850_16 },
- { BFD_RELOC_8, R_V850_8 },
+ { BFD_RELOC_NONE, R_V850_NONE },
+ { BFD_RELOC_V850_9_PCREL, R_V850_9_PCREL },
+ { BFD_RELOC_V850_22_PCREL, R_V850_22_PCREL },
+ { BFD_RELOC_HI16_S, R_V850_HI16_S },
+ { BFD_RELOC_HI16, R_V850_HI16 },
+ { BFD_RELOC_LO16, R_V850_LO16 },
+ { BFD_RELOC_32, R_V850_ABS32 },
+ { BFD_RELOC_32_PCREL, R_V850_REL32 },
+ { BFD_RELOC_16, R_V850_16 },
+ { BFD_RELOC_8, R_V850_8 },
{ BFD_RELOC_V850_SDA_16_16_OFFSET, R_V850_SDA_16_16_OFFSET },
{ BFD_RELOC_V850_SDA_15_16_OFFSET, R_V850_SDA_15_16_OFFSET },
{ BFD_RELOC_V850_ZDA_16_16_OFFSET, R_V850_ZDA_16_16_OFFSET },
@@ -1310,7 +1718,28 @@ static const struct v850_elf_reloc_map v850_elf_reloc_map[] =
{ BFD_RELOC_V850_LONGCALL, R_V850_LONGCALL },
{ BFD_RELOC_V850_LONGJUMP, R_V850_LONGJUMP },
{ BFD_RELOC_V850_ALIGN, R_V850_ALIGN },
-
+ { BFD_RELOC_V850_16_PCREL, R_V850_16_PCREL },
+ { BFD_RELOC_V850_17_PCREL, R_V850_17_PCREL },
+ { BFD_RELOC_V850_23, R_V850_23 },
+ { BFD_RELOC_V850_32_PCREL, R_V850_32_PCREL },
+ { BFD_RELOC_V850_32_ABS, R_V850_32_ABS },
+ { BFD_RELOC_V850_16_SPLIT_OFFSET, R_V850_HI16 },
+ { BFD_RELOC_V850_16_S1, R_V850_16_S1 },
+ { BFD_RELOC_V850_LO16_S1, R_V850_LO16_S1 },
+ { BFD_RELOC_V850_CALLT_15_16_OFFSET, R_V850_CALLT_15_16_OFFSET },
+ { BFD_RELOC_V850_32_GOTPCREL, R_V850_32_GOTPCREL },
+ { BFD_RELOC_V850_16_GOT, R_V850_16_GOT },
+ { BFD_RELOC_V850_32_GOT, R_V850_32_GOT },
+ { BFD_RELOC_V850_22_PLT_PCREL, R_V850_22_PLT },
+ { BFD_RELOC_V850_32_PLT_PCREL, R_V850_32_PLT },
+ { BFD_RELOC_V850_COPY, R_V850_COPY },
+ { BFD_RELOC_V850_GLOB_DAT, R_V850_GLOB_DAT },
+ { BFD_RELOC_V850_JMP_SLOT, R_V850_JMP_SLOT },
+ { BFD_RELOC_V850_RELATIVE, R_V850_RELATIVE },
+ { BFD_RELOC_V850_16_GOTOFF, R_V850_16_GOTOFF },
+ { BFD_RELOC_V850_32_GOTOFF, R_V850_32_GOTOFF },
+ { BFD_RELOC_V850_CODE, R_V850_CODE },
+ { BFD_RELOC_V850_DATA, R_V850_DATA },
};
/* Map a bfd relocation into the appropriate howto structure. */
@@ -1417,28 +1846,54 @@ v850_elf_final_link_relocate (reloc_howto_type *howto,
value -= offset;
break;
+ case R_V850_16_PCREL:
+ value -= (input_section->output_section->vma
+ + input_section->output_offset
+ + offset);
+
+ /* If the sign extension will corrupt the value then we have overflowed. */
+ if ((value & 0xffff0000) != 0xffff0000)
+ return bfd_reloc_overflow;
+
+ break;
+
+ case R_V850_17_PCREL:
+ value -= (input_section->output_section->vma
+ + input_section->output_offset
+ + offset);
+
+ /* If the sign extension will corrupt the value then we have overflowed. */
+ if (((value & 0xffff0000) != 0x0) && ((value & 0xffff0000) != 0xffff0000))
+ return bfd_reloc_overflow;
+
+ value = SEXT17 (value);
+ break;
+
case R_V850_22_PCREL:
value -= (input_section->output_section->vma
+ input_section->output_offset
+ offset);
/* If the sign extension will corrupt the value then we have overflowed. */
- if (((value & 0xff000000) != 0x0) && ((value & 0xff000000) != 0xff000000))
+ if (((value & 0xffe00000) != 0x0) && ((value & 0xffe00000) != 0xffe00000))
return bfd_reloc_overflow;
- /* Only the bottom 24 bits of the PC are valid. */
- value = SEXT24 (value);
+ /* Only the bottom 22 bits of the PC are valid. */
+ value = SEXT22 (value);
break;
- case R_V850_REL32:
+ case R_V850_32_PCREL:
value -= (input_section->output_section->vma
+ input_section->output_offset
+ offset);
break;
+ case R_V850_32_ABS:
+ case R_V850_23:
case R_V850_HI16_S:
case R_V850_HI16:
case R_V850_LO16:
+ case R_V850_LO16_S1:
case R_V850_LO16_SPLIT_OFFSET:
case R_V850_16:
case R_V850_ABS32:
@@ -1481,10 +1936,10 @@ v850_elf_final_link_relocate (reloc_howto_type *howto,
case R_V850_TDA_4_4_OFFSET:
case R_V850_TDA_4_5_OFFSET:
- case R_V850_TDA_16_16_OFFSET:
case R_V850_TDA_7_7_OFFSET:
case R_V850_TDA_7_8_OFFSET:
case R_V850_TDA_6_8_OFFSET:
+ case R_V850_TDA_16_16_OFFSET:
{
unsigned long ep;
struct bfd_link_hash_entry * h;
@@ -1521,6 +1976,7 @@ v850_elf_final_link_relocate (reloc_howto_type *howto,
}
break;
+ case R_V850_CALLT_15_16_OFFSET:
case R_V850_CALLT_16_16_OFFSET:
{
unsigned long ctbp;
@@ -1766,6 +2222,12 @@ v850_elf_object_p (bfd *abfd)
case E_V850E1_ARCH:
bfd_default_set_arch_mach (abfd, bfd_arch_v850, bfd_mach_v850e1);
break;
+ case E_V850E2_ARCH:
+ bfd_default_set_arch_mach (abfd, bfd_arch_v850, bfd_mach_v850e2);
+ break;
+ case E_V850E2V3_ARCH:
+ bfd_default_set_arch_mach (abfd, bfd_arch_v850, bfd_mach_v850e2v3);
+ break;
}
return TRUE;
}
@@ -1784,6 +2246,8 @@ v850_elf_final_write_processing (bfd *abfd,
case bfd_mach_v850: val = E_V850_ARCH; break;
case bfd_mach_v850e: val = E_V850E_ARCH; break;
case bfd_mach_v850e1: val = E_V850E1_ARCH; break;
+ case bfd_mach_v850e2: val = E_V850E2_ARCH; break;
+ case bfd_mach_v850e2v3: val = E_V850E2V3_ARCH; break;
}
elf_elfheader (abfd)->e_flags &=~ EF_V850_ARCH;
@@ -1847,20 +2311,40 @@ v850_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd)
if ((in_flags & EF_V850_ARCH) != (out_flags & EF_V850_ARCH)
&& (in_flags & EF_V850_ARCH) != E_V850_ARCH)
{
+
/* Allow v850e1 binaries to be linked with v850e binaries.
- Set the output binary to v850e. */
+ Set the output binary to v850e. */
if ((in_flags & EF_V850_ARCH) == E_V850E1_ARCH
- && (out_flags & EF_V850_ARCH) == E_V850E_ARCH)
- return TRUE;
+ && (out_flags & EF_V850_ARCH) == E_V850E_ARCH)
+ return TRUE;
- if ((in_flags & EF_V850_ARCH) == E_V850E_ARCH
- && (out_flags & EF_V850_ARCH) == E_V850E1_ARCH)
+ if ((in_flags & EF_V850_ARCH) == E_V850_ARCH
+ && (out_flags & EF_V850_ARCH) == E_V850E_ARCH)
{
elf_elfheader (obfd)->e_flags =
((out_flags & ~ EF_V850_ARCH) | E_V850E_ARCH);
return TRUE;
}
+ if (((in_flags & EF_V850_ARCH) == E_V850_ARCH
+ || (in_flags & EF_V850_ARCH) == E_V850E_ARCH)
+ && (out_flags & EF_V850_ARCH) == E_V850E2_ARCH)
+ {
+ elf_elfheader (obfd)->e_flags =
+ ((out_flags & ~ EF_V850_ARCH) | E_V850E2_ARCH);
+ return TRUE;
+ }
+
+ if (((in_flags & EF_V850_ARCH) == E_V850_ARCH
+ || (in_flags & EF_V850_ARCH) == E_V850E_ARCH
+ || (in_flags & EF_V850_ARCH) == E_V850E2_ARCH)
+ && (out_flags & EF_V850_ARCH) == E_V850E2V3_ARCH)
+ {
+ elf_elfheader (obfd)->e_flags =
+ ((out_flags & ~ EF_V850_ARCH) | E_V850E2V3_ARCH);
+ return TRUE;
+ }
+
_bfd_error_handler (_("%B: Architecture mismatch with previous modules"),
ibfd);
}
@@ -1879,7 +2363,7 @@ v850_elf_print_private_bfd_data (bfd *abfd, void * ptr)
_bfd_elf_print_private_bfd_data (abfd, ptr);
- /* xgettext:c-format */
+ /* xgettext:c-format. */
fprintf (file, _("private flags = %lx: "), elf_elfheader (abfd)->e_flags);
switch (elf_elfheader (abfd)->e_flags & EF_V850_ARCH)
@@ -1888,6 +2372,8 @@ v850_elf_print_private_bfd_data (bfd *abfd, void * ptr)
case E_V850_ARCH: fprintf (file, _("v850 architecture")); break;
case E_V850E_ARCH: fprintf (file, _("v850e architecture")); break;
case E_V850E1_ARCH: fprintf (file, _("v850e1 architecture")); break;
+ case E_V850E2_ARCH: fprintf (file, _("v850e2 architecture")); break;
+ case E_V850E2V3_ARCH: fprintf (file, _("v850e2v3 architecture")); break;
}
fputc ('\n', file);
@@ -1949,7 +2435,7 @@ v850_elf_symbol_processing (bfd *abfd, asymbol *asym)
FIXME: Should we alter the st_shndx field as well ? */
if (indx < elf_numsections (abfd))
- switch (elf_elfsections(abfd)[indx]->sh_type)
+ switch (elf_elfsections (abfd)[indx]->sh_type)
{
case SHT_V850_SCOMMON:
indx = SHN_V850_SCOMMON;
@@ -2046,7 +2532,7 @@ v850_elf_add_symbol_hook (bfd *abfd,
FIXME: Should we alter the st_shndx field as well ? */
if (indx < elf_numsections (abfd))
- switch (elf_elfsections(abfd)[indx]->sh_type)
+ switch (elf_elfsections (abfd)[indx]->sh_type)
{
case SHT_V850_SCOMMON:
indx = SHN_V850_SCOMMON;
@@ -2376,22 +2862,22 @@ v850_elf_relax_delete_bytes (bfd *abfd,
}
#define NOP_OPCODE (0x0000)
-#define MOVHI 0x0640 /* 4byte */
+#define MOVHI 0x0640 /* 4byte. */
#define MOVHI_MASK 0x07e0
-#define MOVHI_R1(insn) ((insn) & 0x1f) /* 4byte */
+#define MOVHI_R1(insn) ((insn) & 0x1f) /* 4byte. */
#define MOVHI_R2(insn) ((insn) >> 11)
-#define MOVEA 0x0620 /* 2byte */
+#define MOVEA 0x0620 /* 2byte. */
#define MOVEA_MASK 0x07e0
#define MOVEA_R1(insn) ((insn) & 0x1f)
#define MOVEA_R2(insn) ((insn) >> 11)
-#define JARL_4 0x00040780 /* 4byte */
+#define JARL_4 0x00040780 /* 4byte. */
#define JARL_4_MASK 0xFFFF07FF
#define JARL_R2(insn) (int)(((insn) & (~JARL_4_MASK)) >> 11)
-#define ADD_I 0x0240 /* 2byte */
+#define ADD_I 0x0240 /* 2byte. */
#define ADD_I_MASK 0x07e0
-#define ADD_I5(insn) ((((insn) & 0x001f) << 11) >> 11) /* 2byte */
+#define ADD_I5(insn) ((((insn) & 0x001f) << 11) >> 11) /* 2byte. */
#define ADD_R2(insn) ((insn) >> 11)
-#define JMP_R 0x0060 /* 2byte */
+#define JMP_R 0x0060 /* 2byte. */
#define JMP_R_MASK 0xFFE0
#define JMP_R1(insn) ((insn) & 0x1f)
View
34 bfd/libbfd.h
@@ -1636,6 +1636,28 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_V850_LONGJUMP",
"BFD_RELOC_V850_ALIGN",
"BFD_RELOC_V850_LO16_SPLIT_OFFSET",
+ "BFD_RELOC_V850_16_PCREL",
+ "BFD_RELOC_V850_17_PCREL",
+ "BFD_RELOC_V850_23",
+ "BFD_RELOC_V850_32_PCREL",
+ "BFD_RELOC_V850_32_ABS",
+ "BFD_RELOC_V850_16_SPLIT_OFFSET",
+ "BFD_RELOC_V850_16_S1",
+ "BFD_RELOC_V850_LO16_S1",
+ "BFD_RELOC_V850_CALLT_15_16_OFFSET",
+ "BFD_RELOC_V850_32_GOTPCREL",
+ "BFD_RELOC_V850_16_GOT",
+ "BFD_RELOC_V850_32_GOT",
+ "BFD_RELOC_V850_22_PLT_PCREL",
+ "BFD_RELOC_V850_32_PLT_PCREL",
+ "BFD_RELOC_V850_COPY",
+ "BFD_RELOC_V850_GLOB_DAT",
+ "BFD_RELOC_V850_JMP_SLOT",
+ "BFD_RELOC_V850_RELATIVE",
+ "BFD_RELOC_V850_16_GOTOFF",
+ "BFD_RELOC_V850_32_GOTOFF",
+ "BFD_RELOC_V850_CODE",
+ "BFD_RELOC_V850_DATA",
"BFD_RELOC_MN10300_32_PCREL",
"BFD_RELOC_MN10300_16_PCREL",
"BFD_RELOC_TIC30_LDP",
@@ -2243,12 +2265,12 @@ bfd_boolean bfd_generic_merge_sections
(bfd *, struct bfd_link_info *);
bfd_byte *bfd_generic_get_relocated_section_contents
- (bfd *,
- struct bfd_link_info *,
- struct bfd_link_order *,
- bfd_byte *,
- bfd_boolean,
- asymbol **);
+ (bfd *abfd,
+ struct bfd_link_info *link_info,
+ struct bfd_link_order *link_order,
+ bfd_byte *data,
+ bfd_boolean relocatable,
+ asymbol **symbols);
/* Extracted from archures.c. */
extern const bfd_arch_info_type bfd_default_arch_struct;
View
88 bfd/reloc.c
@@ -3723,6 +3723,94 @@ ENUMDOC
This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
instructions.
ENUM
+ BFD_RELOC_V850_16_PCREL
+ENUMDOC
+ This is a 16-bit reloc.
+ENUM
+ BFD_RELOC_V850_17_PCREL
+ENUMDOC
+ This is a 17-bit reloc.
+ENUM
+ BFD_RELOC_V850_23
+ENUMDOC
+ This is a 23-bit reloc.
+ENUM
+ BFD_RELOC_V850_32_PCREL
+ENUMDOC
+ This is a 32-bit reloc.
+ENUM
+ BFD_RELOC_V850_32_ABS
+ENUMDOC
+ This is a 32-bit reloc.
+ENUM
+ BFD_RELOC_V850_16_SPLIT_OFFSET
+ENUMDOC
+ This is a 16-bit reloc.
+ENUM
+ BFD_RELOC_V850_16_S1
+ENUMDOC
+ This is a 16-bit reloc.
+ENUM
+ BFD_RELOC_V850_LO16_S1
+ENUMDOC
+ Low 16 bits. 16 bit shifted by 1.
+ENUM
+ BFD_RELOC_V850_CALLT_15_16_OFFSET
+ENUMDOC
+ This is a 16 bit offset from the call table base pointer.
+ENUM
+ BFD_RELOC_V850_32_GOTPCREL
+ENUMDOC
+ DSO relocations.
+ENUM
+ BFD_RELOC_V850_16_GOT
+ENUMDOC
+ DSO relocations.
+ENUM
+ BFD_RELOC_V850_32_GOT
+ENUMDOC
+ DSO relocations.
+ENUM
+ BFD_RELOC_V850_22_PLT_PCREL
+ENUMDOC
+ DSO relocations.
+ENUM
+ BFD_RELOC_V850_32_PLT_PCREL
+ENUMDOC
+ DSO relocations.
+ENUM
+ BFD_RELOC_V850_COPY
+ENUMDOC
+ DSO relocations.
+ENUM
+ BFD_RELOC_V850_GLOB_DAT
+ENUMDOC
+ DSO relocations.
+ENUM
+ BFD_RELOC_V850_JMP_SLOT
+ENUMDOC
+ DSO relocations.
+ENUM
+ BFD_RELOC_V850_RELATIVE
+ENUMDOC
+ DSO relocations.
+ENUM
+ BFD_RELOC_V850_16_GOTOFF
+ENUMDOC
+ DSO relocations.
+ENUM
+ BFD_RELOC_V850_32_GOTOFF
+ENUMDOC
+ DSO relocations.
+ENUM
+ BFD_RELOC_V850_CODE
+ENUMDOC
+ start code.
+ENUM
+ BFD_RELOC_V850_DATA
+ENUMDOC
+ start data in text.
+ENUM
BFD_RELOC_MN10300_32_PCREL
ENUMDOC
This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
View
5 binutils/ChangeLog
@@ -1,3 +1,8 @@
+2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
+ Ina Pandit <ina.pandit@kpitcummins.com>
+
+ * binutils/readelf.c: Add support for V850E2 and V850E2V3.
+
2010-07-22 Alan Modra <amodra@gmail.com>
* readelf.c: Add Moxie support.
View
10 binutils/readelf.c
@@ -2352,8 +2352,14 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
case EM_CYGNUS_V850:
switch (e_flags & EF_V850_ARCH)
{
- case E_V850E1_ARCH:
- strcat (buf, ", v850e1");
+ case E_V850E2V3_ARCH:
+ strcat (buf, ", v850e2v3");
+ break;
+ case E_V850E2_ARCH:
+ strcat (buf, ", v850e2");
+ break;
+ case E_V850E1_ARCH:
+ strcat (buf, ", v850e1");
break;
case E_V850E_ARCH:
strcat (buf, ", v850e");
View
10 configure
@@ -3730,14 +3730,8 @@ case "${target}" in
v810-*-*)
noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}"
;;
- v850-*-*)
- noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
- ;;
- v850e-*-*)
- noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
- ;;
- v850ea-*-*)
- noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
+ v850*-*-*)
+ noconfigdirs="$noconfigdirs ${libgcj}"
;;
vax-*-vms)
noconfigdirs="$noconfigdirs bfd binutils gdb ld target-newlib opcodes target-libgloss ${libgcj}"
View
10 configure.ac
@@ -967,14 +967,8 @@ case "${target}" in
v810-*-*)
noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}"
;;
- v850-*-*)
- noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
- ;;
- v850e-*-*)
- noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
- ;;
- v850ea-*-*)
- noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
+ v850*-*-*)
+ noconfigdirs="$noconfigdirs ${libgcj}"
;;
vax-*-vms)
noconfigdirs="$noconfigdirs bfd binutils gdb ld target-newlib opcodes target-libgloss ${libgcj}"
View
47 gas/ChangeLog
@@ -1,3 +1,50 @@
+2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
+ Ina Pandit <ina.pandit@kpitcummins.com>
+
+ * config/tc-v850.c: Update processor_mask.
+ (reg_name): Update the structure to use processors field.
+ (md_relax_table): Define SUBYPTE_COND_9_22, SUBYPTE_SA_9_22,
+ SUBYPTE_UNCOND_9_22, SUBYPTE_COND_9_22_32, SUBYPTE_SA_9_22_32,
+ SUBYPTE_UNCOND_9_22_32, SUBYPTE_COND_9_17_22,
+ SUBYPTE_SA_9_17_22, SUBYPTE_COND_9_17_22_32 and
+ SUBYPTE_SA_9_17_22_32.
+ (set_machine): Add support for V850E2 and V850E2V3.
+ (md_pseudo_table): Likewise.
+ (pre_defined_registers): Update pre defined registers suitable
+ for each family of registers.
+ (system_registers): Likewise.
+ (cc_names): Update the condition code.
+ (float_cc_names): Update the condition code for float.
+ (reg_name_search): Update based on current modifications.
+ (register_name): Likewise.
+ (system_register_name): Update to support new system registers
+ and supported families.
+ (cc_name): Update to support new condition codes.
+ (float_cc_name): New function to support float condition codes.
+ (parse_register_list): Update to support newly added registers.
+ (md_show_usage): Define support for V850E2 and V850E2V3 targets.
+ Also support added for disp-size-default-22, disp-size-default-32,
+ mextension, mno-bcond17 and mno-stld23.
+ (md_parse_option): Implement the support for above options defined
+ in md_show-usage.
+ (md_convert_frag): Implement support for subtypes defined in
+ md_relax_table to support branch operations.
+ (md_begin): Add support for V850E2 and V850E2V3.
+ (handle_hi016, handle_hi16): new relocation handling functions
+ (handle_lo16, handle_ctoff, handle_sdaoff, handle_zdaoff,
+ handle_tdaoff): Updated relocation handling functions for newly
+ added relocations.
+ (v850_reloc_prefix): Update the relocation handling functions.
+ (v850_insert_operand): Updated the functions with error message
+ parameter and modified the function to use it.
+ (md_assemble): Update according to the latest modifications.
+ (md_apply_fix): Updated the functions with error message parameter
+ and modified the function to use it.
+ (v850_force_relocation): Update with newly added relocations.
+ * configure.tgt: Match all v850 targets.
+ * doc/c-v850.texi: Document the newly added targets.
+ * NEWS: Likewise.
+
2010-07-23 Alan Modra <amodra@gmail.com>
PR gas/11834
View
2 gas/NEWS
@@ -16,6 +16,8 @@
Changes in 2.20:
+* Added support for v850e2 and v850e2v3.
+
* GNU/Linux targets now supports "gnu_unique_object" as a value in the .type
pseudo op. It marks the symbol as being globally unique in the entire
process.
View
1,986 gas/config/tc-v850.c
1,444 additions, 542 deletions not shown because the diff is too large. Please use a local Git client to view these changes.
View
7 gas/configure.tgt
@@ -53,7 +53,6 @@ case ${cpu} in
m680[012346]0) cpu_type=m68k ;;
m6811|m6812|m68hc12) cpu_type=m68hc11 ;;
m683??) cpu_type=m68k ;;
- maxq) cpu_type=maxq ;;
mep) cpu_type=mep endian=little ;;
microblaze*) cpu_type=microblaze ;;
mips*el) cpu_type=mips endian=little ;;
@@ -271,8 +270,6 @@ case ${generic_target} in
m68k-*-openbsd*) fmt=aout em=nbsd bfd_gas=yes ;;
m68k-*-psos*) fmt=elf em=psos;;
- maxq-*-coff) fmt=coff bfd_gas=yes ;;
-
mep-*-elf) fmt=elf ;;
mcore-*-elf) fmt=elf ;;
@@ -403,9 +400,7 @@ case ${generic_target} in
tic54x-*-* | c54x*-*-*) fmt=coff bfd_gas=yes need_libm=yes;;
tic6x-*-*) fmt=elf ;;
- v850-*-*) fmt=elf ;;
- v850e-*-*) fmt=elf ;;
- v850ea-*-*) fmt=elf ;;
+ v850*-*-*) fmt=elf ;;
vax-*-netbsdelf*) fmt=elf em=nbsd ;;
vax-*-linux-*) fmt=elf em=linux ;;
View
24 gas/doc/c-v850.texi
@@ -68,6 +68,18 @@ routines used by the code produced by GCC for all versions of the v850
architecture, together with support routines only used by the V850E
architecture.
+@cindex @code{-mv850e2} command line option, V850
+@item -mv850e2
+Specifies that the assembled code should be marked as being targeted at
+the V850E2 processor. This allows the linker to detect attempts to link
+such code with code assembled for other processors.
+
+@cindex @code{-mv850e2v3} command line option, V850
+@item -mv850e2v3
+Specifies that the assembled code should be marked as being targeted at
+the V850E2V3 processor. This allows the linker to detect attempts to link
+such code with code assembled for other processors.
+
@cindex @code{-mrelax} command line option, V850
@item -mrelax
Enables relaxation. This allows the .longcall and .longjump pseudo
@@ -245,6 +257,18 @@ Specifies that the assembled code should be marked as being targeted at
the V850E1 processor. This allows the linker to detect attempts to link
such code with code assembled for other processors.
+@cindex @code{.v850e2} directive, V850
+@item .v850e2
+Specifies that the assembled code should be marked as being targeted at
+the V850E2 processor. This allows the linker to detect attempts to link
+such code with code assembled for other processors.
+
+@cindex @code{.v850e2v3} directive, V850
+@item .v850e2v3
+Specifies that the assembled code should be marked as being targeted at
+the V850E2V3 processor. This allows the linker to detect attempts to link
+such code with code assembled for other processors.
+
@end table
@node V850 Opcodes
View
7 gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
+ Ina Pandit <ina.pandit@kpitcummins.com>
+
+ * gas/v850/split-lo16.d: Update the "ld" instructions with a space
+ for second operand.
+ * gas/v850/v850e1.d: Likewise.
+
2010-07-22 Alan Modra <amodra@gmail.com>
* gas/arm/mapdir.s: Don't specify attr/type for .fini_array.
View
3 gas/testsuite/gas/all/byte.d
@@ -1,2 +1,5 @@
#name: bad byte directive
#error-output: byte.l
+# The RX target allows quoted ASCII strings inside .byte directives
+# for compatibily with the Renesas assembler.
+#skip: rx-*-*
View
4 gas/testsuite/gas/rx/rx-asm-good.d
@@ -10,8 +10,8 @@ Disassembly of section .text:
0+0108 <mem\+0x8> 66 20[ ]+mov.l[ ]+#2, r0
0+010a <mem\+0xa> 66 10[ ]+mov.l[ ]+#1, r0
0+010c <mem\+0xc> 66 00[ ]+mov.l[ ]+#0, r0
-0+010e <mem\+0xe> 05 f2 fe ff[ ]+bsr.a[ ]+0+0000 <mem-0x100>
-0+0112 <mem\+0x12> 05 ee fe ff[ ]+bsr.a[ ]+0+0000 <mem-0x100>
+0+010e <mem\+0xe> 05 .. .. ..[ ]+bsr.a[ ]+[0-9a-f]+ <mem.0x[0-9a-f]+>
+0+0112 <mem\+0x12> 05 .. .. ..[ ]+bsr.a[ ]+[0-9a-f]+ <mem.0x[0-9a-f]+>
0+0116 <mem\+0x16> 62 65[ ]+add[ ]+#6, r5
0+0118 <mem\+0x18> 72 74 0b 2e[ ]+add[ ]+#0x2e0b, r7, r4
0+011c <mem\+0x1c> ff 2e 00[ ]+add[ ]+r0, r0, r14
View
12 gas/testsuite/gas/v850/split-lo16.d
@@ -7,12 +7,12 @@
2: R_V850_HI16_S foo
4: 01 16 00 00 addi 0, r1, r2
6: R_V850_LO16 foo
- 8: 01 17 00 00 ld\.b 0\[r1\],r2
+ 8: 01 17 00 00 ld\.b 0\[r1\], r2
a: R_V850_LO16 foo
- c: 81 17 01 00 ld\.bu 0\[r1\],r2
+ c: 81 17 01 00 ld\.bu 0\[r1\], r2
c: R_V850_LO16_SPLIT_OFFSET foo
- 10: a1 17 45 23 ld\.bu 9029\[r1\],r2
- 14: 81 17 57 34 ld\.bu 13398\[r1\],r2
- 18: 20 57 01 00 ld.w 0\[r0\],r10
- 1c: 20 57 79 56 ld.w 22136\[r0\],r10
+ 10: a1 17 45 23 ld\.bu 9029\[r1\], r2
+ 14: 81 17 57 34 ld\.bu 13398\[r1\], r2
+ 18: 20 57 01 00 ld.w 0\[r0\], r10
+ 1c: 20 57 79 56 ld.w 22136\[r0\], r10
#pass
View
8 gas/testsuite/gas/v850/v850e1.d
@@ -23,8 +23,8 @@ Disassembly of section .text:
0x0+30 e7 47 82 4a [ ]*divhu r7, r8, r9
0x0+34 ea 5f c2 62 [ ]*divu r10, r11, r12
0x0+38 e0 6f 44 73 [ ]*hsw r13, r14
-0x0+3c a1 17 0d 00 [ ]*ld.bu 13\[r1\],r2
-0x0+40 e3 27 11 00 [ ]*ld.hu 16\[sp\],gp
+0x0+3c a1 17 0d 00 [ ]*ld.bu 13\[r1\], r2
+0x0+40 e3 27 11 00 [ ]*ld.hu 16\[sp\], gp
0x0+44 21 06 78 56 34 12 [ ]*mov 0x12345678, r1
0x0+4a e5 17 40 1a [ ]*mul 5, r2, sp
0x0+4e e1 17 20 1a [ ]*mul r1, r2, sp
@@ -35,8 +35,8 @@ Disassembly of section .text:
0x0+62 a8 07 03 70 [ ]*prepare {r25 - r27}, 20, sp
0x0+66 e1 4f e0 00 [ ]*set1 r9, r1
0x0+6a ea 47 00 02 [ ]*sasf nz, r8
-0x0+6e 60 20 [ ]*sld.bu 0\[ep\],gp
-0x0+70 77 28 [ ]*sld.hu 14\[ep\],r5
+0x0+6e 60 20 [ ]*sld.bu 0\[ep\], gp
+0x0+70 77 28 [ ]*sld.hu 14\[ep\], r5
0x0+72 a1 00 [ ]*sxb r1
0x0+74 e2 00 [ ]*sxh r2
0x0+76 ff 07 e6 00 [ ]*tst1 r0, lp
View
6 include/elf/ChangeLog
@@ -1,3 +1,9 @@
+2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
+ Ina Pandit <ina.pandit@kpitcummins.com>
+
+ * v850.h: Add support for V850E2 and V850E2V3.
+ (v850_reloc_type): Update the newly added relocations
+
2010-07-20 Alan Modra <amodra@gmail.com>
* internal.h (ELF_TBSS_SPECIAL): New macro, extracted from..
View
28 include/elf/v850.h
@@ -40,6 +40,11 @@
/* v850e1 code. */
#define E_V850E1_ARCH 0x20000000
+/* v850e2 code. */
+#define E_V850E2_ARCH 0x30000000
+
+/* v850e2v3 code. */
+#define E_V850E2V3_ARCH 0x40000000
/* Flags for the st_other field. */
#define V850_OTHER_SDA 0x10 /* Symbol had SDA relocations. */
@@ -81,6 +86,29 @@ START_RELOC_NUMBERS (v850_reloc_type)
RELOC_NUMBER (R_V850_ALIGN, 27)
RELOC_NUMBER (R_V850_REL32, 28)
RELOC_NUMBER (R_V850_LO16_SPLIT_OFFSET, 29) /* For ld.bu */
+ RELOC_NUMBER (R_V850_16_PCREL, 30) /* For loop */
+ RELOC_NUMBER (R_V850_17_PCREL, 31) /* For br */
+ RELOC_NUMBER (R_V850_23, 32) /* For 23bit ld.[w,h,hu,b,bu],st.[w,h,b] */
+ RELOC_NUMBER (R_V850_32_PCREL, 33) /* For jr32, jarl32 */
+ RELOC_NUMBER (R_V850_32_ABS, 34) /* For jmp32 */
+ RELOC_NUMBER (R_V850_16_SPLIT_OFFSET, 35) /* For ld.bu */
+ RELOC_NUMBER (R_V850_16_S1, 36) /* For ld.w, ld.h st.w st.h */
+ RELOC_NUMBER (R_V850_LO16_S1, 37) /* For ld.w, ld.h st.w st.h */
+ RELOC_NUMBER (R_V850_CALLT_15_16_OFFSET, 38) /* For ld.w, ld.h, ld.hu, st.w, st.h */
+ RELOC_NUMBER (R_V850_32_GOTPCREL, 39) /* GLOBAL_OFFSET_TABLE from pc */
+ RELOC_NUMBER (R_V850_16_GOT, 40) /* GOT ENTRY from gp */
+ RELOC_NUMBER (R_V850_32_GOT, 41)
+ RELOC_NUMBER (R_V850_22_PLT, 42) /* For jr */
+ RELOC_NUMBER (R_V850_32_PLT, 43) /* For jr32 */
+ RELOC_NUMBER (R_V850_COPY, 44)
+ RELOC_NUMBER (R_V850_GLOB_DAT, 45)
+ RELOC_NUMBER (R_V850_JMP_SLOT, 46)
+ RELOC_NUMBER (R_V850_RELATIVE, 47)
+ RELOC_NUMBER (R_V850_16_GOTOFF, 48) /* From gp */
+ RELOC_NUMBER (R_V850_32_GOTOFF, 49)
+ RELOC_NUMBER (R_V850_CODE, 50)
+ RELOC_NUMBER (R_V850_DATA, 51) /* For loop */
+
END_RELOC_NUMBERS (R_V850_max)
View
18 include/opcode/ChangeLog
@@ -1,3 +1,21 @@
+2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
+ Ina Pandit <ina.pandit@kpitcummins.com>
+
+ * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
+ PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
+ PROCESSOR_V850E2_ALL.
+ Remove PROCESSOR_V850EA support.
+ (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
+ V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
+ V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
+ V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
+ V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
+ V850_OPERAND_PERCENT.
+ Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
+ V850_NOT_R0.
+ Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
+ and V850E_PUSH_POP
+
2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
View
94 include/opcode/v850.h
@@ -55,12 +55,18 @@ struct v850_opcode
};
/* Values for the processors field in the v850_opcode structure. */
+#define PROCESSOR_MASK 0x1f
+#define PROCESSOR_OPTION_EXTENSION (1 << 5) /* Enable extension opcodes. */
+#define PROCESSOR_OPTION_ALIAS (1 << 6) /* Enable alias opcodes. */
#define PROCESSOR_V850 (1 << 0) /* Just the V850. */
-#define PROCESSOR_ALL -1 /* Any processor. */
-#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */
-#define PROCESSOR_NOT_V850 (~ PROCESSOR_V850) /* Any processor except the V850. */
-#define PROCESSOR_V850EA (1 << 2) /* Just the V850EA. */
-#define PROCESSOR_V850E1 (1 << 3) /* Just the V850E1. */
+#define PROCESSOR_ALL PROCESSOR_MASK /* Any processor. */
+#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */
+#define PROCESSOR_NOT_V850 (PROCESSOR_ALL & (~ PROCESSOR_V850)) /* Any processor except the V850. */
+#define PROCESSOR_V850E1 (1 << 2) /* Just the V850E1. */
+#define PROCESSOR_V850E2 (1 << 3) /* Just the V850E2. */
+#define PROCESSOR_V850E2V3 (1 << 4) /* Just the V850E2V3. */
+#define PROCESSOR_V850E2_ALL (PROCESSOR_V850E2 | PROCESSOR_V850E2V3) /* V850E2 & V850E2V3. */
+#define SET_PROCESSOR_MASK(mask,set) ((mask) = ((mask) & ~PROCESSOR_MASK) | (set))
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
@@ -74,7 +80,8 @@ extern const int v850_num_opcodes;
struct v850_operand
{
/* The number of bits in the operand. */
- /* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */
+ /* If this value is -1 then the operand's bits are in a discontinous
+ distribution in the instruction. */
int bits;
/* (bits >= 0): How far the operand is left shifted in the instruction. */
@@ -120,6 +127,8 @@ struct v850_operand
/* One bit syntax flags. */
int flags;
+
+ int default_reloc;
};
/* Elements in the table are retrieved by indexing with values from
@@ -129,39 +138,70 @@ extern const struct v850_operand v850_operands[];
/* Values defined for the flags field of a struct v850_operand. */
-/* This operand names a general purpose register */
+/* This operand names a general purpose register. */
#define V850_OPERAND_REG 0x01
-/* This operand names a system register */
-#define V850_OPERAND_SRG 0x02
+/* This operand is the ep register. */
+#define V850_OPERAND_EP 0x02
-/* This operand names a condition code used in the setf instruction */
-#define V850_OPERAND_CC 0x04
+/* This operand names a system register. */
+#define V850_OPERAND_SRG 0x04
-/* This operand takes signed values */
-#define V850_OPERAND_SIGNED 0x08
+/* Prologue eilogue type instruction, V850E specific. */
+#define V850E_OPERAND_REG_LIST 0x08
-/* This operand is the ep register. */
-#define V850_OPERAND_EP 0x10
+/* This operand names a condition code used in the setf instruction. */
+#define V850_OPERAND_CC 0x10
-/* This operand is a PC displacement */
-#define V850_OPERAND_DISP 0x20
+#define V850_OPERAND_FLOAT_CC 0x20
-/* This is a relaxable operand. Only used for D9->D22 branch relaxing
- right now. We may need others in the future (or maybe handle them like
- promoted operands on the mn10300?) */
-#define V850_OPERAND_RELAX 0x40
+/* This operand names a vector purpose register. */
+#define V850_OPERAND_VREG 0x40
-/* The register specified must not be r0 */
-#define V850_NOT_R0 0x80
+/* 16 bit immediate follows instruction, V850E specific. */
+#define V850E_IMMEDIATE16 0x80
-/* push/pop type instruction, V850E specific. */
-#define V850E_PUSH_POP 0x100
+/* hi16 bit immediate follows instruction, V850E specific. */
+#define V850E_IMMEDIATE16HI 0x100
-/* 16 bit immediate follows instruction, V850E specific. */
-#define V850E_IMMEDIATE16 0x200
+/* 23 bit immediate follows instruction, V850E specific. */
+#define V850E_IMMEDIATE23 0x200
/* 32 bit immediate follows instruction, V850E specific. */
#define V850E_IMMEDIATE32 0x400
+/* This is a relaxable operand. Only used for D9->D22 branch relaxing
+ right now. We may need others in the future (or maybe handle them like
+ promoted operands on the mn10300?). */
+#define V850_OPERAND_RELAX 0x800
+
+/* This operand takes signed values. */
+#define V850_OPERAND_SIGNED 0x1000
+
+/* This operand is a displacement. */
+#define V850_OPERAND_DISP 0x2000
+
+/* This operand is a PC displacement. */
+#define V850_PCREL 0x4000
+
+/* The register specified must be even number. */
+#define V850_REG_EVEN 0x8000
+
+/* The register specified must not be r0. */
+#define V850_NOT_R0 0x20000
+
+/* The register specified must not be 0. */
+#define V850_NOT_IMM0 0x40000
+
+/* The condition code must not be SA CONDITION. */
+#define V850_NOT_SA 0x80000
+
+/* The operand has '!' prefix. */
+#define V850_OPERAND_BANG 0x100000
+
+/* The operand has '%' prefix. */
+#define V850_OPERAND_PERCENT 0x200000
+
+extern int v850_msg_is_out_of_range (const char * msg);
+
#endif /* V850_H */
View
5 ld/ChangeLog
@@ -1,3 +1,8 @@
+2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
+ Ina Pandit <ina.pandit@kpitcummins.com>
+
+ * configure.tgt: Match all v850 targets.
+
2010-07-20 Mike Frysinger <vapier@gentoo.org>
* ld.texinfo (VERSION): Remove "int" from example script and add ";".
View
6 ld/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
+ Ina Pandit <ina.pandit@kpitcummins.com>
+
+ * ld-v850/split-lo16.d: Update the "ld" instructions with a space
+ for second operand.
+
2010-07-20 Alan Modra <amodra@gmail.com>
* ld-powerpc/tlsexe.r: Update.
View
14 ld/testsuite/ld-v850/split-lo16.d
@@ -5,22 +5,22 @@
00010000 <.*>:
10000: 40 0e 34 12 movhi 4660, r0, r1
10004: 01 16 78 56 addi 22136, r1, r2
- 10008: 81 17 79 56 ld\.bu 22136\[r1\],r2
+ 10008: 81 17 79 56 ld\.bu 22136\[r1\], r2
1000c: 40 0e 36 12 movhi 4662, r0, r1
10010: 01 16 78 d8 addi -10120, r1, r2
- 10014: 81 17 79 d8 ld\.bu -10120\[r1\],r2
+ 10014: 81 17 79 d8 ld\.bu -10120\[r1\], r2
10018: 40 0e 12 00 movhi 18, r0, r1
- 1001c: 81 17 57 34 ld\.bu 13398\[r1\],r2
+ 1001c: 81 17 57 34 ld\.bu 13398\[r1\], r2
10020: 01 16 56 34 addi 13398, r1, r2
10024: 40 0e 14 00 movhi 20, r0, r1
- 10028: 81 17 57 b6 ld\.bu -18858\[r1\],r2
+ 10028: 81 17 57 b6 ld\.bu -18858\[r1\], r2
1002c: 01 16 56 b6 addi -18858, r1, r2
10030: 40 0e 79 56 movhi 22137, r0, r1
10034: 01 16 bc 9a addi -25924, r1, r2
- 10038: 81 17 bd 9a ld\.bu -25924\[r1\],r2
+ 10038: 81 17 bd 9a ld\.bu -25924\[r1\], r2
1003c: 40 0e 9b 78 movhi 30875, r0, r1
- 10040: 81 17 df bc ld\.bu -17186\[r1\],r2
+ 10040: 81 17 df bc ld\.bu -17186\[r1\], r2
10044: 01 16 de bc addi -17186, r1, r2
10048: 40 0e 45 23 movhi 9029, r0, r1
- 1004c: a1 17 89 67 ld\.bu 26505\[r1\],r2
+ 1004c: a1 17 89 67 ld\.bu 26505\[r1\], r2
#pass
View
23 opcodes/ChangeLog
@@ -1,3 +1,26 @@
+2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
+ Ina Pandit <ina.pandit@kpitcummins.com>
+
+ * v850-dis.c (v850_sreg_names): Updated structure for system
+ registers.
+ (float_cc_names): new structure for condition codes.
+ (print_value): Update the function that prints value.
+ (get_operand_value): New function to get the operand value.
+ (disassemble): Updated to handle the disassembly of instructions.
+ (print_insn_v850): Updated function to print instruction for different
+ families.
+ * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
+ extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
+ extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
+ insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
+ extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
+ extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
+ extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
+ insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
+ (insert_d8_7, insert_d5_4, insert_i5div): Remove.
+ (v850_operands): Update with the relocation name. Also update
+ the instructions with specific set of processors.
+
2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
* arm-dis.c (print_insn_arm): Add cases for printing more
View
609 opcodes/v850-dis.c
@@ -1,5 +1,5 @@
/* Disassemble V850 instructions.
- Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2007
+ Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2007, 2010
Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
@@ -28,44 +28,169 @@
#include "opintl.h"
static const char *const v850_reg_names[] =
-{ "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7",
+{
+ "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",