diff --git a/rtl/user/axilite_axis/rtl/axi_ctrl_logic.sv b/rtl/user/axilite_axis/rtl/axi_ctrl_logic.sv
index 4150db9..81be852 100755
--- a/rtl/user/axilite_axis/rtl/axi_ctrl_logic.sv
+++ b/rtl/user/axilite_axis/rtl/axi_ctrl_logic.sv
@@ -287,7 +287,13 @@ module axi_ctrl_logic(
     logic [9:0]aa_index; // for index of aa_regs 
     logic [9:0]mb_index; // for index of mb_regs 
 
-    assign next_trans = (next_ss) ? TRANS_SS : TRANS_LS;
+    //assign next_trans = (next_ss) ? TRANS_SS : TRANS_LS; // iverilog issue
+    always_comb begin
+        if(next_ss == 1'b1)
+            next_trans = TRANS_SS;
+        else
+            next_trans = TRANS_LS;
+    end
 
     // compute control signals according to source (LS / SS) and address range
     // note this is combinational, so the signals can only exist when state is AXI_DECIDE_DEST,