Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
Newer
Older
100644 228 lines (151 sloc) 9.633 kb
6ade0cd bootnecklad Added front panel specifications
authored
1 # Titan - Specifications #
83d757e Toby Oops, a wild markup appears.
qu1j0t3 authored
2
3a43d2f bootnecklad added general specs
authored
3 ## System Specifications ##
4
5 Currently, Titan has the following specifications:
6
7 8 bit data bus
8 16 8 bit registers, mapped to them are the program counter and stack pointer
9 16 bit stack pointer(64k stack)
10 16 bit program counter
11 64k addressable memory
12 Capable of 10 8bit arithmetic functions
13 Various addressing modes(Immediate, Indirect, Index, Register)
14 Memory mapped I/O
15
16 Planned Memory map:
17 0000-9EFF - Fixed SRAM
18 9F00-DFFF - Switchable 16k banked SRAM
19 E000-FEFF - 8k EEPROM
20 FF00-FFFF - 256 I/O ports
21
22
23
6ade0cd bootnecklad Added front panel specifications
authored
24 ## Front Panel Specifications ##
25
26 On the front panel there are eight control switches, they have the following function:
27
28 | LOAD ADDR* | CONT* | EXAMINE* | DEPOSIT* | | STEP* | SINGLE/CONT | RUN/PRGM(HALT) | RESET* |
29
7eac6b2 bootnecklad I accidently formatting
authored
30 LOAD ADDR - Loads the address currently on the address switches into the PC[1]
31 CONT - Continues to the next address, ie increments the program counter[2]
32 EXAMINE - Displays the contents of memory
33 DEPOSIT - Writes the value on the data input switches into memory
34 STEP - Single step the clock
35 SINGLE/CONTINUOUS - Switch between single or continuous mode[3]
36 RUN/PRGM(HALT) - Switch between run and program mode(halted clock)
37 RESET - Send the reset line through the whole processor + expansion board[4]
38
39 * - denotes that the switches are spring loaded, so will return to a zero(switch down) when released.
40
41 [1] - When the 'LOAD ADDR' switch is zero then the value of the switches is used to directly access memory. The address to be examined or deposited to does not have to be clocked into the program counter.
42 [2] - This allows various functions, for example the examine switch could be set high and the CONT switch toggled, this would coninuously display values in memory in from the next address.
43 [3] - Various clock speeds below the processors maximum speed can be selected from within the case using some DIP switches.
44 [4] - The reset line is common throughout the processor, it is also sent to the expansion board to reset any devices that would be plugged into the expansion board.
6ade0cd bootnecklad Added front panel specifications
authored
45
46
47
48 ## ISA - Instruction Set Architecture ##
49
83d757e Toby Oops, a wild markup appears.
qu1j0t3 authored
50 ## Notation ##
234a017 bootnecklad Updated Specifications
authored
51
ba2f936 Added explanation for S-expression-style assembly
Marc Cleave authored
52 Titan uses S-expression-style assembly. Each assembly program is a list of instructions. Instead of the assembler operating on assembly code as a textual representation, it instead has a SYMBOLIC representation.
53
54 why does this symbolic stuff make a difference!!!
55
56 Symbolic expressions make instructions into manipulable objects, that can be created, modified, stored, and printed. Assembly programs and the component instructions are first-class, and functions can both take them as arguments and produce them as output.
57
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
58 Rs = Source register
59 Rd = Destination register
60 Rl = Low byte source register
61 Rh = High byte source register
62 SSSS = Source register in binary
63 DDDD = Destination register in binary
64 LLLL = Low byte source register in binary
65 HHHH = High byte source register in binary
66 ZZZZ = Source/Destination Address in hex
972bddb bootnecklad Added Specifications.txt to shut qu1j0t3
authored
67
a5f6e80 Toby Edits.
qu1j0t3 authored
68 ## Flags ##
69
6bbdc01 bootnecklad Update Specifications.md
authored
70 Z: Set if ALU operation stores a zero in the destination register.
a5f6e80 Toby Edits.
qu1j0t3 authored
71
6bbdc01 bootnecklad Update Specifications.md
authored
72 C: Set if ALU operation carries a 1 bit from an ADD function.[1]
6ade0cd bootnecklad Added front panel specifications
authored
73
6bbdc01 bootnecklad Update Specifications.md
authored
74 S: Set if ALU operation stores a number with the MSB set.
a5f6e80 Toby Edits.
qu1j0t3 authored
75
6ade0cd bootnecklad Added front panel specifications
authored
76 [1] - The carry flag is *always* set in any ALU operation, for operations which don't require two arguments the B input is zero.
a5f6e80 Toby Edits.
qu1j0t3 authored
77
1be81be bootnecklad Optimised memmang and cleared up spec
authored
78 ## CPU CTRL ##
79
80 Opcode Cond
81 ------- -------
ba2f936 Added explanation for S-expression-style assembly
Marc Cleave authored
82 0 0 0 0 0 0 0 0 - (NOP) - Performs a No Operation
83 0 0 0 0 0 0 0 1 - (HLT) - Stops the clock
1be81be bootnecklad Optimised memmang and cleared up spec
authored
84
2422054 bootnecklad Fixed typos
authored
85 ## Arithmetic ##
9ca01d8 bootnecklad Added the ADC (Add with carry in) instruction, reduces 32bit add by ~6by...
authored
86
11b3c83 bootnecklad Updated, made room for more instructions, replaced lists for tables
authored
87 Opcode Cond
88 ------- -------
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
89 0 0 0 1 0 0 0 0 - (ADD Rs Rd) - Adds source and destination register
90 0 0 0 1 0 0 0 1 - (ADC Rs Rd) - Add source and destination register with carry in high
91 0 0 0 1 0 0 1 0 - (SUB Rs Rd) - Subtracts source and destination register
92 0 0 0 1 0 0 1 1 - (AND Rs Rd) - Logical AND of source and destination register
93 0 0 0 1 0 1 0 0 - (IOR Rs Rd) - Logical OR of source and destination register
94 0 0 0 1 0 1 0 1 - (XOR Rs Rd) - Logical XOR of source and destination register
95 0 0 0 1 0 1 1 0 - (NOT Rs) - Invert/Complement of source register
96 0 0 0 1 0 1 1 1 - (SHR Rs) - Shifts all bits right away from carry of source register(LSB fed into carry)
97 0 0 0 1 1 0 0 0 - (INC Rs) - Increments the source register
98 0 0 0 1 1 0 0 1 - (DEC Rs) - Decrements the source register
972bddb bootnecklad Added Specifications.txt to shut qu1j0t3
authored
99
0a57ad4 bootnecklad Added ability for system calls (software interrupts!)
authored
100 ## Interrupt/Exception operations ##
11d333a bootnecklad Added ability for system calls (software interrupts!)
authored
101
102 These are generally used as system calls, the interrupt vector addresses is stored in the EEPROM on the external address bus.
0a57ad4 bootnecklad Added ability for system calls (software interrupts!)
authored
103 All registers are saved in a location in system memory when an interrupt is called. The interrupt will also return with an interrupt code, and the address the interrupt was called at.
11d333a bootnecklad Added ability for system calls (software interrupts!)
authored
104
0a57ad4 bootnecklad Added ability for system calls (software interrupts!)
authored
105 Opcode Cond
106 ------- -------
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
107 0 0 1 0 0 0 0 0 - (INT #x5A) - Calls interrupt 5A
108 0 0 1 0 0 0 0 1 - (RTE) - Return from exception/interrupt
11d333a bootnecklad Added ability for system calls (software interrupts!)
authored
109
110 Where ZZZZ ZZZZ is the interrupt to call.
972bddb bootnecklad Added Specifications.txt to shut qu1j0t3
authored
111
83d757e Toby Oops, a wild markup appears.
qu1j0t3 authored
112 ## Stack operations ##
972bddb bootnecklad Added Specifications.txt to shut qu1j0t3
authored
113
d58e8a9 bootnecklad More typos, finalising ISA...
authored
114 Opcode Operand
115 ------- -------
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
116 0 1 1 1 S S S S - (PSH Rs) - Pushes Rs onto the stack
117 1 0 0 0 D D D D - (POP Rd) - Pops the top of the stack into Rd
234a017 bootnecklad Updated Specifications
authored
118
c338780 bootnecklad Updated and documented more microcode, also updated specifications
authored
119 ## Register operations ##
120
121 Opcode Cond
122 ------- -------
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
123 0 1 1 0 S S S S - (CLR Rs) - Clears Rs
124 1 0 0 1 0 0 0 0 - (MOV Rs Rd) - Moves Rs into Rd
972bddb bootnecklad Added Specifications.txt to shut qu1j0t3
authored
125
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
126 Second byte of MOV instruction is assembled into:
972bddb bootnecklad Added Specifications.txt to shut qu1j0t3
authored
127
c338780 bootnecklad Updated and documented more microcode, also updated specifications
authored
128 SSSS DDDD
972bddb bootnecklad Added Specifications.txt to shut qu1j0t3
authored
129
130
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
131 ## Jumps ##
972bddb bootnecklad Added Specifications.txt to shut qu1j0t3
authored
132
a5f6e80 Toby Edits.
qu1j0t3 authored
133 Only JMI has indexed addressing.
972bddb bootnecklad Added Specifications.txt to shut qu1j0t3
authored
134
a5f6e80 Toby Edits.
qu1j0t3 authored
135 Opcode I Cond
83d757e Toby Oops, a wild markup appears.
qu1j0t3 authored
136 ------- --- -----
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
137 1 0 1 0 0 0 0 0 - (JMP #xZZZZ) - Direct jump to 0xZZZZ
138 1 0 1 0 0 0 0 1 - (JPZ #xZZZZ) - Jump if zero flag set
139 1 0 1 0 0 0 1 0 - (JPS #xZZZZ) - Jump if sign flag set
140 1 0 1 0 0 0 1 1 - (JPC #xZZZZ) - Jump if carry flag set
141 1 0 1 0 0 1 0 0 - (JPI #xZZZZ) - Indirect jump, point to a location in memory (0xZZZZ) and jumps to the value stored in the address (Big endian)
142 1 0 1 0 0 1 0 1 - (JSR #xZZZZ) - Push return address onto stack, direct jump to 0xZZZZ
143 1 0 1 0 0 1 1 0 - (RTN) - Returns to address thats stored on stack
144 1 0 1 0 1 0 0 0 - (JMI #xZZZZ) - Where base address is 0xZZZZ and offset is in R1
145 1 0 1 0 1 0 0 1 - (JMI #(R1 R2)) - Where address to jump to is in R1(high byte) and R2(low byte) (can only be R1 & R2)
972bddb bootnecklad Added Specifications.txt to shut qu1j0t3
authored
146
ccff015 Updated assembly conventions to "schemeified" assembly
Marc Cleave authored
147 ## Indexed Load/Store Memory ##
972bddb bootnecklad Added Specifications.txt to shut qu1j0t3
authored
148
fa7d516 bootnecklad ...
authored
149 Opcode I Dst
150 ------- -- ------
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
151 1 0 1 1 0 D D D - (LDI Rd #xZZZZ) - Indexed load byte from memory, from address ZZZZ, offset in R1
152 1 1 0 0 0 S S S - (STI Rs #xZZZZ) - Indexed store byte to memory, from address ZZZZ, offset in R1
153 1 0 1 1 1 D D D - (LDI Rd #(R1 R2)) - Indexed load byte from memory, from address in R1(high byte) and R2(low byte)
154 1 1 0 0 1 S S S - (STI Rs #(R1 R2)) - Indexed store byte to memory, from address in R1(high byte) and R2(low byte)
972bddb bootnecklad Added Specifications.txt to shut qu1j0t3
authored
155
156
157
ccff015 Updated assembly conventions to "schemeified" assembly
Marc Cleave authored
158 ## Load Constant ##
972bddb bootnecklad Added Specifications.txt to shut qu1j0t3
authored
159
1be81be bootnecklad Optimised memmang and cleared up spec
authored
160 Opcode Cond
161 ------- -------
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
162 1 1 0 1 D D D D - (LDC Rd #xZZ)
972bddb bootnecklad Added Specifications.txt to shut qu1j0t3
authored
163
164
ccff015 Updated assembly conventions to "schemeified" assembly
Marc Cleave authored
165 ## Load/Store Memory ##
972bddb bootnecklad Added Specifications.txt to shut qu1j0t3
authored
166
fa7d516 bootnecklad ...
authored
167 Opcode Dst
168 ------- ------
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
169 1 1 1 0 D D D D - (LDM Rs #xZZZZ) - Load byte from memory, from address ZZZZ to DDDD
170 1 1 1 1 S S S S - (STM Rd #xZZZZ) - Store byte to memory, to address ZZZZ, byte from SSSS.
cb6f83b bootnecklad Added some assembly conventions
authored
171
172
173
174
175
176
d58e8a9 bootnecklad More typos, finalising ISA...
authored
177 ## ASSEMBLY CONVENTIONS ##
cb6f83b bootnecklad Added some assembly conventions
authored
178
d58e8a9 bootnecklad More typos, finalising ISA...
authored
179 ### Pseudo instructions ###
dd87a88 bootnecklad added the
authored
180
181 These pseudo instructions are built into the assembler, this makes code cleaner.
182
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
183 (SHL Rs) - Simple ADD Rn,Rn - shifts all bits towards the carry bit, highest significant bit sent into carry
184 (TST Rs) - XOR Rn,Rn - Tests if a register is zero or not.
c932230 added more diretive information and pseudo instructions
bootnecklad@gmail.com authored
185 (JNZ #xZZZZ) - Jump if no zero flag set
186 (JNS #xZZZZ) - Jump if no sign flag set
187 (JNC #xZZZZ) - Jump if no carry flag set
dd87a88 bootnecklad added the
authored
188
189
ccff015 Updated assembly conventions to "schemeified" assembly
Marc Cleave authored
190 ### Assembly directives ###
191
cb6f83b bootnecklad Added some assembly conventions
authored
192 Labels are used to write programs, you dont want to be dealing with straight addresses. It hurts. A lot!
193
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
194 (.LABEL LOOP)
c932230 added more diretive information and pseudo instructions
bootnecklad@gmail.com authored
195 (LDI R0 #x0000) ; Fetch byte from set of byes in memory
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
196 (TST R0) ; Tests byte fetched
197 (JPZ END) ; If 0x00 then end of the set
198 (INC R1) ; Next address must be +1 from previous
199 (JMP LOOP) ; Time to get next byte
200 (.LABEL END)
201 (JMP END) ; infinte loop
cb6f83b bootnecklad Added some assembly conventions
authored
202
203 Above example shoves a label and a couple of instructions.
204
205
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
206 Below shows an ASCII string "BAR" that will be placed in memory at FOO, FOO is a label, beginning in memory at the first character of the string
cb6f83b bootnecklad Added some assembly conventions
authored
207
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
208 (.ASCII FOO "BAR")
209 (.ASCIZ <label> "ZERO TERMINATED STRING, ADDS 0x00 AT END OF STRING")
cb6f83b bootnecklad Added some assembly conventions
authored
210
51a6642 bootnecklad Added the .DATA assembly convention
authored
211 Below is syntax for BYTE and WORD and DATA:
cb6f83b bootnecklad Added some assembly conventions
authored
212
c932230 added more diretive information and pseudo instructions
bootnecklad@gmail.com authored
213 (.RAW #xFF)
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
214 (.BYTE <label> #xZZ)
215 (.WORD <label> #xZZZZ)
216 (.DATA <label> #xZZ #xZZ ... #xZZ)
cb6f83b bootnecklad Added some assembly conventions
authored
217
c932230 added more diretive information and pseudo instructions
bootnecklad@gmail.com authored
218 Byte defines the label as a byte, this is used to map labels to interrupt codez, ie .BYTE END 0x05 ... INT END would call the interrupt 0x05. This is used to make software interrupts or get defined bytes into registers
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
219
220 Word defines the label as the address, this is used to map labels to addresses. This time, any referance to the label in the rest of the program will return the value of the word. ie (.WORD HUE 0xFE5A) Would return 0xFE5A in (JMP HUE)
221
36c842b bootnecklad Redefined .BYTE .WORD. DATA
authored
222 Data will dump the list of data in order into memory, the label will return the address of the first item of the list of data.
223
c932230 added more diretive information and pseudo instructions
bootnecklad@gmail.com authored
224 Raw does the same as Data but there is no label mapped to the area where it its dumped into memory.
225
8eb34bd Updated assembly conventions to "schemefied" titan assembly
Marc Cleave authored
226 Below is the syntax for including another file containing assembly, this allows routines to be called from another file.
227
228 (.INCL "filename")
Something went wrong with that request. Please try again.