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move cse_simple to platform specific files

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commit b63fa427b1a4c9ee596426fafd6dc36d6a029e8f 1 parent cea832f
Brad Roberts authored
Showing with 60 additions and 59 deletions.
  1. +0 −59 src/backend/cgcod.c
  2. +59 −0 src/backend/cod3.c
  3. +1 −0  src/backend/code.h
59 src/backend/cgcod.c
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@@ -37,7 +37,6 @@ STATIC code * loadcse(elem *,unsigned,regm_t);
STATIC void blcodgen(block *);
STATIC void cgcod_eh();
STATIC code * cse_save(regm_t ms);
-STATIC bool cse_simple(code *c, elem *e);
STATIC code * comsub(elem *,regm_t *);
bool floatreg; // !=0 if floating register is required
@@ -1619,64 +1618,6 @@ code *cse_flush(int do87)
return c;
}
-/*************************************************
- */
-
-STATIC bool cse_simple(code *c, elem *e)
-{ regm_t regm;
- unsigned reg;
- int sz = tysize[tybasic(e->Ety)];
-
- if (!I16 && // don't bother with 16 bit code
- e->Eoper == OPadd &&
- sz == REGSIZE &&
- e->E2->Eoper == OPconst &&
- e->E1->Eoper == OPvar &&
- isregvar(e->E1,&regm,&reg) &&
- !(e->E1->EV.sp.Vsym->Sflags & SFLspill)
- )
- {
- memset(c,0,sizeof(*c));
-
- // Make this an LEA instruction
- c->Iop = 0x8D; // LEA
- buildEA(c,reg,-1,1,e->E2->EV.Vuns);
- if (I64)
- { if (sz == 8)
- c->Irex |= REX_W;
- else if (sz == 1 && reg >= 4)
- c->Irex |= REX;
- }
-
- return true;
- }
- else if (e->Eoper == OPind &&
- sz <= REGSIZE &&
- e->E1->Eoper == OPvar &&
- isregvar(e->E1,&regm,&reg) &&
- (I32 || I64 || regm & IDXREGS) &&
- !(e->E1->EV.sp.Vsym->Sflags & SFLspill)
- )
- {
- memset(c,0,sizeof(*c));
-
- // Make this a MOV instruction
- c->Iop = (sz == 1) ? 0x8A : 0x8B; // MOV reg,EA
- buildEA(c,reg,-1,1,0);
- if (sz == 2 && I32)
- c->Iflags |= CFopsize;
- else if (I64)
- { if (sz == 8)
- c->Irex |= REX_W;
- else if (sz == 1 && reg >= 4)
- c->Irex |= REX;
- }
-
- return true;
- }
- return false;
-}
-
/*************************
* Common subexpressions exist in registers. Note this in regcon.cse.mval.
* Input:
59 src/backend/cod3.c
View
@@ -1630,6 +1630,65 @@ regm_t cod3_useBP()
return 0;
}
+/*************************************************
+ * Generate code segment to be used later to restore a cse
+ */
+
+bool cse_simple(code *c, elem *e)
+{ regm_t regm;
+ unsigned reg;
+ int sz = tysize[tybasic(e->Ety)];
+
+ if (!I16 && // don't bother with 16 bit code
+ e->Eoper == OPadd &&
+ sz == REGSIZE &&
+ e->E2->Eoper == OPconst &&
+ e->E1->Eoper == OPvar &&
+ isregvar(e->E1,&regm,&reg) &&
+ !(e->E1->EV.sp.Vsym->Sflags & SFLspill)
+ )
+ {
+ memset(c,0,sizeof(*c));
+
+ // Make this an LEA instruction
+ c->Iop = 0x8D; // LEA
+ buildEA(c,reg,-1,1,e->E2->EV.Vuns);
+ if (I64)
+ { if (sz == 8)
+ c->Irex |= REX_W;
+ else if (sz == 1 && reg >= 4)
+ c->Irex |= REX;
+ }
+
+ return true;
+ }
+ else if (e->Eoper == OPind &&
+ sz <= REGSIZE &&
+ e->E1->Eoper == OPvar &&
+ isregvar(e->E1,&regm,&reg) &&
+ (I32 || I64 || regm & IDXREGS) &&
+ !(e->E1->EV.sp.Vsym->Sflags & SFLspill)
+ )
+ {
+ memset(c,0,sizeof(*c));
+
+ // Make this a MOV instruction
+ c->Iop = (sz == 1) ? 0x8A : 0x8B; // MOV reg,EA
+ buildEA(c,reg,-1,1,0);
+ if (sz == 2 && I32)
+ c->Iflags |= CFopsize;
+ else if (I64)
+ { if (sz == 8)
+ c->Irex |= REX_W;
+ else if (sz == 1 && reg >= 4)
+ c->Irex |= REX;
+ }
+
+ return true;
+ }
+ return false;
+}
+
/***************************************
* Gen code for OPframeptr
*/
1  src/backend/code.h
View
@@ -691,6 +691,7 @@ void useregs (regm_t regm );
code *getregs (regm_t r );
code *getregs_imm (regm_t r );
code *cse_flush(int);
+bool cse_simple(code *c, elem *e);
void cssave (elem *e , regm_t regm , unsigned opsflag );
bool evalinregister (elem *e );
regm_t getscratch();
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