974 Project files/Processor.bdf
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Large diffs are not rendered by default.

9 Project files/controlUnit.vhd
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@@ -114,6 +114,15 @@ BEGIN
b_select <= '1';
--the next line sets immediate to 1
--check immediate.vhd for more detail
extend <= "10";
END IF;
IF(opCode(2 downto 0) = "000") THEN
--DEC
alu_op <= "11";
b_select <= '1';
b_inv <= '1';
--the next line sets immediate to 1
--check immediate.vhd for more detail
extend <= "10";
END IF;
END IF;
49 Project files/lpm_constant4.bsf
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@@ -0,0 +1,49 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 0 0 112 48)
(text "lpm_constant4" (rect 15 0 115 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 32 25 44)(font "Arial" ))
(port
(pt 112 24)
(output)
(text "result[15..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "4" (rect 87 17 91 30)(font "Arial" (font_size 8)))
(line (pt 112 24)(pt 96 24)(line_width 3))
)
(drawing
(text "16" (rect 94 26 196 63)(font "Arial" ))
(line (pt 106 20)(pt 98 28))
(line (pt 16 16)(pt 16 32))
(line (pt 16 16)(pt 96 16))
(line (pt 16 32)(pt 96 32))
(line (pt 96 16)(pt 96 32))
(line (pt 0 0)(pt 114 0))
(line (pt 114 0)(pt 114 50))
(line (pt 0 50)(pt 114 50))
(line (pt 0 0)(pt 0 50))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
)
)
109 Project files/lpm_constant4.vhd
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@@ -0,0 +1,109 @@
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT

-- ============================================================
-- File Name: lpm_constant4.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 173 11/01/2011 SJ Web Edition
-- ************************************************************


--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.


LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY lpm;
USE lpm.all;

ENTITY lpm_constant4 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END lpm_constant4;


ARCHITECTURE SYN OF lpm_constant4 IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);



COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;

BEGIN
result <= sub_wire0(15 DOWNTO 0);

LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 4,
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "LPM_CONSTANT",
lpm_width => 16
)
PORT MAP (
result => sub_wire0
);



END SYN;

-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "4"
-- Retrieval info: PRIVATE: nBit NUMERIC "16"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm