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syntax cleaning

Fixup of all the minor syntax errors. Now on to compilation...
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1 parent 8e75c74 commit 3f4686c62dfc7db7ad19f995da0b80f39d52181d @bunnie committed Feb 24, 2012
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3 kovan1.ppr
@@ -2,12 +2,13 @@
<Project Version="4" Minor="27">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
+ <RunSet Dir="runs" File="runs.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
<Config>
<Option Name="Part" Val="xc6slx45csg324-2"/>
<Option Name="TargetLanguage" Val="Verilog"/>
- <Option Name="SourceMgmtMode" Val="All"/>
+ <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
</Config>
</Project>
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2 kovan1.srcs/sources_1/imports/kovan1/common/i2c_slave.v
@@ -285,7 +285,7 @@ module i2c_slave (
parameter EXT_RAM_WIDTH = 8;
parameter EXT_RAM_ADDR_BITS = 6; // note parameter width exception in reg_a* assign block below
- reg [EXT_RAM_WIDTH-1:0] I2C_regblock_ext [(2**RAM_ADDR_BITS)-1:0];
+ reg [EXT_RAM_WIDTH-1:0] I2C_regblock_ext [(2**EXT_RAM_ADDR_BITS)-1:0];
reg [EXT_RAM_WIDTH-1:0] I2C_regread_async_ext;
wire [EXT_RAM_ADDR_BITS-1:0] I2C_ramaddr_ext;
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24 kovan1.srcs/sources_1/imports/kovan1/kovan.v
@@ -166,7 +166,6 @@ module kovan (
wire clk26;
wire clk26ibuf;
wire clk26buf;
- wire clk26ibuf;
assign clk26 = FPGA_SCLK;
@@ -188,13 +187,15 @@ module kovan (
.RESET(glbl_reset),
.LOCKED(qvga_clkgen_locked) );
- reg lcd_pipe_b[5:0];
- reg lcd_pipe_r[5:0];
- reg lcd_pipe_g[5:0];
+ reg [5:0] lcd_pipe_b;
+ reg [5:0] lcd_pipe_r;
+ reg [5:0] lcd_pipe_g;
reg lcd_pipe_den;
reg lcd_hsync;
reg lcd_vsync;
reg lcd_reset_n;
+ reg lcd_pipe_hsync;
+ reg lcd_pipe_vsync;
wire lcd_reset;
sync_reset qvga_reset(
@@ -454,7 +455,7 @@ module kovan (
end
// local reset timer for ddr2
- sync_reset ddr2_reset(
+ sync_reset ddr2_reset_sync(
.clk(c3_clk0),
.glbl_reset(!c3_clk_locked),
.reset(ddr2_reset) );
@@ -573,6 +574,7 @@ module kovan (
DDR2_RD_nstate = DDR2_RD_DATA;
end else begin
DDR2_RD_nstate = DDR2_RD_WAIT;
+ end
end
DDR2_RD_DATA: begin
if( ddr2_rd_avail_n == 1'b0 ) begin
@@ -647,14 +649,16 @@ module kovan (
BUFG clk1M_buf(.I(clk1M_unbuf), .O(clk1M));
wire dna_reset;
- sync_reset dna_reset(
+ sync_reset dna_reset_sync(
.clk(clk_2M),
.glbl_reset(glbl_reset),
.reset(dna_reset) );
reg dna_pulse;
reg dna_shift;
wire dna_bit;
+ reg [55:0] dna_data;
+
DNA_PORT device_dna( .CLK(clk2M), .DIN(1'b0), .DOUT(dna_bit), .READ(dna_pulse), .SHIFT(dna_shift) );
parameter DNA_INIT = 4'b1 << 0;
@@ -1194,14 +1198,14 @@ module kovan (
.reg_64(ddr2_test_addr[7:0]),
.reg_65(ddr2_test_addr[15:8]),
.reg_66(ddr2_test_addr[23:16]),
- .reg_67(ddr2_test_addr[31:24]),
+ .reg_67(ddr2_test_addr[29:24]),
.reg_68(ddr2_regcmd[7:0]),
// read-only interfaces
- .reg_80({dig_val_good, dig_busy}),
+ .reg_80({6'b0,dig_val_good, dig_busy}),
.reg_81(adc_in[7:0]),
- .reg_82(6'b000000,adc_in[9:8]),
- .reg_83({adc_valid}),
+ .reg_82({6'b000000,adc_in[9:8]}),
+ .reg_83({7'b0,adc_valid}),
.reg_90(ddr2_read_data[7:0]),
.reg_91(ddr2_read_data[15:8]),
View
7 kovan1.srcs/sources_1/imports/kovan1/robot_iface.v
@@ -45,7 +45,7 @@ module robot_iface(
// ADC interface
output reg [9:0] adc_in,
input wire [3:0] adc_chan, // channels 0-7 are for user, 8-15 are for motor current fbk
- output wire adc_valid,
+ output reg adc_valid,
input wire adc_go,
// motor driver interface
@@ -194,7 +194,7 @@ module robot_iface(
shift_out <= {ana_pu[7:0],dig_pu[7:0],dig_oe_n[7:0],dig_out_val[7:0]};
shift_in <= shift_in;
- dig_srload <= chain_detect; // if chain detect is high, we never update the digital SRs
+ dig_srload <= 1'b0; // just need to create a rising edge on the next transition
update_dig <= 1'b1;
dig_in_val <= dig_in_val;
@@ -346,7 +346,6 @@ module robot_iface(
reg adc_go_d;
reg adc_go_edge;
reg [4:0] adc_shift_count;
- reg adc_valid;
reg [15:0] adc_shift_out;
reg [15:0] adc_shift_in;
reg [1:0] adc_cs;
@@ -406,7 +405,7 @@ module robot_iface(
end
ADC_START: begin
adc_shift_count <= 5'b0;
- adc_shift_out <= {11'b0,adc_chan[0:2],2'b0};
+ adc_shift_out <= {11'b0,adc_chan[0],adc_chan[1],adc_chan[2],2'b0};
adc_shift_in <= adc_shift_in;
adc_cs <= adc_chan[3] ? 2'b01 : 2'b10;
View
2 kovan1.srcs/sources_1/ip/clk_wiz_v3_2_0/clk_ddr2_26m_312m.xco
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 13.3
-# Date: Fri Feb 17 09:50:12 2012
+# Date: Thu Feb 23 19:08:39 2012
#
##############################################################
#
View
2 kovan1.srcs/sources_1/ip/clk_wiz_v3_2_1/clk_wiz_v3_2_qvga.xco
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 13.3
-# Date: Fri Feb 17 20:56:17 2012
+# Date: Thu Feb 23 19:09:25 2012
#
##############################################################
#
View
2 kovan1.srcs/sources_1/ip/mig_v3_9_0/ddr2_m3_core_v2.xco
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 13.3
-# Date: Fri Feb 17 09:50:58 2012
+# Date: Thu Feb 23 19:08:00 2012
#
##############################################################
#

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