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syntax clean and bug fixes to get to clean-compile

code now cleanly compiles and ports look properly hooked up.
on to testing!
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1 parent 3f4686c commit 4c7792ca2e4d01908e60c27936410280502e633a @bunnie committed Feb 24, 2012
@@ -13,7 +13,7 @@ CONFIG VCCAUX = 3.3;
##################
## clocks
-NET "FPGA_SCLK" TNM_NET = "TNM_clk26";
+NET "OSC_CLK" TNM_NET = "TNM_clk26";
TIMESPEC "TS_clk26" = PERIOD "TNM_clk26" 26 MHz HIGH 50;
@@ -62,16 +62,16 @@ NET "CEC" LOC = N5;
NET "CEC" IOSTANDARD = LVCMOS33;
# HDMI DDC pins
NET "DDC_SCL_LV_N" LOC = T4;
-NET "DDC_SCL_LV_N" IOSTANDARD = TMDS_33;
+NET "DDC_SCL_LV_N" IOSTANDARD = LVCMOS33;
NET "DDC_SDA_LV_N" LOC = R5;
-NET "DDC_SDA_LV_N" IOSTANDARD = TMDS_33;
+NET "DDC_SDA_LV_N" IOSTANDARD = LVCMOS33;
NET "DDC_SDA_PD" LOC = V4;
NET "DDC_SDA_PD" IOSTANDARD = LVCMOS33;
NET "DDC_SDA_PU" LOC = T3;
NET "DDC_SDA_PU" IOSTANDARD = LVCMOS33;
# HDMI hot plug detect ins
-NET "HDMI_HPD_LL_N" LOC = P6;
-NET "HDMI_HPD_LL_N" IOSTANDARD = LVCMOS33;
+NET "HPD_N" LOC = P6;
+NET "HPD_N" IOSTANDARD = LVCMOS33;
NET "HPD_OVERRIDE" LOC = R3;
NET "HPD_OVERRIDE" IOSTANDARD = LVCMOS33;
# HDMI genlock feedback
@@ -125,8 +125,8 @@ NET "DIG_ADC_OUT" LOC = R11;
NET "DIG_ADC_OUT" IOSTANDARD = LVCMOS33;
NET "DIG_ADC_SCLK" LOC = T11;
NET "DIG_ADC_SCLK" IOSTANDARD = LVCMOS33;
-NET "DIG_CLR" LOC = P16;
-NET "DIG_CLR" IOSTANDARD = LVCMOS33;
+NET "DIG_CLR_N" LOC = P16;
+NET "DIG_CLR_N" IOSTANDARD = LVCMOS33;
NET "DIG_IN" LOC = R10;
NET "DIG_IN" IOSTANDARD = LVCMOS33;
NET "DIG_OUT" LOC = L16;
@@ -247,7 +247,7 @@ NET "LCDO_R[6]" IOSTANDARD = LVCMOS33;
NET "LCDO_R[7]" LOC = P18;
NET "LCDO_R[7]" IOSTANDARD = LVCMOS33;
NET "LCDO_RESET_N" LOC = D18;
-NET "LCDO_RESET_N" IOSTANDARD = TMDS_33;
+NET "LCDO_RESET_N" IOSTANDARD = LVCMOS33;
NET "LCDO_VSYNC" LOC = T18;
NET "LCDO_VSYNC" IOSTANDARD = LVCMOS33;
NET "LCD_B[0]" LOC = A11;
@@ -357,7 +357,7 @@ NET "FPGA_LED" IOSTANDARD = LVCMOS33;
############################################################################
## Clock constraints
############################################################################
-NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
+NET "ddr2core/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 3.2 ns HIGH 50 %;
############################################################################
@@ -40,10 +40,8 @@
module i2c_slave (
// external host interface
input wire SCL, // the SCL pin state
- output wire SCL_pd, // signals to IOB to pull the SCL bus low
input wire SDA,
output reg SDA_pd,
- output wire SDA_pu, // for overriding SDA...in the future.
input wire clk, // internal FPGA clock
input wire glbl_reset, // internal FPGA reset
@@ -135,7 +133,7 @@ module i2c_slave (
output wire [7:0] reg_41,
output wire [7:0] reg_42,
output wire [7:0] reg_43,
- output wire [7:0] reg_44,
+// output wire [7:0] reg_44,
output wire [7:0] reg_45,
output wire [7:0] reg_46,
output wire [7:0] reg_47,
@@ -174,6 +172,7 @@ module i2c_slave (
input wire [7:0] reg_81,
input wire [7:0] reg_82,
input wire [7:0] reg_83,
+ input wire [7:0] reg_84,
input wire [7:0] reg_90,
input wire [7:0] reg_91,
@@ -214,10 +213,6 @@ module i2c_slave (
// At 100kHz operation, 10us is a cycle, so 0.5us ~ 12 cycles
parameter TRF_CYCLES = 5'd4; // number of cycles for rise/fall time
- // just some tie-offs for future functionality not yet implemented...
- assign SDA_pu = 1'b0;
- assign SCL_pd = 1'b0;
-
////////////////
///// protocol-level state machine
////////////////
@@ -641,7 +636,7 @@ module i2c_slave (
assign reg_41 = I2C_regblock_ext[6'h1];
assign reg_42 = I2C_regblock_ext[6'h2];
assign reg_43 = I2C_regblock_ext[6'h3];
- assign reg_44 = I2C_regblock_ext[6'h4];
+// assign reg_44 = I2C_regblock_ext[6'h4];
assign reg_45 = I2C_regblock_ext[6'h5];
assign reg_46 = I2C_regblock_ext[6'h6];
assign reg_47 = I2C_regblock_ext[6'h7];
@@ -814,6 +809,9 @@ module i2c_slave (
8'h83: begin
I2C_regread_async = reg_83;
end
+ 8'h84: begin
+ I2C_regread_async = reg_84;
+ end
8'h90: begin
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