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added missing mig.prj file

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1 parent ff002fd commit a0a40415bde13df898aa58fd6b315cfbb3c3649f @bunnie committed Jun 27, 2012
Showing with 62 additions and 0 deletions.
  1. +62 −0 kovan1.srcs/sources_1/ip/mig_v3_9_0/ddr2_m3_core_v2/user_design/mig.prj
@@ -0,0 +1,62 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<Project NoOfControllers="1" >
+ <ModuleName>ddr2_m3_core_v2</ModuleName>
+ <TargetFPGA>xc6slx45-csg324/-2</TargetFPGA>
+ <Version>3.9</Version>
+ <Controller number="3" >
+ <MemoryDevice>DDR2_SDRAM/Components/MT47H64M16XX-25</MemoryDevice>
+ <TimePeriod>3200</TimePeriod>
+ <EnableVoltageRange>0</EnableVoltageRange>
+ <DataMask>1</DataMask>
+ <CustomPart>FALSE</CustomPart>
+ <NewPartName/>
+ <RowAddress>13</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <TimingParameters>
+ <Parameters twtr="7.5" trefi="7.8" twr="15" trtp="7.5" trfc="127.5" trp="15" tras="40" trcd="15" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >4(010)</mrBurstLength>
+ <mrCasLatency name="CAS Latency" >5</mrCasLatency>
+ <emrDllEnable name="DLL Enable" >Enable-Normal</emrDllEnable>
+ <emrOutputDriveStrength name="Output Drive Strength" >Reducedstrength</emrOutputDriveStrength>
+ <emrRTT name="RTT (nominal) - ODT" >50ohms</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="OCD Operation" >OCD Exit</emrOCD>
+ <emrDQS name="DQS# Enable" >Enable</emrDQS>
+ <emrRDQS name="RDQS Enable" >Disable</emrRDQS>
+ <emrOutputs name="Outputs" >Enable</emrOutputs>
+ <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Disable</mr2SelfRefreshTempRange>
+ <PortInterface>NATIVE,NATIVE,NATIVE,NATIVE,NATIVE,NATIVE</PortInterface>
+ <Class>Class II</Class>
+ <DataClass>Class II</DataClass>
+ <InputPinTermination>CALIB_TERM</InputPinTermination>
+ <DataTermination>25 Ohms</DataTermination>
+ <CalibrationRowAddress/>
+ <CalibrationColumnAddress/>
+ <CalibrationBankAddress/>
+ <SystemClock>Single-Ended</SystemClock>
+ <BypassCalibration>1</BypassCalibration>
+ <DebugSignals>Disable</DebugSignals>
+ <SystemClock>Single-Ended</SystemClock>
+ <Configuration>Two 32-bit bi-directional and four 32-bit unidirectional ports</Configuration>
+ <RzqPin>N4</RzqPin>
+ <ZioPin>P4</ZioPin>
+ <PortsSelected>Port2,Port3</PortsSelected>
+ <PortDirections>none,none,Read,Write,none,none</PortDirections>
+ <UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
+ <ArbitrationAlgorithm>Round Robin</ArbitrationAlgorithm>
+ <TimeSlot0>23</TimeSlot0>
+ <TimeSlot1>32</TimeSlot1>
+ <TimeSlot2>23</TimeSlot2>
+ <TimeSlot3>32</TimeSlot3>
+ <TimeSlot4>23</TimeSlot4>
+ <TimeSlot5>32</TimeSlot5>
+ <TimeSlot6>23</TimeSlot6>
+ <TimeSlot7>32</TimeSlot7>
+ <TimeSlot8>23</TimeSlot8>
+ <TimeSlot9>32</TimeSlot9>
+ <TimeSlot10>23</TimeSlot10>
+ <TimeSlot11>32</TimeSlot11>
+ </Controller>
+</Project>

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