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Adding an auto-generated file, ddr2_m3_core_v2, to fix xilinx bugs

Coregen creates the .ncf file for the DDR2 core with some odd
heirarchy for the constraints. A direct edit of the .ncf file was
employed to fix these bugs.
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commit c16375b6f3bfa8a88fd4818bba2622d9b9bedb62 1 parent 4c7792c
bunnie authored

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  1. +168 0 kovan1.srcs/sources_1/ip/mig_v3_9_0/ddr2_m3_core_v2.ncf
168 kovan1.srcs/sources_1/ip/mig_v3_9_0/ddr2_m3_core_v2.ncf
... ... @@ -0,0 +1,168 @@
  1 +
  2 +#---------------------------------------------------------
  3 +# Concatenated contents of IP UCF file C:\largework\fpga\kovan\kovan1\kovan1.srcs\sources_1\ip\mig_v3_9_0\ddr2_m3_core_v2/user_design/par/ddr2_m3_core_v2.ucf
  4 +#---------------------------------------------------------
  5 +
  6 +############################################################################
  7 +##
  8 +## Xilinx, Inc. 2006 www.xilinx.com
  9 +## Fri Feb 24 22:58:30 2012
  10 +## Generated by MIG Version 3.9
  11 +##
  12 +############################################################################
  13 +## File name : ddr2_m3_core_v2.ucf
  14 +##
  15 +## Details : Constraints file
  16 +## FPGA family: spartan6
  17 +## FPGA: xc6slx45-csg324
  18 +## Speedgrade: -2
  19 +## Design Entry: VERILOG
  20 +## Design: without Test bench
  21 +## DCM Used: Enable
  22 +## No.Of Memory Controllers: 1
  23 +##
  24 +############################################################################
  25 +############################################################################
  26 +# VCC AUX VOLTAGE
  27 +############################################################################
  28 +CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3
  29 +
  30 +############################################################################
  31 +# DDR2 requires the MCB to operate in Extended performance mode with higher Vccint
  32 +# specification to achieve maximum frequency. Therefore, the following CONFIG constraint
  33 +# follows the corresponding GUI option setting. However, DDR3 can operate at higher
  34 +# frequencies with any Vcciint value by operating MCB in extended mode. Please do not
  35 +# remove/edit the below constraint to avoid false errors.
  36 +############################################################################
  37 +CONFIG MCB_PERFORMANCE= STANDARD;
  38 +
  39 +
  40 +##################################################################################
  41 +# Timing Ignore constraints for paths crossing the clock domain
  42 +##################################################################################
  43 +NET "memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
  44 +NET "c3_pll_lock" TIG;
  45 +INST "memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
  46 +
  47 +#Please uncomment the below TIG if used in a design which enables self-refresh mode
  48 +#NET "ddr2core/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
  49 +
  50 +NET "memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ##This path exists for DDR2 only
  51 +
  52 +
  53 +############################################################################
  54 +## Memory Controller 3
  55 +## Memory Device: DDR2_SDRAM->MT47H64M16XX-25
  56 +## Frequency: 312.5 MHz
  57 +## Time Period: 3200 ps
  58 +## Supported Part Numbers: MT47H64M16HR-25
  59 +############################################################################
  60 +
  61 +############################################################################
  62 +## Clock constraints
  63 +############################################################################
  64 +NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
  65 +TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 3.2 ns HIGH 50 ;
  66 +############################################################################
  67 +
  68 +############################################################################
  69 +## I/O TERMINATION
  70 +############################################################################
  71 +NET "mcb3_dram_dq[*]" IN_TERM = NONE;
  72 +NET "mcb3_dram_dqs" IN_TERM = NONE;
  73 +NET "mcb3_dram_dqs_n" IN_TERM = NONE;
  74 +NET "mcb3_dram_udqs" IN_TERM = NONE;
  75 +NET "mcb3_dram_udqs_n" IN_TERM = NONE;
  76 +
  77 +############################################################################
  78 +# I/O STANDARDS
  79 +############################################################################
  80 +
  81 +NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL18_II ;
  82 +NET "mcb3_dram_a[*]" IOSTANDARD = SSTL18_II ;
  83 +NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL18_II ;
  84 +NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL18_II ;
  85 +NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL18_II ;
  86 +NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL18_II ;
  87 +NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL18_II ;
  88 +NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL18_II ;
  89 +NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL18_II ;
  90 +NET "mcb3_dram_cke" IOSTANDARD = SSTL18_II ;
  91 +NET "mcb3_dram_ras_n" IOSTANDARD = SSTL18_II ;
  92 +NET "mcb3_dram_cas_n" IOSTANDARD = SSTL18_II ;
  93 +NET "mcb3_dram_we_n" IOSTANDARD = SSTL18_II ;
  94 +NET "mcb3_dram_odt" IOSTANDARD = SSTL18_II ;
  95 +NET "mcb3_dram_dm" IOSTANDARD = SSTL18_II ;
  96 +NET "mcb3_dram_udm" IOSTANDARD = SSTL18_II ;
  97 +NET "mcb3_rzq" IOSTANDARD = SSTL18_II ;
  98 +NET "mcb3_zio" IOSTANDARD = SSTL18_II ;
  99 +NET "c3_sys_clk" IOSTANDARD = LVCMOS25 ;
  100 +NET "c3_sys_rst_i" IOSTANDARD = LVCMOS18 ;
  101 +############################################################################
  102 +# MCB 3
  103 +# Pin Location Constraints for Clock, Masks, Address, and Controls
  104 +############################################################################
  105 +
  106 +NET "mcb3_dram_a[0]" LOC = "J7" ;
  107 +NET "mcb3_dram_a[10]" LOC = "F4" ;
  108 +NET "mcb3_dram_a[11]" LOC = "D3" ;
  109 +NET "mcb3_dram_a[12]" LOC = "G6" ;
  110 +NET "mcb3_dram_a[1]" LOC = "J6" ;
  111 +NET "mcb3_dram_a[2]" LOC = "H5" ;
  112 +NET "mcb3_dram_a[3]" LOC = "L7" ;
  113 +NET "mcb3_dram_a[4]" LOC = "F3" ;
  114 +NET "mcb3_dram_a[5]" LOC = "H4" ;
  115 +NET "mcb3_dram_a[6]" LOC = "H3" ;
  116 +NET "mcb3_dram_a[7]" LOC = "H6" ;
  117 +NET "mcb3_dram_a[8]" LOC = "D2" ;
  118 +NET "mcb3_dram_a[9]" LOC = "D1" ;
  119 +NET "mcb3_dram_ba[0]" LOC = "F2" ;
  120 +NET "mcb3_dram_ba[1]" LOC = "F1" ;
  121 +NET "mcb3_dram_ba[2]" LOC = "E1" ;
  122 +NET "mcb3_dram_cas_n" LOC = "K5" ;
  123 +NET "mcb3_dram_ck" LOC = "G3" ;
  124 +NET "mcb3_dram_ck_n" LOC = "G1" ;
  125 +NET "mcb3_dram_cke" LOC = "H7" ;
  126 +NET "mcb3_dram_dm" LOC = "K3" ;
  127 +NET "mcb3_dram_dq[0]" LOC = "L2" ;
  128 +NET "mcb3_dram_dq[10]" LOC = "N2" ;
  129 +NET "mcb3_dram_dq[11]" LOC = "N1" ;
  130 +NET "mcb3_dram_dq[12]" LOC = "T2" ;
  131 +NET "mcb3_dram_dq[13]" LOC = "T1" ;
  132 +NET "mcb3_dram_dq[14]" LOC = "U2" ;
  133 +NET "mcb3_dram_dq[15]" LOC = "U1" ;
  134 +NET "mcb3_dram_dq[1]" LOC = "L1" ;
  135 +NET "mcb3_dram_dq[2]" LOC = "K2" ;
  136 +NET "mcb3_dram_dq[3]" LOC = "K1" ;
  137 +NET "mcb3_dram_dq[4]" LOC = "H2" ;
  138 +NET "mcb3_dram_dq[5]" LOC = "H1" ;
  139 +NET "mcb3_dram_dq[6]" LOC = "J3" ;
  140 +NET "mcb3_dram_dq[7]" LOC = "J1" ;
  141 +NET "mcb3_dram_dq[8]" LOC = "M3" ;
  142 +NET "mcb3_dram_dq[9]" LOC = "M1" ;
  143 +NET "mcb3_dram_dqs" LOC = "L4" ;
  144 +NET "mcb3_dram_dqs_n" LOC = "L3" ;
  145 +NET "mcb3_dram_odt" LOC = "K6" ;
  146 +NET "mcb3_dram_ras_n" LOC = "L5" ;
  147 +#NET "c3_sys_clk" LOC = "R10" ;
  148 +#NET "c3_sys_rst_i" LOC = "M8" ;
  149 +NET "mcb3_dram_udm" LOC = "K4" ;
  150 +NET "mcb3_dram_udqs" LOC = "P2" ;
  151 +NET "mcb3_dram_udqs_n" LOC = "P1" ;
  152 +NET "mcb3_dram_we_n" LOC = "E3" ;
  153 +
  154 +##################################################################################
  155 +#RZQ is required for all MCB designs. Do not move the location #
  156 +#of this pin for ES devices.For production devices, RZQ can be moved to any #
  157 +#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
  158 +#a 2R resistor should be connected between RZQand ground, where R is the desired#
  159 +#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
  160 +##################################################################################
  161 +NET "mcb3_rzq" LOC = "N4" ;
  162 +##################################################################################
  163 +#ZIO is only required for MCB designs using Calibrated Input Termination.#
  164 +#ZIO can be moved to any valid package pin (i.e. bonded IO) within the#
  165 +#MCB bank but must be left as a no-connect (NC) pin.#
  166 +##################################################################################
  167 +NET "mcb3_zio" LOC = "P4" ;
  168 +

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