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Adding an auto-generated file, ddr2_m3_core_v2, to fix xilinx bugs

Coregen creates the .ncf file for the DDR2 core with some odd
heirarchy for the constraints. A direct edit of the .ncf file was
employed to fix these bugs.
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1 parent 4c7792c commit c16375b6f3bfa8a88fd4818bba2622d9b9bedb62 @bunnie committed Feb 24, 2012
Showing with 168 additions and 0 deletions.
  1. +168 −0 kovan1.srcs/sources_1/ip/mig_v3_9_0/ddr2_m3_core_v2.ncf
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+
+#---------------------------------------------------------
+# Concatenated contents of IP UCF file C:\largework\fpga\kovan\kovan1\kovan1.srcs\sources_1\ip\mig_v3_9_0\ddr2_m3_core_v2/user_design/par/ddr2_m3_core_v2.ucf
+#---------------------------------------------------------
+
+############################################################################
+##
+## Xilinx, Inc. 2006 www.xilinx.com
+## Fri Feb 24 22:58:30 2012
+## Generated by MIG Version 3.9
+##
+############################################################################
+## File name : ddr2_m3_core_v2.ucf
+##
+## Details : Constraints file
+## FPGA family: spartan6
+## FPGA: xc6slx45-csg324
+## Speedgrade: -2
+## Design Entry: VERILOG
+## Design: without Test bench
+## DCM Used: Enable
+## No.Of Memory Controllers: 1
+##
+############################################################################
+############################################################################
+# VCC AUX VOLTAGE
+############################################################################
+CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3
+
+############################################################################
+# DDR2 requires the MCB to operate in Extended performance mode with higher Vccint
+# specification to achieve maximum frequency. Therefore, the following CONFIG constraint
+# follows the corresponding GUI option setting. However, DDR3 can operate at higher
+# frequencies with any Vcciint value by operating MCB in extended mode. Please do not
+# remove/edit the below constraint to avoid false errors.
+############################################################################
+CONFIG MCB_PERFORMANCE= STANDARD;
+
+
+##################################################################################
+# Timing Ignore constraints for paths crossing the clock domain
+##################################################################################
+NET "memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
+NET "c3_pll_lock" TIG;
+INST "memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
+
+#Please uncomment the below TIG if used in a design which enables self-refresh mode
+#NET "ddr2core/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
+
+NET "memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ##This path exists for DDR2 only
+
+
+############################################################################
+## Memory Controller 3
+## Memory Device: DDR2_SDRAM->MT47H64M16XX-25
+## Frequency: 312.5 MHz
+## Time Period: 3200 ps
+## Supported Part Numbers: MT47H64M16HR-25
+############################################################################
+
+############################################################################
+## Clock constraints
+############################################################################
+NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
+TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 3.2 ns HIGH 50 ;
+############################################################################
+
+############################################################################
+## I/O TERMINATION
+############################################################################
+NET "mcb3_dram_dq[*]" IN_TERM = NONE;
+NET "mcb3_dram_dqs" IN_TERM = NONE;
+NET "mcb3_dram_dqs_n" IN_TERM = NONE;
+NET "mcb3_dram_udqs" IN_TERM = NONE;
+NET "mcb3_dram_udqs_n" IN_TERM = NONE;
+
+############################################################################
+# I/O STANDARDS
+############################################################################
+
+NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL18_II ;
+NET "mcb3_dram_a[*]" IOSTANDARD = SSTL18_II ;
+NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL18_II ;
+NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL18_II ;
+NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL18_II ;
+NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL18_II ;
+NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL18_II ;
+NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL18_II ;
+NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL18_II ;
+NET "mcb3_dram_cke" IOSTANDARD = SSTL18_II ;
+NET "mcb3_dram_ras_n" IOSTANDARD = SSTL18_II ;
+NET "mcb3_dram_cas_n" IOSTANDARD = SSTL18_II ;
+NET "mcb3_dram_we_n" IOSTANDARD = SSTL18_II ;
+NET "mcb3_dram_odt" IOSTANDARD = SSTL18_II ;
+NET "mcb3_dram_dm" IOSTANDARD = SSTL18_II ;
+NET "mcb3_dram_udm" IOSTANDARD = SSTL18_II ;
+NET "mcb3_rzq" IOSTANDARD = SSTL18_II ;
+NET "mcb3_zio" IOSTANDARD = SSTL18_II ;
+NET "c3_sys_clk" IOSTANDARD = LVCMOS25 ;
+NET "c3_sys_rst_i" IOSTANDARD = LVCMOS18 ;
+############################################################################
+# MCB 3
+# Pin Location Constraints for Clock, Masks, Address, and Controls
+############################################################################
+
+NET "mcb3_dram_a[0]" LOC = "J7" ;
+NET "mcb3_dram_a[10]" LOC = "F4" ;
+NET "mcb3_dram_a[11]" LOC = "D3" ;
+NET "mcb3_dram_a[12]" LOC = "G6" ;
+NET "mcb3_dram_a[1]" LOC = "J6" ;
+NET "mcb3_dram_a[2]" LOC = "H5" ;
+NET "mcb3_dram_a[3]" LOC = "L7" ;
+NET "mcb3_dram_a[4]" LOC = "F3" ;
+NET "mcb3_dram_a[5]" LOC = "H4" ;
+NET "mcb3_dram_a[6]" LOC = "H3" ;
+NET "mcb3_dram_a[7]" LOC = "H6" ;
+NET "mcb3_dram_a[8]" LOC = "D2" ;
+NET "mcb3_dram_a[9]" LOC = "D1" ;
+NET "mcb3_dram_ba[0]" LOC = "F2" ;
+NET "mcb3_dram_ba[1]" LOC = "F1" ;
+NET "mcb3_dram_ba[2]" LOC = "E1" ;
+NET "mcb3_dram_cas_n" LOC = "K5" ;
+NET "mcb3_dram_ck" LOC = "G3" ;
+NET "mcb3_dram_ck_n" LOC = "G1" ;
+NET "mcb3_dram_cke" LOC = "H7" ;
+NET "mcb3_dram_dm" LOC = "K3" ;
+NET "mcb3_dram_dq[0]" LOC = "L2" ;
+NET "mcb3_dram_dq[10]" LOC = "N2" ;
+NET "mcb3_dram_dq[11]" LOC = "N1" ;
+NET "mcb3_dram_dq[12]" LOC = "T2" ;
+NET "mcb3_dram_dq[13]" LOC = "T1" ;
+NET "mcb3_dram_dq[14]" LOC = "U2" ;
+NET "mcb3_dram_dq[15]" LOC = "U1" ;
+NET "mcb3_dram_dq[1]" LOC = "L1" ;
+NET "mcb3_dram_dq[2]" LOC = "K2" ;
+NET "mcb3_dram_dq[3]" LOC = "K1" ;
+NET "mcb3_dram_dq[4]" LOC = "H2" ;
+NET "mcb3_dram_dq[5]" LOC = "H1" ;
+NET "mcb3_dram_dq[6]" LOC = "J3" ;
+NET "mcb3_dram_dq[7]" LOC = "J1" ;
+NET "mcb3_dram_dq[8]" LOC = "M3" ;
+NET "mcb3_dram_dq[9]" LOC = "M1" ;
+NET "mcb3_dram_dqs" LOC = "L4" ;
+NET "mcb3_dram_dqs_n" LOC = "L3" ;
+NET "mcb3_dram_odt" LOC = "K6" ;
+NET "mcb3_dram_ras_n" LOC = "L5" ;
+#NET "c3_sys_clk" LOC = "R10" ;
+#NET "c3_sys_rst_i" LOC = "M8" ;
+NET "mcb3_dram_udm" LOC = "K4" ;
+NET "mcb3_dram_udqs" LOC = "P2" ;
+NET "mcb3_dram_udqs_n" LOC = "P1" ;
+NET "mcb3_dram_we_n" LOC = "E3" ;
+
+##################################################################################
+#RZQ is required for all MCB designs. Do not move the location #
+#of this pin for ES devices.For production devices, RZQ can be moved to any #
+#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
+#a 2R resistor should be connected between RZQand ground, where R is the desired#
+#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
+##################################################################################
+NET "mcb3_rzq" LOC = "N4" ;
+##################################################################################
+#ZIO is only required for MCB designs using Calibrated Input Termination.#
+#ZIO can be moved to any valid package pin (i.e. bonded IO) within the#
+#MCB bank but must be left as a no-connect (NC) pin.#
+##################################################################################
+NET "mcb3_zio" LOC = "P4" ;
+

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