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Team I's chip tester
Shell Verilog C Tcl Ruby
branch: master

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Virtual Chip(SV)
VirtualChip
bootstrap/linux
conf
dist
doc
frequencyCounter
hdl
linux-2.6 @ 036d5b6
linux
overlay
patchq
report_group
server
toolchain-mmu @ b11d373
tools
tools2 @ 7bd938a
u-boot @ e37ae40
uClibc @ e355ed8
uClinux-dist @ 7ceec2d
uboot
.gitignore
.gitmodules
DHRYBENCH
Makefile
NOTES
README
TEST
bootstrap.sh
build_env.sh
env.sh
patch_overlay.sh
submod.sh

README

Team I's project.

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