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A RISC-V processor
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doc doc: update toolchain note Dec 3, 2018
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This project is a single-issue RISC processor in SystemVerilog 1800-2012. The processor executes the base integer instruction set of the user level 32-bit RISC-V ISA (RV32I).


The design is targeted for Xilinx 7 Series FPGAs and SoCs. The Arty board from Digilent is used for development and testing.



Xilinx Vivado 2016.2 is used for hardware synthesis and simulation. The RISC-V GNU toolchain is used for software compiling and linking.

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