Skip to content
A RISC-V processor
Branch: master
Clone or download
Fetching latest commit…
Cannot retrieve the latest commit at this time.
Permalink
Type Name Latest commit message Commit time
Failed to load latest commit information.
doc doc: update toolchain note Dec 3, 2018
rtl rtl: rename package core -> rv32 Dec 4, 2018
scripts move loader to scripts subdir Oct 1, 2016
sim
src src: update make for new compiler and path Dec 4, 2018
xgui ip: move to IP-XACT to top level Oct 11, 2016
.gitignore xpr: add vivado project generation script Dec 5, 2018
LICENSE doc: update LICENSE copyright dates Dec 4, 2018
Makefile add IP target Sep 30, 2016
README.md doc: fix image links Dec 11, 2018
component.xml
xpr.tcl xpr: add vivado project generation script Dec 5, 2018

README.md

RV32CPU

Diagram

Summary

This project is a single-issue RISC processor in SystemVerilog 1800-2012. The processor executes the base integer instruction set of the user level 32-bit RISC-V ISA (RV32I).

Platforms

The design is targeted for Xilinx 7 Series FPGAs and SoCs. The Arty board from Digilent is used for development and testing.

VivadoSystem

Dependencies

Xilinx Vivado 2016.2 is used for hardware synthesis and simulation. The RISC-V GNU toolchain is used for software compiling and linking.

You can’t perform that action at this time.