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jit_codegen_x86_64.cpp
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/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
*/
#include "jit_codegen.h"
#include "jit_codecache.h"
#include "jit_compiler.h"
#include "jit_frontend.h"
#include "jit_dump.h"
#include <asmjit/core.h>
#include <asmjit/x86.h>
#if WASM_ENABLE_FAST_JIT_DUMP != 0
#include <Zydis/Zydis.h>
#endif
#define CODEGEN_CHECK_ARGS 1
#define CODEGEN_DUMP 0
using namespace asmjit;
static char *code_block_switch_to_jitted_from_interp = NULL;
static char *code_block_return_to_interp_from_jitted = NULL;
#if WASM_ENABLE_LAZY_JIT != 0
static char *code_block_compile_fast_jit_and_then_call = NULL;
#endif
typedef enum {
REG_BPL_IDX = 0,
REG_AXL_IDX,
REG_BXL_IDX,
REG_CXL_IDX,
REG_DXL_IDX,
REG_DIL_IDX,
REG_SIL_IDX,
REG_I8_FREE_IDX = REG_SIL_IDX
} RegIndexI8;
typedef enum {
REG_BP_IDX = 0,
REG_AX_IDX,
REG_BX_IDX,
REG_CX_IDX,
REG_DX_IDX,
REG_DI_IDX,
REG_SI_IDX,
REG_I16_FREE_IDX = REG_SI_IDX
} RegIndexI16;
typedef enum {
REG_EBP_IDX = 0,
REG_EAX_IDX,
REG_EBX_IDX,
REG_ECX_IDX,
REG_EDX_IDX,
REG_EDI_IDX,
REG_ESI_IDX,
REG_I32_FREE_IDX = REG_ESI_IDX
} RegIndexI32;
typedef enum {
REG_RBP_IDX = 0,
REG_RAX_IDX,
REG_RBX_IDX,
REG_RCX_IDX,
REG_RDX_IDX,
REG_RDI_IDX,
REG_RSI_IDX,
REG_RSP_IDX,
REG_R8_IDX,
REG_R9_IDX,
REG_R10_IDX,
REG_R11_IDX,
REG_R12_IDX,
REG_R13_IDX,
REG_R14_IDX,
REG_R15_IDX,
REG_I64_FREE_IDX = REG_RSI_IDX
} RegIndexI64;
/* clang-format off */
x86::Gp regs_i8[] = {
x86::bpl, x86::al, x86::bl, x86::cl,
x86::dl, x86::dil, x86::sil, x86::spl,
x86::r8b, x86::r9b, x86::r10b, x86::r11b,
x86::r12b, x86::r13b, x86::r14b, x86::r15b
};
x86::Gp regs_i16[] = {
x86::bp, x86::ax, x86::bx, x86::cx,
x86::dx, x86::di, x86::si, x86::sp,
x86::r8w, x86::r9w, x86::r10w, x86::r11w,
x86::r12w, x86::r13w, x86::r14w, x86::r15w
};
x86::Gp regs_i32[] = {
x86::ebp, x86::eax, x86::ebx, x86::ecx,
x86::edx, x86::edi, x86::esi, x86::esp,
x86::r8d, x86::r9d, x86::r10d, x86::r11d,
x86::r12d, x86::r13d, x86::r14d, x86::r15d
};
x86::Gp regs_i64[] = {
x86::rbp, x86::rax, x86::rbx, x86::rcx,
x86::rdx, x86::rdi, x86::rsi, x86::rsp,
x86::r8, x86::r9, x86::r10, x86::r11,
x86::r12, x86::r13, x86::r14, x86::r15,
};
#define REG_F32_FREE_IDX 15
#define REG_F64_FREE_IDX 15
x86::Xmm regs_float[] = {
x86::xmm0,
x86::xmm1,
x86::xmm2,
x86::xmm3,
x86::xmm4,
x86::xmm5,
x86::xmm6,
x86::xmm7,
x86::xmm8,
x86::xmm9,
x86::xmm10,
x86::xmm11,
x86::xmm12,
x86::xmm13,
x86::xmm14,
x86::xmm15,
};
/* clang-format on */
int
jit_codegen_interp_jitted_glue(void *exec_env, JitInterpSwitchInfo *info,
uint32 func_idx, void *target)
{
typedef int32 (*F)(const void *exec_env, void *info, uint32 func_idx,
const void *target);
union {
F f;
void *v;
} u;
u.v = code_block_switch_to_jitted_from_interp;
return u.f(exec_env, info, func_idx, target);
}
#define PRINT_LINE() LOG_VERBOSE("<Line:%d>\n", __LINE__)
#if CODEGEN_DUMP != 0
#define GOTO_FAIL \
do { \
PRINT_LINE(); \
goto fail; \
} while (0)
#else
#define GOTO_FAIL goto fail
#endif
#if CODEGEN_CHECK_ARGS == 0
#define CHECK_EQKIND(reg0, reg1) (void)0
#define CHECK_CONST(reg0) (void)0
#define CHECK_NCONST(reg0) (void)0
#define CHECK_KIND(reg0, type) (void)0
#define CHECK_REG_NO(no, kind) (void)0
#else
/* Check if two register's kind is equal */
#define CHECK_EQKIND(reg0, reg1) \
do { \
if (jit_reg_kind(reg0) != jit_reg_kind(reg1)) { \
PRINT_LINE(); \
LOG_VERBOSE("reg type not equal:\n"); \
jit_dump_reg(cc, reg0); \
jit_dump_reg(cc, reg1); \
GOTO_FAIL; \
} \
} while (0)
/* Check if a register is an const */
#define CHECK_CONST(reg0) \
do { \
if (!jit_reg_is_const(reg0)) { \
PRINT_LINE(); \
LOG_VERBOSE("reg is not const:\n"); \
jit_dump_reg(cc, reg0); \
GOTO_FAIL; \
} \
} while (0)
/* Check if a register is not an const */
#define CHECK_NCONST(reg0) \
do { \
if (jit_reg_is_const(reg0)) { \
PRINT_LINE(); \
LOG_VERBOSE("reg is const:\n"); \
jit_dump_reg(cc, reg0); \
GOTO_FAIL; \
} \
} while (0)
/* Check if a register is a special type */
#define CHECK_KIND(reg0, type) \
do { \
if (jit_reg_kind(reg0) != type) { \
PRINT_LINE(); \
LOG_VERBOSE("invalid reg type %d, expected is: %d", \
jit_reg_kind(reg0), type); \
jit_dump_reg(cc, reg0); \
GOTO_FAIL; \
} \
} while (0)
#define CHECK_I32_REG_NO(no) \
do { \
if ((uint32)no >= sizeof(regs_i32) / sizeof(regs_i32[0])) \
GOTO_FAIL; \
} while (0)
#define CHECK_I64_REG_NO(no) \
do { \
if ((uint32)no >= sizeof(regs_i64) / sizeof(regs_i64[0])) \
GOTO_FAIL; \
} while (0)
#define CHECK_F32_REG_NO(no) \
do { \
if ((uint32)no >= sizeof(regs_float) / sizeof(regs_float[0])) \
GOTO_FAIL; \
} while (0)
#define CHECK_F64_REG_NO(no) \
do { \
if ((uint32)no >= sizeof(regs_float) / sizeof(regs_float[0])) \
GOTO_FAIL; \
} while (0)
/* Check if a register number is valid */
#define CHECK_REG_NO(no, kind) \
do { \
if (kind == JIT_REG_KIND_I32 || kind == JIT_REG_KIND_I64) { \
CHECK_I32_REG_NO(no); \
CHECK_I64_REG_NO(no); \
} \
else if (kind == JIT_REG_KIND_F32 || kind == JIT_REG_KIND_F64) { \
CHECK_F32_REG_NO(no); \
CHECK_F64_REG_NO(no); \
} \
else \
GOTO_FAIL; \
} while (0)
#endif /* end of CODEGEN_CHECK_ARGS == 0 */
/* Load one operand from insn and check none */
#define LOAD_1ARG() r0 = *jit_insn_opnd(insn, 0)
/* Load two operands from insn and check if r0 is non-const */
#define LOAD_2ARGS() \
r0 = *jit_insn_opnd(insn, 0); \
r1 = *jit_insn_opnd(insn, 1); \
CHECK_NCONST(r0)
/* Load three operands from insn and check if r0 is non-const */
#define LOAD_3ARGS() \
r0 = *jit_insn_opnd(insn, 0); \
r1 = *jit_insn_opnd(insn, 1); \
r2 = *jit_insn_opnd(insn, 2); \
CHECK_NCONST(r0)
/* Load three operands from insn and check none */
#define LOAD_3ARGS_NO_ASSIGN() \
r0 = *jit_insn_opnd(insn, 0); \
r1 = *jit_insn_opnd(insn, 1); \
r2 = *jit_insn_opnd(insn, 2);
/* Load four operands from insn and check if r0 is non-const */
#define LOAD_4ARGS() \
r0 = *jit_insn_opnd(insn, 0); \
r1 = *jit_insn_opnd(insn, 1); \
r2 = *jit_insn_opnd(insn, 2); \
r3 = *jit_insn_opnd(insn, 3); \
CHECK_NCONST(r0)
/* Load five operands from insn and check if r0 is non-const */
#define LOAD_4ARGS_NO_ASSIGN() \
r0 = *jit_insn_opnd(insn, 0); \
r1 = *jit_insn_opnd(insn, 1); \
r2 = *jit_insn_opnd(insn, 2); \
r3 = *jit_insn_opnd(insn, 3);
class JitErrorHandler : public ErrorHandler
{
public:
Error err;
JitErrorHandler()
: err(kErrorOk)
{}
void handleError(Error e, const char *msg, BaseEmitter *base) override
{
(void)msg;
(void)base;
this->err = e;
}
};
/* Alu opcode */
typedef enum { ADD, SUB, MUL, DIV_S, REM_S, DIV_U, REM_U, MIN, MAX } ALU_OP;
/* Bit opcode */
typedef enum { OR, XOR, AND } BIT_OP;
/* Shift opcode */
typedef enum { SHL, SHRS, SHRU, ROTL, ROTR } SHIFT_OP;
/* Bitcount opcode */
typedef enum { CLZ, CTZ, POPCNT } BITCOUNT_OP;
/* Condition opcode */
typedef enum { EQ, NE, GTS, GES, LTS, LES, GTU, GEU, LTU, LEU } COND_OP;
typedef union _cast_float_to_integer {
float f;
uint32 i;
} cast_float_to_integer;
typedef union _cast_double_to_integer {
double d;
uint64 i;
} cast_double_to_integer;
static uint32
local_log2(uint32 data)
{
uint32 ret = 0;
while (data >>= 1) {
ret++;
}
return ret;
}
static uint64
local_log2l(uint64 data)
{
uint64 ret = 0;
while (data >>= 1) {
ret++;
}
return ret;
}
/* Jmp type */
typedef enum JmpType {
JMP_DST_LABEL_REL, /* jmp to dst label with relative addr */
JMP_DST_LABEL_ABS, /* jmp to dst label with absolute addr */
JMP_END_OF_CALLBC, /* jmp to end of CALLBC */
JMP_LOOKUPSWITCH_BASE, /* LookupSwitch table base addr */
} JmpType;
/**
* Jmp info, save the info on first encoding pass,
* and replace the offset with exact offset when the code cache
* has been allocated actually.
*/
typedef struct JmpInfo {
bh_list_link link;
JmpType type;
uint32 label_src;
uint32 offset;
union {
uint32 label_dst;
} dst_info;
} JmpInfo;
static bool
label_is_neighboring(JitCompContext *cc, int32 label_prev, int32 label_succ)
{
return (label_prev == 0 && label_succ == 2)
|| (label_prev >= 2 && label_succ == label_prev + 1)
|| (label_prev == (int32)jit_cc_label_num(cc) - 1
&& label_succ == 1);
}
static bool
label_is_ahead(JitCompContext *cc, int32 label_dst, int32 label_src)
{
return (label_dst == 0 && label_src != 0)
|| (label_dst != 1 && label_src == 1)
|| (2 <= label_dst && label_dst < label_src
&& label_src <= (int32)jit_cc_label_num(cc) - 1);
}
/**
* Encode jumping from one label to the other label
*
* @param a the assembler to emit the code
* @param jmp_info_list the jmp info list
* @param label_dst the index of dst label
* @param label_src the index of src label
*
* @return true if success, false if failed
*/
static bool
jmp_from_label_to_label(x86::Assembler &a, bh_list *jmp_info_list,
int32 label_dst, int32 label_src)
{
Imm imm(INT32_MAX);
JmpInfo *node;
node = (JmpInfo *)jit_calloc(sizeof(JmpInfo));
if (!node)
return false;
node->type = JMP_DST_LABEL_REL;
node->label_src = label_src;
node->dst_info.label_dst = label_dst;
node->offset = a.code()->sectionById(0)->buffer().size() + 2;
bh_list_insert(jmp_info_list, node);
a.jmp(imm);
return true;
}
/**
* Encode detecting compare result register according to condition code
* and then jumping to suitable label when the condition is met
*
* @param cc the compiler context
* @param a the assembler to emit the code
* @param jmp_info_list the jmp info list
* @param label_src the index of src label
* @param op the opcode of condition operation
* @param r1 the label info when condition is met
* @param r2 the label info when condition is unmet, do nothing if VOID
* @param is_last_insn if current insn is the last insn of current block
*
* @return true if success, false if failed
*/
static bool
cmp_r_and_jmp_label(JitCompContext *cc, x86::Assembler &a,
bh_list *jmp_info_list, int32 label_src, COND_OP op,
JitReg r1, JitReg r2, bool is_last_insn)
{
Imm imm(INT32_MAX);
JmpInfo *node;
node = (JmpInfo *)jit_malloc(sizeof(JmpInfo));
if (!node)
return false;
node->type = JMP_DST_LABEL_REL;
node->label_src = label_src;
node->dst_info.label_dst = jit_reg_no(r1);
node->offset = a.code()->sectionById(0)->buffer().size() + 2;
bh_list_insert(jmp_info_list, node);
bool fp_cmp = cc->last_cmp_on_fp;
bh_assert(!fp_cmp || (fp_cmp && (op == GTS || op == GES)));
switch (op) {
case EQ:
{
a.je(imm);
break;
}
case NE:
{
a.jne(imm);
break;
}
case GTS:
{
if (fp_cmp)
a.ja(imm);
else
a.jg(imm);
break;
}
case LES:
{
a.jng(imm);
break;
}
case GES:
{
if (fp_cmp)
a.jae(imm);
else
a.jnl(imm);
break;
}
case LTS:
{
a.jl(imm);
break;
}
case GTU:
{
a.ja(imm);
break;
}
case LEU:
{
a.jna(imm);
break;
}
case GEU:
{
a.jnb(imm);
break;
}
case LTU:
{
a.jb(imm);
break;
}
default:
{
bh_assert(0);
break;
}
}
if (r2) {
int32 label_dst = jit_reg_no(r2);
if (!(is_last_insn && label_is_neighboring(cc, label_src, label_dst)))
if (!jmp_from_label_to_label(a, jmp_info_list, label_dst,
label_src))
return false;
}
return true;
}
#if WASM_ENABLE_FAST_JIT_DUMP != 0
static void
dump_native(char *data, uint32 length)
{
/* Initialize decoder context */
ZydisDecoder decoder;
ZydisDecoderInit(&decoder, ZYDIS_MACHINE_MODE_LONG_64,
ZYDIS_STACK_WIDTH_64);
/* Initialize formatter */
ZydisFormatter formatter;
ZydisFormatterInit(&formatter, ZYDIS_FORMATTER_STYLE_INTEL);
/* Loop over the instructions in our buffer */
ZyanU64 runtime_address = (ZyanU64)(uintptr_t)data;
ZyanUSize offset = 0;
ZydisDecodedInstruction instruction;
ZydisDecodedOperand operands[ZYDIS_MAX_OPERAND_COUNT_VISIBLE];
while (ZYAN_SUCCESS(ZydisDecoderDecodeFull(
&decoder, data + offset, length - offset, &instruction, operands,
ZYDIS_MAX_OPERAND_COUNT_VISIBLE, ZYDIS_DFLAG_VISIBLE_OPERANDS_ONLY))) {
/* Print current instruction pointer */
os_printf("%012" PRIX64 " ", runtime_address);
/* Format & print the binary instruction structure to
human readable format */
char buffer[256];
ZydisFormatterFormatInstruction(&formatter, &instruction, operands,
instruction.operand_count_visible,
buffer, sizeof(buffer),
runtime_address);
puts(buffer);
offset += instruction.length;
runtime_address += instruction.length;
}
}
#endif
/**
* Encode extending register of byte to register of dword
* @param a the assembler to emit the code
* @param reg_no_dst the no of dst register
* @param reg_no_src tho no of src register
* @param is_signed the data is signed or unsigned
*
* @return true if success, false otherwise
*/
static bool
extend_r8_to_r32(x86::Assembler &a, int32 reg_no_dst, int32 reg_no_src,
bool is_signed)
{
if (is_signed) {
a.movsx(regs_i32[reg_no_dst], regs_i8[reg_no_src]);
}
else {
a.movzx(regs_i32[reg_no_dst], regs_i8[reg_no_src]);
}
return true;
}
/**
* Encode extending register of word to register of dword
* @param a the assembler to emit the code
* @param reg_no_dst the no of dst register
* @param reg_no_src tho no of src register
* @param is_signed the data is signed or unsigned
*
* @return true if success, false otherwise
*/
static bool
extend_r16_to_r32(x86::Assembler &a, int32 reg_no_dst, int32 reg_no_src,
bool is_signed)
{
if (is_signed) {
a.movsx(regs_i32[reg_no_dst], regs_i16[reg_no_src]);
}
else {
a.movzx(regs_i32[reg_no_dst], regs_i16[reg_no_src]);
}
return true;
}
/**
* Encode extending register of byte to register of qword
* @param a the assembler to emit the code
* @param reg_no_dst the no of dst register
* @param reg_no_src tho no of src register
* @param is_signed the data is signed or unsigned
*
* @return true if success, false otherwise
*/
static bool
extend_r8_to_r64(x86::Assembler &a, int32 reg_no_dst, int32 reg_no_src,
bool is_signed)
{
if (is_signed) {
a.movsx(regs_i64[reg_no_dst], regs_i8[reg_no_src]);
}
else {
a.movzx(regs_i64[reg_no_dst], regs_i8[reg_no_src]);
}
return true;
}
/**
* Encode extending register of word to register of qword
* @param a the assembler to emit the code
* @param reg_no_dst the no of dst register
* @param reg_no_src tho no of src register
* @param is_signed the data is signed or unsigned
*
* @return true if success, false otherwise
*/
static bool
extend_r16_to_r64(x86::Assembler &a, int32 reg_no_dst, int32 reg_no_src,
bool is_signed)
{
if (is_signed) {
a.movsx(regs_i64[reg_no_dst], regs_i16[reg_no_src]);
}
else {
a.movzx(regs_i64[reg_no_dst], regs_i16[reg_no_src]);
}
return true;
}
/**
* Encode extending register of dword to register of qword
* @param a the assembler to emit the code
* @param reg_no_dst the no of dst register
* @param reg_no_src tho no of src register
* @param is_signed the data is signed or unsigned
*
* @return true if success, false otherwise
*/
static bool
extend_r32_to_r64(x86::Assembler &a, int32 reg_no_dst, int32 reg_no_src,
bool is_signed)
{
if (is_signed) {
a.movsxd(regs_i64[reg_no_dst], regs_i32[reg_no_src]);
}
else {
/*
* The upper 32-bit will be zero-extended, ref to Intel document,
* 3.4.1.1 General-Purpose Registers: 32-bit operands generate
* a 32-bit result, zero-extended to a 64-bit result in the
* destination general-purpose register
*/
a.mov(regs_i32[reg_no_dst], regs_i32[reg_no_src]);
}
return true;
}
static bool
mov_r_to_r_i32(x86::Assembler &a, int32 reg_no_dst, int32 reg_no_src);
static bool
mov_r_to_r_i64(x86::Assembler &a, int32 reg_no_dst, int32 reg_no_src);
static void
mov_r_to_r(x86::Assembler &a, uint32 kind_dst, int32 reg_no_dst,
int32 reg_no_src)
{
if (kind_dst == JIT_REG_KIND_I32)
mov_r_to_r_i32(a, reg_no_dst, reg_no_src);
else if (kind_dst == JIT_REG_KIND_I64)
mov_r_to_r_i64(a, reg_no_dst, reg_no_src);
else if (kind_dst == JIT_REG_KIND_F32) {
/* TODO */
bh_assert(0);
}
else if (kind_dst == JIT_REG_KIND_F64) {
/* TODO */
bh_assert(0);
}
else {
bh_assert(0);
}
}
/**
* Encode moving memory to a register
*
* @param a the assembler to emit the code
* @param bytes_dst the bytes number of the data,
* could be 1(byte), 2(short), 4(int32), 8(int64),
* skipped by float and double
* @param kind_dst the kind of data to move, could be I32, I64, F32 or F64
* @param is_signed whether the data is signed or unsigned
* @param reg_no_dst the index of dest register
* @param m_src the memory operand which contains the source data
*
* @return true if success, false otherwise
*/
static bool
mov_m_to_r(x86::Assembler &a, uint32 bytes_dst, uint32 kind_dst, bool is_signed,
int32 reg_no_dst, x86::Mem &m_src)
{
if (kind_dst == JIT_REG_KIND_I32) {
switch (bytes_dst) {
case 1:
case 2:
if (is_signed)
a.movsx(regs_i32[reg_no_dst], m_src);
else
a.movzx(regs_i32[reg_no_dst], m_src);
break;
case 4:
a.mov(regs_i32[reg_no_dst], m_src);
break;
default:
bh_assert(0);
return false;
}
}
else if (kind_dst == JIT_REG_KIND_I64) {
switch (bytes_dst) {
case 1:
case 2:
if (is_signed)
a.movsx(regs_i64[reg_no_dst], m_src);
else
a.movzx(regs_i64[reg_no_dst], m_src);
break;
case 4:
if (is_signed)
a.movsxd(regs_i64[reg_no_dst], m_src);
else
/*
* The upper 32-bit will be zero-extended, ref to Intel
* document, 3.4.1.1 General-Purpose Registers: 32-bit
* operands generate a 32-bit result, zero-extended to
* a 64-bit result in the destination general-purpose
* register
*/
a.mov(regs_i32[reg_no_dst], m_src);
break;
case 8:
a.mov(regs_i64[reg_no_dst], m_src);
break;
default:
bh_assert(0);
return false;
}
}
else if (kind_dst == JIT_REG_KIND_F32) {
a.movss(regs_float[reg_no_dst], m_src);
}
else if (kind_dst == JIT_REG_KIND_F64) {
a.movsd(regs_float[reg_no_dst], m_src);
}
return true;
}
/**
* Encode moving register to memory
*
* @param a the assembler to emit the code
* @param bytes_dst the bytes number of the data,
* could be 1(byte), 2(short), 4(int32), 8(int64),
* skipped by float and double
* @param kind_dst the kind of data to move, could be I32, I64, F32 or F64
* @param is_signed whether the data is signed or unsigned
* @param m_dst the dest memory operand
* @param reg_no_src the index of dest register
*
* @return true if success, false otherwise
*/
static bool
mov_r_to_m(x86::Assembler &a, uint32 bytes_dst, uint32 kind_dst,
x86::Mem &m_dst, int32 reg_no_src)
{
if (kind_dst == JIT_REG_KIND_I32) {
bh_assert(reg_no_src < 16);
switch (bytes_dst) {
case 1:
a.mov(m_dst, regs_i8[reg_no_src]);
break;
case 2:
a.mov(m_dst, regs_i16[reg_no_src]);
break;
case 4:
a.mov(m_dst, regs_i32[reg_no_src]);
break;
default:
bh_assert(0);
return false;
}
}
else if (kind_dst == JIT_REG_KIND_I64) {
bh_assert(reg_no_src < 16);
switch (bytes_dst) {
case 1:
a.mov(m_dst, regs_i8[reg_no_src]);
break;
case 2:
a.mov(m_dst, regs_i16[reg_no_src]);
break;
case 4:
a.mov(m_dst, regs_i32[reg_no_src]);
break;
case 8:
a.mov(m_dst, regs_i64[reg_no_src]);
break;
default:
bh_assert(0);
return false;
}
}
else if (kind_dst == JIT_REG_KIND_F32) {
a.movss(m_dst, regs_float[reg_no_src]);
}
else if (kind_dst == JIT_REG_KIND_F64) {
a.movsd(m_dst, regs_float[reg_no_src]);
}
return true;
}
/**
* Encode moving immediate data to memory
*
* @param m dst memory
* @param imm src immediate data
*
* @return new stream
*/
static bool
mov_imm_to_m(x86::Assembler &a, x86::Mem &m_dst, Imm imm_src, uint32 bytes_dst)
{
if (bytes_dst == 8) {
int64 value = imm_src.value();
if (value >= INT32_MIN && value <= INT32_MAX) {
imm_src.setValue((int32)value);
a.mov(m_dst, imm_src);
}
else {
/* There is no instruction `MOV m64, imm64`, we use
two instructions to implement it */
a.mov(regs_i64[REG_I64_FREE_IDX], imm_src);
a.mov(m_dst, regs_i64[REG_I64_FREE_IDX]);
}
}
else
a.mov(m_dst, imm_src);
return true;
}
#if WASM_ENABLE_SHARED_MEMORY != 0
/**
* Encode exchange register with memory
*
* @param a the assembler to emit the code
* @param bytes_dst the bytes number of the data,
* could be 1(byte), 2(short), 4(int32), 8(int64),
* skipped by float and double
* @param kind_dst the kind of data to move, could only be I32 or I64
* @param m_dst the dest memory operand
* @param reg_no_src the index of dest register
*
* @return true if success, false otherwise
*/
static bool
xchg_r_to_m(x86::Assembler &a, uint32 bytes_dst, uint32 kind_dst,
x86::Mem &m_dst, int32 reg_no_src)
{
bh_assert((kind_dst == JIT_REG_KIND_I32 && bytes_dst <= 4)
|| kind_dst == JIT_REG_KIND_I64);
bh_assert(reg_no_src < 16);
switch (bytes_dst) {
case 1:
a.xchg(m_dst, regs_i8[reg_no_src]);
break;
case 2:
a.xchg(m_dst, regs_i16[reg_no_src]);
break;
case 4:
a.xchg(m_dst, regs_i32[reg_no_src]);
break;
case 8:
a.xchg(m_dst, regs_i64[reg_no_src]);
break;
default:
bh_assert(0);
return false;
}
return true;
}
#endif
/**
* Encode loading register data from memory with imm base and imm offset
*
* @param a the assembler to emit the code
* @param bytes_dst the bytes number of the data,
* could be 1(byte), 2(short), 4(int32), 8(int64), skipped by
* float/double
* @param kind_dst the kind of data to move, could be I32, I64, F32 or F64
* @param is_signed the data is signed or unsigned
* @param reg_no_dst the index of dest register
* @param base the base address of the memory
* @param offset the offset address of the memory
*
* @return true if success, false otherwise
*/
static bool
ld_r_from_base_imm_offset_imm(x86::Assembler &a, uint32 bytes_dst,
uint32 kind_dst, bool is_signed, int32 reg_no_dst,
int32 base, int32 offset)
{
x86::Mem m((uintptr_t)(base + offset), bytes_dst);
return mov_m_to_r(a, bytes_dst, kind_dst, is_signed, reg_no_dst, m);
}
/**
* Encode loading register data from memory with imm base and register offset
*
* @param a the assembler to emit the code
* @param bytes_dst the bytes number of the data,
* could be 1(byte), 2(short), 4(int32), 8(int64), skipped by
* float/double
* @param kind_dst the kind of data to move, could be I32, I64, F32 or F64
* @param is_signed the data is signed or unsigned
* @param reg_no_dst the index of dest register
* @param base the base address of the memory
* @param reg_no_offset the no of register which stores the offset of the memory
*
* @return true if success, false otherwise
*/
static bool
ld_r_from_base_imm_offset_r(x86::Assembler &a, uint32 bytes_dst,
uint32 kind_dst, bool is_signed, int32 reg_no_dst,
int32 base, int32 reg_no_offset)
{
x86::Mem m(regs_i64[reg_no_offset], base, bytes_dst);
return mov_m_to_r(a, bytes_dst, kind_dst, is_signed, reg_no_dst, m);
}
/**
* Encode loading register data from memory with register base and imm offset
*
* @param a the assembler to emit the code
* @param bytes_dst the bytes number of the data,
* could be 1(byte), 2(short), 4(int32), 8(int64), skipped by
* float/double
* @param kind_dst the kind of data to move, could be I32, I64, F32 or F64
* @param is_signed the data is signed or unsigned
* @param reg_no_dst the index of dest register
* @param reg_no_base the no of register which stores the base of the memory
* @param offset the offset address of the memory
*
* @return true if success, false otherwise
*/
static bool
ld_r_from_base_r_offset_imm(x86::Assembler &a, uint32 bytes_dst,
uint32 kind_dst, bool is_signed, int32 reg_no_dst,
int32 reg_no_base, int32 offset)
{
x86::Mem m(regs_i64[reg_no_base], offset, bytes_dst);
return mov_m_to_r(a, bytes_dst, kind_dst, is_signed, reg_no_dst, m);
}
/**
* Encode loading register data from memory with register base and register
* offset