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initial commit : test setup

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0 parents commit 89c7b512ecfdd1798c246e213273754a450ab0e6 @tuxcodejohn tuxcodejohn committed Mar 26, 2011
Showing with 696 additions and 0 deletions.
  1. +446 −0 firmware_buzzIface/Makefile
  2. +73 −0 firmware_buzzIface/buzzIface.c
  3. +107 −0 firmware_buzzIface/usart.c
  4. +70 −0 firmware_buzzIface/usart.h
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@@ -0,0 +1,73 @@
+/*
+ * ============================================================================
+ *
+ * Filename: buzzIface.c
+ *
+ * Description: this is the first test
+ *
+ * Version: 0.0
+ * Revision: none
+ * Compiler: gcc
+ *
+ * Author: Johannes Steinmetz (js), john ät tuxcode dot org
+ *
+ * ============================================================================
+ */
+
+
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <avr/io.h>
+#include <avr/interrupt.h>
+/*#include <avr/pgmspace.h>*/
+#include <avr/sleep.h>
+#include <util/delay.h>
+#include "usart.h"
+
+
+inline void hardware_init(void)
+{
+ // Configure LED Port C as OUTPUT:
+ DDRC = (1<<DDC3) | (1<<DDC2) ;
+ PORTC = 0 | (1<<DDC2);
+ USART_Init();
+}
+
+
+int main(void)
+{
+ hardware_init();
+ sei();
+//------------------------------------
+
+ uint8_t c ,i ;
+ char buf[16];
+
+
+ USART_puts("Test");
+ USART_puts("\n\r");
+
+
+ for(;;){ //ever
+
+ i = uart_getc_nb(&c);
+ if (i) {
+ USART_putc(c);
+ switch (c){
+ case 'r' :
+ PORTC = 0 | (1<<DDC3);
+ break;
+ case 'g' :
+ PORTC = 0 | (1<<DDC2);
+ break;
+ default :
+ PORTC = 0 | (1<<DDC3)|(1<<DDC2);
+ }
+ }
+
+ }
+
+ /* never gets here*/
+ return 0;
+}
@@ -0,0 +1,107 @@
+#include <avr/io.h>
+#include <avr/interrupt.h>
+#include <avr/pgmspace.h>
+#include <avr/wdt.h>
+#include <stdarg.h>
+
+/*#include "main.h"*/
+#include "usart.h"
+
+
+#define UART_RXBUFSIZE 64
+
+volatile static uint8_t rxbuf[UART_RXBUFSIZE];
+volatile static uint8_t *volatile rxhead, *volatile rxtail;
+
+
+
+uint8_t uart_getc_nb(uint8_t *c)
+{
+ if (rxhead==rxtail) return 0;
+ *c = *rxtail;
+ if (++rxtail == (rxbuf + UART_RXBUFSIZE)) rxtail = rxbuf;
+ return 1;
+}
+
+
+ISR (USART_RX_vect)
+{
+
+ int diff;
+ uint8_t c;
+ c=UDR;
+ diff = rxhead - rxtail;
+ if (diff < 0) diff += UART_RXBUFSIZE;
+ if (diff < UART_RXBUFSIZE -1)
+ {
+ *rxhead = c;
+ ++rxhead;
+ if (rxhead == (rxbuf + UART_RXBUFSIZE)) rxhead = rxbuf;
+ };
+
+
+
+
+}
+
+void USART_Init (void)
+{
+ // set clock divider
+ #undef BAUD
+ #define BAUD USART_BAUD
+ #include <util/setbaud.h>
+ UBRRH = UBRRH_VALUE;
+ UBRRL = UBRRL_VALUE;
+
+#if USE_2X
+ UCSRA |= (1 << U2X); // enable double speed operation
+#else
+ UCSRA &= ~(1 << U2X); // disable double speed operation
+#endif
+
+ // set 8N1
+ UCSRC = (1 << UCSZ1) | (1 << UCSZ0);
+ UCSRB &= ~(1 << UCSZ2);
+
+ // flush receive buffer
+ while ( UCSRA & (1 << RXC) ) UDR;
+
+ UCSRB |= (1 << RXEN) | (1 << TXEN);
+ UCSRB |= (1 << RXCIE);
+
+ rxhead = rxtail = rxbuf;
+
+}
+
+
+
+
+//*****************************************************************************
+//
+void USART_putc (char c)
+{
+ loop_until_bit_is_set(UCSRA, UDRE);
+ UDR = c;
+}
+
+//*****************************************************************************
+//
+void USART_puts (char *s)
+{
+ while (*s)
+ {
+ USART_putc (*s);
+ s++;
+ }
+}
+
+//*****************************************************************************
+//
+void USART_puts_p (const char *s)
+{
+ while (pgm_read_byte(s))
+ {
+ USART_putc (pgm_read_byte(s));
+ s++;
+ }
+}
@@ -0,0 +1,70 @@
+#ifndef _USART_H
+#define _USART_H
+
+//*****************************************************************************
+//
+#ifndef FALSE
+#define FALSE 0
+#endif
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+// Baud rate of the USART
+//#define USART_BAUD 57600
+#define USART_BAUD 115200
+
+
+//*****************************************************************************
+//
+
+//*****************************************************************************
+//
+void USART_Init (void);
+
+
+void USART_putc (char c);
+void USART_puts (char *s);
+void USART_puts_p (const char *s);
+
+uint8_t uart_getc_nb(uint8_t*);
+
+//-----------------------
+#define UCSRA UCSR0A
+#define UCSRB UCSR0B
+#define UCSRC UCSR0C
+#define UDR UDR0
+#define UBRRL UBRR0L
+#define UBRRH UBRR0H
+
+// UCSRA
+#define RXC RXC0
+#define TXC TXC0
+#define UDRE UDRE0
+#define FE FE0
+#define UPE UPE0
+#define U2X U2X0
+#define MPCM MPCM0
+
+// UCSRB
+#define RXCIE RXCIE0
+#define TXCIE TXCIE0
+#define UDRIE UDRIE0
+#define TXEN TXEN0
+#define RXEN RXEN0
+#define UCSZ2 UCSZ02
+#define RXB8 RXB80
+#define TXB8 TXB80
+
+// UCSRC
+#define UMSEL1 UMSEL01
+#define UMSEL0 UMSEL00
+#define UPM1 UPM01
+#define UPM0 UPM00
+#define USBS USBS0
+#define UCSZ1 UCSZ01
+#define UCSZ0 UCSZ00
+#define UCPOL UCPOL0
+
+
+#endif

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