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208 lines (206 loc) · 4.39 KB
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import "primitives/core.futil";
import "primitives/binary_operators.futil";
import "primitives/memories/comb.futil";
component adder<"pos"={0}>(val1: 32, val2: 32) -> (out: 32) {
cells {
@pos{1} reg_1 = std_reg(32);
@pos{2} add_2 = std_add(32);
}
wires {
group compute_sum<"pos"={3}> {
add_2.left = val1;
add_2.right = val2;
reg_1.write_en = 1'd1;
reg_1.in = add_2.out;
compute_sum[done] = reg_1.done;
}
out = reg_1.out;
}
control {
@pos{4} compute_sum;
}
}
component abs_diff<"pos"={5}>(val1: 32, val2: 32) -> (out: 32) {
cells {
@pos{6} reg_1 = std_reg(32);
@pos{7} ge = std_ge(32);
@pos{8} reg_2 = std_reg(1);
@pos{9} sub_3 = std_sub(32);
@pos{10} sub_4 = std_sub(32);
@pos{12} lt_5 = std_lt(32);
}
wires {
group sub_3_group<"pos"={9}> {
sub_3.left = val1;
sub_3.right = val2;
reg_1.write_en = 1'd1;
reg_1.in = sub_3.out;
sub_3_group[done] = reg_1.done;
}
group sub_4_group<"pos"={10}> {
sub_4.left = val2;
sub_4.right = val1;
reg_1.write_en = 1'd1;
reg_1.in = sub_4.out;
sub_4_group[done] = reg_1.done;
}
group val1_ge_val2<"pos"={11}> {
ge.left = val1;
ge.right = val2;
reg_2.write_en = 1'd1;
reg_2.in = ge.out;
val1_ge_val2[done] = reg_2.done;
}
comb group lt_5_group<"pos"={12}> {
lt_5.left = val2;
lt_5.right = val1;
}
out = reg_1.out;
}
control {
@pos{15} par {
@pos{15} seq {
@pos{15} val1_ge_val2;
@pos{13} if reg_2.out {
@pos{13} sub_3_group;
} else {
@pos{13} sub_4_group;
}
}
@pos{14} if lt_5.out with lt_5_group {
@pos{14} sub_4_group;
} else {
@pos{14} sub_3_group;
}
}
}
}
component mux<"pos"={16}>(val1: 32, val2: 32, sel: 1) -> (out: 32) {
cells {
@pos{17} reg_1 = std_reg(32);
@pos{18} eq_2 = std_eq(1);
@pos{19} add_3 = std_add(32);
@pos{20} abs_diff = abs_diff();
}
wires {
comb group eq_2_group<"pos"={18}> {
eq_2.left = sel;
eq_2.right = 1'd0;
}
group add_3_group<"pos"={19}> {
add_3.left = val1;
add_3.right = val2;
reg_1.write_en = 1'd1;
reg_1.in = add_3.out;
add_3_group[done] = reg_1.done;
}
group compute_diff<"pos"={21}> {
abs_diff.val1 = val1;
abs_diff.val2 = val2;
abs_diff.go = 1'd1;
reg_1.write_en = abs_diff.done;
reg_1.in = abs_diff.out;
compute_diff[done] = reg_1.done;
}
out = reg_1.out;
}
control {
@pos{22} if eq_2.out with eq_2_group {
@pos{22} add_3_group;
} else {
@pos{22} compute_diff;
}
}
}
component map<"pos"={23}>(v: 32) -> () {
cells {
@pos{24} ref mem = comb_mem_d1(32, 10, 32);
@pos{25} reg_1 = std_reg(8);
@pos{26} reg_1_incr_1_2 = std_add(8);
@pos{27} mult_pipe_3 = std_mult_pipe(32);
@pos{28} lt_4 = std_lt(8);
}
wires {
group reg_1_incr_1_2_group<"pos"={26}> {
reg_1_incr_1_2.left = reg_1.out;
reg_1_incr_1_2.right = 8'd1;
reg_1.write_en = 1'd1;
reg_1.in = reg_1_incr_1_2.out;
reg_1_incr_1_2_group[done] = reg_1.done;
}
comb group lt_4_group<"pos"={28}> {
lt_4.left = reg_1.out;
lt_4.right = 8'd10;
}
group mul_at_position_i<"pos"={29}> {
mem.addr0 = reg_1.out;
mult_pipe_3.left = mem.read_data;
mult_pipe_3.right = v;
mem.write_en = mult_pipe_3.done ? 1'd1;
mem.write_data = mult_pipe_3.out;
mul_at_position_i[done] = mem.done;
}
}
control {
@pos{30} while lt_4.out with lt_4_group {
@pos{30} seq {
@pos{30} mul_at_position_i;
@pos{30} reg_1_incr_1_2_group;
}
}
}
}
component main<"pos"={31}>() -> () {
cells {
@pos{32} map = map();
@external @pos{33} mymem = comb_mem_d1(32, 10, 32);
}
wires {
}
control {
@pos{35} seq {
@pos{34} invoke map[mem=mymem](v=32'd42)();
}
}
}
sourceinfo #{
FILES
0: walkthrough.py
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}#