From ed7cd090930549b86ad2046959d44ea3a6c34020 Mon Sep 17 00:00:00 2001 From: Rachit Nigam Date: Fri, 6 Aug 2021 22:29:18 +0530 Subject: [PATCH] check if groups done signal depends on components input signal. Fixes #621 --- calyx/src/passes/well_formed.rs | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/calyx/src/passes/well_formed.rs b/calyx/src/passes/well_formed.rs index 715648a6d8..7ed8f18018 100644 --- a/calyx/src/passes/well_formed.rs +++ b/calyx/src/passes/well_formed.rs @@ -63,14 +63,34 @@ impl Visitor for WellFormed { for group_ref in comp.groups.iter() { let group = group_ref.borrow(); let gname = group.name(); + let mut count = 0; // Find an assignment writing to this group's done condition. - let done = group.assignments.iter().find(|assign| { + group.assignments.iter().filter(|assign| { let dst = assign.dst.borrow(); dst.is_hole() && dst.name == "done" && dst.get_parent_name() == gname - }); - if done.is_none() { + }).try_for_each(|assign| { + // Increment the number of writes to the done signal. + count += 1; + // Check if the done signal depends on the input port. + let src = assign.src.borrow(); + if let ir::PortParent::Cell(cell_wref) = &src.parent { + if matches!( + cell_wref.upgrade().borrow().prototype, + ir::CellType::ThisComponent + ) { + let msg = gname.fmt_err(&format!( + "Group's done signal depends on component's input port {}.{}", + comp.name, + src.name + )); + return Err(Error::MalformedStructure(msg)) + } + } + Ok(()) + })?; + if count == 0 { return Err(Error::MalformedStructure(gname.fmt_err( &format!( "No writes to the `done' hole for group `{}'",