Connectal is a framework for software-driven hardware development.
Bluespec 137 46
Scripts to create a boot.bin file for linux on Xilinx Zync
C 21 11
SystemVerilog 2
Generate Verilog from Atomicc IR files (which are generated from llvm-translate)
A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.
Generates Makefiles to synthesize, place, and route verilog using Vivado
Memoizes execution of build commands
The official Linux kernel from Xilinx
Translates Bluespec SystemVerilog to Kami for use with the coq proof assistant.
llvm runtime interpreter/translator
Mirror of official clang git repository located at http://llvm.org/git/clang. Updated every five minutes.
Loading…
