Connectal is a framework for software-driven hardware development.
Repository for publishing non-jekyll documentation
Mirror of tachyon-da cvc Verilog simulator
A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.
Generates Makefiles to synthesize, place, and route verilog using Vivado
Python Productivity for ZYNQ with Python board level designs
Bluespec-derived HDL based on Dart
The official Linux kernel from Xilinx
Mirror of official clang git repository located at http://llvm.org/git/clang. Updated every five minutes.
Branch of llvm repository. Use branch release_34atomicc1
A fork of the main Verilator project for development work.
RISC-V Linux Port
RISC-V Proxy Kernel
QEMU with RISC-V Emulation Support
llvm runtime interpreter/translator
Scripts to create a boot.bin file for linux on Xilinx Zync
KLEE Symbolic Virtual Machine
Scripts for common operations, dependent on local device configuration
Memoizes execution of build commands
A minimalistic and high-performance SAT solver
staging repo for various binutils-gdb enhancements
Spike, a RISC-V ISA Simulator
Port of the Yocto Project to the RISC-V ISA