Connectal is a framework for software-driven hardware development.
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…s7_clockGen_pll]' in zynq xdc files (so that MMCME2_ADV instantation does not required to be in top level module)
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Connectal provides a hardware-software interface for applications split between user mode code and custom hardware in an FPGA. Portal can automatically build the software and hardware glue for a message based interface and also provides for configuring and using shared memory between applications and hardware. Communications between hardware and software are provided by a bidirectional flow of events and regions of memory shared between hardware and software. Events from software to hardware are called requests and events from hardware to software are called indications, but in fact they are symmetric.

A logical request/indication pair is referred to as a portal". An application can make use of multiple portals, which may be specified independently. A portal is specified by a BSV interface declaration, from which connectalgen generates BSV and C++ wrappers and proxies.

Connectal has a mailing list:!forum/connectal

See the documentation for more details:

Supported Platforms

Connectal supports Android on Zynq platforms, including zedboard and zc702.

Connectal supports Linux on x86 with PCIe-attached Virtex and Kintex boards (vc707, kc705).

Connectal supports bluesim as a simulated hardware platform.


  1. Install the Bluespec compiler. Connectal is known to work with 2014.07.A and 2015.05.beta1

Install the bluespec compiler. Make sure the BLUESPECDIR environment variable is set appropriately:

export BLUESPECDIR=~/bluespec/Bluespec-2014.07.A/lib
  1. Install Vivado 2015.2 or 2015.4

  2. Install Connectal

    sudo add-apt-repository -y ppa:jamey-hicks/connectal sudo apt-get update sudo apt-get -y install connectal

Building from Source

  1. Checkout out the following from github: git clone git://

If you are generating code for an FPGA, check out fpgamake: git clone git://

It appears that this requires buildcache to be checked out also: git clone git://

Add USE_BUILDCACHE=1 to your calls to make to enable it to cache, otherwise it will rerun all compilation steps.

  1. Install connectal dependences. This installs ubuntu packages used by connectal or during compilation:

    cd connectal; sudo make install-dependences

  2. If you are using an FPGA attached to your machine, install the drivers:

    make all sudo make install

Preparation for Zynq

  1. Get [](Vivado 2015.2)

  2. Download the Android Native Development Kit (NDK) from: (actual file might be: )

    Connectal uses NDK to compile code to run on Zynq platforms.

    Add the NDK to your PATH.

    curl -O `basename $URL` $URL
    tar -jxvf `basename $URL`
  3. Download and install ADB from the Android Development Tools.

    The Android Debug Bridge (adb) is packaged in platform-tools. Connectal uses adb to transfer files to and from the Zedboard over ethernet and to run commands on the Zedboard.

    User your browser to accept the conditions and download the SDK installation tarball:

    Unpack the installation tarball:

    tar -zxvf android-sdk_r22.6.2-linux.tgz

    Run the android tool to install SDK components


    Deselect all components except for "Android SDK Platform-Tools" (screenshot) and then click the "Install ... package" button to install (screenshot) and then accept the license. (screenshot)

    Add adb to your path:

  4. Create/obtain a boot.bin and SD card image for your board

Follow the instructions at

Copy the files to the SD card, eject the card from the PC, and plug it into the zedboard/zc702/zc706 and boot.

Preparation for Kintex and Virtex boards

  1. Get [](Vivado 2013.2)

  2. Install the drivers make sudo make install sudo modprobe portalmem

  3. Get fpgajtag

    git clone git:// cd fpgajtag make all && sudo make install


Generally cd to the project directory, then type

cd examples/examplename
make build.<target>
make run.<target>

where target is

Command suffix Function
bluesim compile for simulation
zedboard compile for zedboard
zybo compile for zybo
zc702 compile for zc702 board
zc706 compile for zc706 board
kc705 compile for kc705 board
vc707 compile for vc707 board
vc709 compile for vc709 board
nfsume compile for NetFPGA-SUME board

To turn on more verbosity for debugging when running make, add V=1 to command line, as

make examples/examplename.<something> V=1

or V=1 make examples/examplename.

To run the example on a machine different than the build machine, use RUNPARAM=hostname-or-addr:

make RUNPARAM=zedtest run.zedboard
make RUNPARAM= run.vc707

Bitstream Packaging

The FPGA bitstream is included in the application executable, and the
FPGA is automatically programmed when the application is run:

    cd examples/echo
    make build.vc707

We are running Android on the Zynq devices and so the application
executable is called android.exe.

Echo Example

    ## this has only been tested with the Vivado 2013.2 release
    . Xilinx/Vivado/2013.2/

    make -C examples/echo build..zedboard
    make -C examples/echo build.zc702
    make -C examples/echo build.kc705
    make -C examples/echo build.vc707

To run on a zedboard with IP address make -C examples/echo run.zedboard

Memcpy Example

    make -C examples/memcpy build.vc707