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Explanation of how fpgajtag actually forms JTAG commands #3

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gardners opened this issue Jan 7, 2020 · 6 comments
Closed

Explanation of how fpgajtag actually forms JTAG commands #3

gardners opened this issue Jan 7, 2020 · 6 comments

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@gardners
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@gardners gardners commented Jan 7, 2020

I'm trying to adapt fpgajtag to do simple boundary scans on Xilinx FPGAs, since there seems to be no good alternatives: Vivado seems to lack a simple means of connecting to an FPGA and extracting the boundary scan (or is so complicated, that I can't find out how to do it) and seems to hang on some connections, and OpenOCD seems to be able to do just about everything with JTAG, except for simple boundary scans. fpgajtag, in contrast, is beautifully simple, and never hangs the way Vivado does for me. My only challenge is to understand the code enough to be able to adapt it to my purposes.

I've been looking at read_idcode() as what should be a simple JTAG transaction that is in many ways similar to doing a boundary scan. However, I can't for the life of me figure out how it actually works to send the JTAG command. My understanding is that the JTAG command for IDCODE is 001001, but I see nothing suggestive of this in read_idcode().

What I would love, is to be able to craft something like the following (taken from https://www.fpga4fun.com/JTAG4.html) to be able to easily build JTAG transactions in the fpgajtag code base:

// go to reset state
  for(i=0; i<5; i++) JTAG_clock(TMS);

  // go to Shift-IR
  JTAG_clock(0);
  JTAG_clock(TMS);
  JTAG_clock(TMS);
  JTAG_clock(0);
  JTAG_clock(0);

  // Assuming that IR is 10 bits long,
  // that there is only one device in the chain,
  // and that SAMPLE code = 0000000101b
  JTAG_clock(1);
  JTAG_clock(0);
  JTAG_clock(1);
  JTAG_clock(0);
  JTAG_clock(0);
  JTAG_clock(0);
  JTAG_clock(0);
  JTAG_clock(0);
  JTAG_clock(0);
  JTAG_clock(0 or TMS);  // last bit needs to have TMS active, to exit shift-IR

  // we are in Exit1-IR, go to Shift-DR
  JTAG_clock(TMS);
  JTAG_clock(TMS);
  JTAG_clock(0);
  JTAG_clock(0);

  // read the boundary-scan chain bits in an array called BSB
  JTAG_read(BSB, 339);
  printf("Status of pin 99 = %d\n, BSB[3]);

Any pointers for how I would go about constructing such a sequence using the fpgajtag infrastructure?

Thanks,
Paul.

@jameyhicks

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@jameyhicks jameyhicks commented Jan 7, 2020

I'm afraid I don't understand the code either, but maybe we can get some clarification from the author.

My understanding is that this code precisely reproduces the transitions that vivado uses to program the FPGAs. So it's a bit more idiomatic.

This FTDI document might be helpful:
https://www.ftdichip.com/Support/Documents/AppNotes/AN_135_MPSSE_Basics.pdf
along with this one:
https://www.ftdichip.com/Support/Documents/AppNotes/AN_108_Command_Processor_for_MPSSE_and_MCU_Host_Bus_Emulation_Modes.pdf

@gardners

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@gardners gardners commented Jan 7, 2020

Thanks. I'll take a look.

@jankcorn

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@jankcorn jankcorn commented Jan 8, 2020

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@gardners gardners commented Jan 9, 2020

Ok. I managed to figure it out. See https://github.com/MEGA65/mega65-core/blob/unstable/src/tools/fpgajtag/boundary_scan.c for details of how I did it. My code is all GPL, so if you feel inclined to add any boundary scan stuff to fpgajtag, feel free to use it it's of any use. More info here: https://c65gs.blogspot.com/2020/01/programming-bitstream-boot-flash.html

@gardners gardners closed this Jan 9, 2020
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@jankcorn jankcorn commented Jan 10, 2020

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@gardners gardners commented Jan 10, 2020

I've been working further on it, so that it can even be used to monitor signals in realtime, like a cheap and cheery chipscope. Surprisingly can already do close to 1KHz.

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