Fix AArch64 register-offset load/store memory operand access (#2802)#2929
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lgtm. Please add the two tests and we are good to go.
…e-engine#2802) The auto-generated mapping for AArch64 register-offset addressing mode (roW/roX) load, store, and prefetch instructions incorrectly had CS_AC_INVALID for the memory operand access. For example, LDRSW with register offset (ldrsw x10, [x22, x10, lsl capstone-engine#2]) had no access type set on the memory operand, when it should be CS_AC_READ. Fix this by: - Correcting the entries directly in AArch64GenCSMappingInsn.inc - Adding an inc_patches entry so the fix is reapplied on regeneration - Adding a test case for LDRSW with register offset Affected instructions: - Loads (CS_AC_READ): LDR, LDRB, LDRH, LDRSB, LDRSH, LDRSW (roW/roX) - Stores (CS_AC_WRITE): STR, STRB, STRH, STRD (roW/roX) - Prefetch (CS_AC_READ): PRFM (roW/roX) Co-Authored-By: Claude Haiku 4.5 <noreply@anthropic.com>
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Fix issue #2802 where AArch64 load and store instructions with register-offset addressing modes were not correctly marking memory operands with READ/WRITE access type. Closes #2802