CycPUF: Cyclic Physical Unclonable Function

This repository contains resources related to cyclic and acyclic PUF generation.
Michael Dominguez & Amin Rezaei

Abstract

Physical Unclonable Functions (PUFs) leverage manufacturing process imperfections that cause propagation delay discrepancies for the signals traveling along these paths. While PUFs can be used for device authentication and chip-specific key generation, strong PUFs have been shown to be vulnerable to machine learning modeling attacks. Although there is an impression that combinational circuits must be designed without any loops, cyclic combinational circuits have been shown to increase design security against hardware intellectual property theft. In this project, we introduce feedback signals into traditional delay-based PUF designs such as arbiter PUF, ring oscillator PUF, and butterfly PUF to give them a wider range of possible output behaviors and thus an edge against modeling attacks. Based on our analysis, cyclic PUFs produce responses that can be binary, steady-state, oscillating, or pseudo-random under fixed challenges.

A. Contents

1. Paper

The published paper in which we introduce the CycPUF is contained in this folder.

2. Sample Dataset

A sample dataset has been generated and is ready for use. The layout is as follows:
- multi_bit_APUF: an acyclic APUF with 121-bit challenge and response size
- multi_bit_BPUF: an acyclic BPUF with 33-bit challenge and response size
- multi_bit_CycAPUF: a cyclic APUF with 45-bit challenge and response size, and 44 cycles
- multi_bit_CycBPUF: a cyclic BPUF with 15-bit challenge and response size, and 3 cycles
- multi_bit_CycROPUF: a cyclic ROPUF with 6-bit challenge and response size, and 6 cycles
- multi_bit_ROPUF: an acyclic ROPUF with 22-bit challenge and response size
- one_bit_APUF: an acyclic APUF with 243-bit challenge and single-bit response size
- one_bit_BPUF: an acyclic BPUF with 10-bit challenge and single-bit response size
- one_bit_CycAPUF: a cyclic APUF with 37-bit challenge, single-bit response size, and 25 cycles
- one_bit_CycBPUF: a cyclic BPUF with 51-bit challenge, single-bit response size, and 25 cycles
- two_bit_CycROPUF: a cyclic ROPUF with 14-bit challenge, two-bit response size, and 10 cycles
- two_bit_ROPUF: an acyclic ROPUF with 34-bit challenge, two-bit response size
- template_APUF: a Template APUF with 22-bit challenge, single-bit response size, and 18 cycles
- template_BPUF: a Template BPUF with 19-bit challenge, single-bit response size, and 11 cycles
- template_ROPUF: a Template ROPUF with 120-bit challenge, two-bit response size, and 80 cycles

3. Source

Our source code is contained in this folder. Here you will find two python files:
- puf_defs: a python module containing the module definitions for verilog code generation
- puf_framework: the main python file for PUF generation

B. Usage

Use the below steps to generate your own PUFs.

1. First, navigate to the sources directory.

>cd source

2. Next, run the puf_framework to begin the program.

>python puf_framework.py

3. Pick the PUF design that is desired.

Three basic delay PUF designs are currently avilable. In order, these are APUF (1), BPUF (2), and ROPUF (3). By typing a 1, 2, or 3 and hitting enter, one can select their base PUF design.
For the purpose of this tutorial, we will choose the APUF (1).

>Type 1, 2, or 3: 1

4. Choose whether the PUF will be a CycPUF or not.

Here one can set whether the PUF to be generated will contain cycles for CycPUF (2)/Template (3) behavior or if the PUF will remain an acyclic (1) PUF. By typing a 1, 2, or 3 and hitting enter, one can select whether the PUF will have cycles or not.
For the purpose of this tutorial, we will choose to create a CycPUF (2).

>Type 1, 2, or 3: 2

5. Choose whether the PUF will have a multi-bit response or not.

The size of the response vector can either take on the size of the challenge vector or may be a single-bit response.
For the purpose of this tutorial, we will choose to have a multi-bit response (y).

>*Will this PUF have a multi-bit response?*
>Type (y)es or (n)o: y

6. Choose the size of the challenge vector.

The size of the challenge vector must be an integer of at least 1.

• NOTE: The smallest challenge (and response) size that the ROPUF may have is 2 and must be an even number.
  

For the purpose of this tutorial, we will choose to have a challenge size of 45.

>Enter the size of the Challenge vector (an integer): 45

7. Choose the number of cycles.

The number of cycles for a CycPUF must be an integer of at least 1 and cannot equal the challenge vector size.

• NOTE: The minimum number of cycles that the ROPUF may have is 2 and must be an even number. A CycROPUF with a challenge of 2 is not possible.
  

For the purpose of this tutorial, we will choose to have 44 cycles.

>Enter the number of cycles (an integer): 44

8. The requested PUF has been generated.

The PUF that we specified has been generated and can now be found in the sources directory.

>You chose multi-bit response, cyclic APUF with a 45 bit Challenge vector. Your verilog files have been generated in the current directory.

C. Citation

@INPROCEEDINGS{CycPUF,
  author={Dominguez, Michael and Rezaei, Amin},
  booktitle={2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, 
  title={CycPUF: Cyclic Physical Unclonable Function}, 
  year={2024},
  volume={},
  number={},
  pages={1-6},
  doi={10.23919/DATE58400.2024.10546861}
}