REDACTOR: eFPGA Redaction for DNN Accelerator Security

This repository contains resources related to redacting DNN accelators via eFPGAs, from specification to physical design implementation.
Yazan Baddour & Amin Rezaei

ABSTRACT

With the ever-increasing utilization of artificial intelligence in everyday life as well as the preciousness of well-trained models, the security of hardware accelerators supporting DNNs has become crucial. As a promising solution to prevent hardware IP theft, eFPGA redaction has emerged by selectively concealing critical components of the design and enabling authorized users to restore functionality post-fabrication by inserting the correct bitstream. In this paper, for the first time, we delve into redacting DNN accelerators via eFPGAs from specification to physical design implementation. In particular, we investigate the selection of critical DNN modules for redaction using regular and fracturable look-up tables and perform synthesis, timing verification, and place & route on redacted DNN accelerators. Furthermore, we evaluate the overhead of employing eFPGAs into DNN accelerators in terms of power, area, and delay, finding it reasonable given the security gain.

Contents

1. Fabric_generation: contains the eFPGA architecture files, the RTL portion for redaction and config file to run fabric generation using the OpenFPGA framework
2. Logic_synthesis: contain the verilog files of the redacted module, SDC files and cmd file to run synthesis using Cadence Genus as well as the final gate-level netlist (name_synthesis_report.v)
3. Place&Route: contains an example of the final power, area and timing reports
4. security: contains python script that convert gate-level netlist (should be synthesised by Cadence Genus) into .bench files and unrolles the circuit. Also it has an example of the .bench files for our benchmarks that is fed into SAT-based attack tool like NEOS

Redaction Flow

Fabric Generation

create new task and run fabric generation as follows:

1) Navigate to Opengpga

cd OpenGPGA

2) Run Task

python3 openfpga_flow/scripts/run_fpga_task.py PEDC_STATEMACHINE --debug --show_thread_logs

Logic Synthesis

Add the SRC, SDC , cmd file and library file into a folder and source the cmd file in cadence genus as follows :
source /path/to/cmd_file/

Place & Route

Open Cadence Innovus insert the gate level netlist (created by Cadence genus) along with the SDC file , lef and library files for basic PNR flow. At the end of the flow report timing area and power

report_timing > name_of_timing_report

report_power > name_of_power_report

report_area > name_of_area_report

Run Security Analysis

Synthesize only the eFPGA fabric using basic logic gates as shown in security/fabric_synthesis after that take the gate level netlist of the benchmark with its associated bitsream from the fabric generation folder and run the python script to get the locked and oracle .bench files of the benchmark finally these bench files can be taken to SAT attack tool of your choice.

Citation

@INPROCEEDINGS{REDACTOR,
  author={Baddour, Yazan and Hedayatipour, Ava and Rezaei, Amin},
  booktitle={2025 26th International Symposium on Quality Electronic Design (ISQED)}, 
  title={REDACTOR: eFPGA Redaction for DNN Accelerator Security}, 
  year={2025},
  volume={},
  number={},
  pages={1-8},
  doi={10.1109/ISQED65160.2025.11014341}
  }