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Merge pull request #13 from wnew/master

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2 parents caf5873 + 765785c commit 6813555d379cd3c5e4d237d267e1744bb09f38f6 @wnew wnew committed Apr 11, 2012
Showing with 5,452 additions and 196 deletions.
  1. +14 −0 base_designs/roach2/__init__.py
  2. +1 −0 base_designs/roach2/clk_infrastructure/__init__.py
  3. +95 −0 base_designs/roach2/clk_infrastructure/clk_infrastructure.py
  4. +314 −0 base_designs/roach2/clk_infrastructure/clk_infrastructure.v
  5. +1 −0 base_designs/roach2/epb_infrastructure/__init__.py
  6. +44 −0 base_designs/roach2/epb_infrastructure/epb_infrastructure.py
  7. +53 −0 base_designs/roach2/epb_infrastructure/epb_infrastructure.v
  8. +1 −0 base_designs/roach2/epb_wb_bridge/__init__.py
  9. +90 −0 base_designs/roach2/epb_wb_bridge/epb_wb_bridge.py
  10. +202 −0 base_designs/roach2/epb_wb_bridge/epb_wb_bridge.v
  11. +214 −0 base_designs/roach2/r2_basedesign.py
  12. +1 −0 base_designs/roach2/reset_block/__init__.py
  13. +43 −0 base_designs/roach2/reset_block/reset_block.py
  14. +46 −0 base_designs/roach2/reset_block/reset_block.v
  15. +1 −0 base_designs/roach2/sys_block/__init__.py
  16. +61 −0 base_designs/roach2/sys_block/sys_block.py
  17. +251 −0 base_designs/roach2/sys_block/sys_block.v
  18. +23 −0 base_designs/roach2/sys_block/sys_block.vh
  19. +1 −0 base_designs/roach2/wbs_arbiter/__init__.py
  20. +21 −0 base_designs/roach2/wbs_arbiter/timeout.v
  21. +68 −0 base_designs/roach2/wbs_arbiter/wbs_arbiter.py
  22. +166 −0 base_designs/roach2/wbs_arbiter/wbs_arbiter.v
  23. +2 −0 libraries/__init__.py
  24. +2 −0 libraries/controllers/sw_reg/__init__.py
  25. +126 −0 libraries/controllers/sw_reg/sw_reg_r.py
  26. +160 −0 libraries/controllers/sw_reg/sw_reg_r.v
  27. +110 −0 libraries/controllers/sw_reg/sw_reg_r_tb.v
  28. +115 −0 libraries/controllers/sw_reg/sw_reg_wr.py
  29. +179 −0 libraries/controllers/sw_reg/sw_reg_wr.v
  30. +111 −0 libraries/controllers/sw_reg/sw_reg_wr_tb.v
  31. +4 −1 libraries/primitives/__init__.py
  32. +12 −0 libraries/primitives/all.v
  33. +1 −0 libraries/primitives/bit_shift/__init__.py
  34. +79 −0 libraries/primitives/bit_shift/bit_shift.py
  35. +86 −0 libraries/primitives/bit_shift/bit_shift.v
  36. +93 −0 libraries/primitives/bit_shift/bit_shift_tb.v
  37. +156 −0 libraries/primitives/bit_shift/test_bit_shift.py
  38. +95 −0 libraries/primitives/bram/bram_sync_dp.py
  39. +71 −0 libraries/primitives/bram/bram_sync_dp.v
  40. +118 −0 libraries/primitives/bram/bram_sync_dp_tb.v
  41. +83 −0 libraries/primitives/bram/bram_sync_sp.py
  42. +80 −0 libraries/primitives/bram/bram_sync_sp.v
  43. +92 −0 libraries/primitives/bram/bram_sync_sp_tb.v
  44. +1 −1 libraries/primitives/counter/__init__.py
  45. +62 −33 libraries/primitives/counter/counter.py
  46. +72 −65 libraries/primitives/counter/counter.v
  47. +57 −28 libraries/primitives/counter/counter_tb.v
  48. +25 −6 libraries/primitives/counter/test_counter.py
  49. +77 −0 libraries/primitives/delay/delay.py
  50. +58 −0 libraries/primitives/delay/delay.v
  51. +41 −0 libraries/primitives/delay/delay_tb.v
  52. +47 −0 libraries/primitives/delay/fifo_delay.v
  53. +61 −0 libraries/primitives/delay/sync_delay.v
  54. +95 −0 libraries/primitives/fifo/fifo.v
  55. +87 −0 libraries/primitives/fifo/fifo_tb.v
  56. +1 −0 libraries/primitives/mux/__init__.py
  57. +79 −0 libraries/primitives/mux/mux.py
  58. +58 −37 libraries/primitives/mux/mux.v
  59. +61 −25 libraries/primitives/mux/mux_tb.v
  60. +11 −0 libraries/primitives/mux/sim_test.py
  61. +144 −0 libraries/primitives/mux/test_mux.py
  62. +1 −0 libraries/primitives/slice/__init__.py
  63. +83 −0 libraries/primitives/slice/slice.py
  64. +66 −0 libraries/primitives/slice/slice.v
  65. +92 −0 libraries/primitives/slice/slice_tb.v
  66. +155 −0 libraries/primitives/slice/test_slice.py
  67. +64 −0 libraries/xilinx_infr/bufg.py
  68. +68 −0 libraries/xilinx_infr/ibufg.py
  69. +82 −0 libraries/xilinx_infr/ibufgds.py
  70. +80 −0 libraries/xilinx_infr/iobuf.py
  71. +161 −0 libraries/xilinx_infr/mmcm_base.py
  72. +77 −0 libraries/xilinx_infr/obufds.py
@@ -0,0 +1,14 @@
+#import clk_gen
+#import epb_infrastructure
+#import epb_wb_bridge_reg
+#import infrastructure
+#import knight_rider
+#import sys_block
+#import wbs_arbiter
+import clk_infrastructure.clk_infrastructure as clk_infrastructure
+import epb_infrastructure.epb_infrastructure as epb_infrastructure
+import epb_wb_bridge.epb_wb_bridge as epb_wb_bridge_reg
+import reset_block.reset_block as reset_block
+import sys_block.sys_block as sys_block
+import wbs_arbiter.wbs_arbiter as wbs_arbiter
+import counter.counter as counter
@@ -0,0 +1 @@
+import clk_infrastructure
@@ -0,0 +1,95 @@
+from myhdl import *
+
+def clk_infrastructure_wrapper(block_name,
+ sys_clk_n, sys_clk_p,
+ sys_clk, sys_clk90, sys_clk180, sys_clk270,
+ sys_clk_lock, op_power_on_rst,
+ sys_clk2x, sys_clk2x90, sys_clk2x180, sys_clk2x270,
+ #dly_clk_n, dly_clk_p,
+ #dly_clk,
+ epb_clk_in,
+ epb_clk,
+ aux_clk_n, aux_clk_p,
+ aux_clk, aux_clk90, aux_clk180, aux_clk270,
+ aux_clk2x, aux_clk2x90, aux_clk2x180, aux_clk2x270,
+ idelay_rst,
+ idelay_rdy,
+ ARCHITECTURE="BEHAVIORAL",
+ CLK_FREQ="100"
+ ):
+
+ @always(sys_clk_n.posedge)
+ def logic():
+ sys_clk_p = sys_clk_n
+
+ __verilog__ = \
+ """
+ clk_infrastructure
+ #(
+ .ARCHITECTURE ("%(ARCHITECTURE)s"),
+ .CLK_FREQ (%(CLK_FREQ)s)
+ ) clk_infrustructure_%(block_name)s (
+ .sys_clk_n (%(sys_clk_n)s),
+ .sys_clk_p (%(sys_clk_p)s),
+ .sys_clk (%(sys_clk)s),
+ .sys_clk90 (%(sys_clk90)s),
+ .sys_clk180 (%(sys_clk180)s),
+ .sys_clk270 (%(sys_clk270)s),
+ .sys_clk_lock (%(sys_clk_lock)s),
+ .op_power_on_rst (%(op_power_on_rst)s),
+ .sys_clk2x (%(sys_clk2x)s),
+ .sys_clk2x90 (%(sys_clk2x90)s),
+ .sys_clk2x180 (%(sys_clk2x180)s),
+ .sys_clk2x270 (%(sys_clk2x270)s),
+ .epb_clk_in (%(epb_clk_in)s),
+ .epb_clk (%(epb_clk)s),
+ .aux_clk_n (%(aux_clk_n)s),
+ .aux_clk_p (%(aux_clk_p)s),
+ .aux_clk (%(aux_clk)s),
+ .aux_clk90 (%(aux_clk90)s),
+ .aux_clk180 (%(aux_clk180)s),
+ .aux_clk270 (%(aux_clk270)s),
+ .aux_clk2x (%(aux_clk2x)s),
+ .aux_clk2x90 (%(aux_clk2x90)s),
+ .aux_clk2x180 (%(aux_clk2x180)s),
+ .aux_clk2x270 (%(aux_clk2x270)s),
+ .idelay_rst (%(idelay_rst)s),
+ .idelay_rdy (%(idelay_rdy)s)
+ );
+ """
+
+ sys_clk.driven = "wire"
+ sys_clk90.driven = "wire"
+ sys_clk180.driven = "wire"
+ sys_clk270.driven = "wire"
+ sys_clk_lock.driven = "wire"
+ op_power_on_rst.driven = "wire"
+ sys_clk2x.driven = "wire"
+ sys_clk2x90.driven = "wire"
+ sys_clk2x180.driven = "wire"
+ sys_clk2x270.driven = "wire"
+ epb_clk.driven = "wire"
+
+ aux_clk.driven = "wire"
+ aux_clk90.driven = "wire"
+ aux_clk180.driven = "wire"
+ aux_clk270.driven = "wire"
+ aux_clk2x.driven = "wire"
+ aux_clk2x90.driven = "wire"
+ aux_clk2x180.driven = "wire"
+ aux_clk2x270.driven = "wire"
+
+ #idelay_rdy.driven = "wire"
+
+ return logic
+
+def convert():
+
+ sys_clk_n, sys_clk_p, sys_clk, sys_clk90, sys_clk180, sys_clk270, sys_clk_lock, op_power_on_rst, sys_clk2x, sys_clk2x90, sys_clk2x180, sys_clk2x270, epb_clk_in, epb_clk, aux_clk_n, aux_clk_p, aux_clk, aux_clk90, aux_clk180, aux_clk270, aux_clk2x, aux_clk2x90, aux_clk2x180, aux_clk2x270, idelay_rst, idelay_rdy = [Signal(bool(0)) for i in range(26)]
+
+
+ toVerilog(clk_infrastructure_wrapper, "1", sys_clk_n, sys_clk_p, sys_clk, sys_clk90, sys_clk180, sys_clk270, sys_clk_lock, op_power_on_rst, sys_clk2x, sys_clk2x90, sys_clk2x180, sys_clk2x270, epb_clk_in, epb_clk, aux_clk_n, aux_clk_p, aux_clk, aux_clk90, aux_clk180, aux_clk270, aux_clk2x, aux_clk2x90, aux_clk2x180, aux_clk2x270, idelay_rst, idelay_rdy, ARCHITECTURE="VIRTEX6")
+
+if __name__ == "__main__":
+ convert()
+
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