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  • 2 commits
  • 4 files changed
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  • 1 contributor
Commits on Mar 18, 2012
Mark Wagner Adding version 102 of the ASIAA ADC model file and bof file.
This version 102 of the asiaa 5gsps adc adds a conversion
from the adc output of fixed 8_0 to signed 8_7 for proper
input into the pfb_fir.  The fft shift on every other stage.

This bof (v01_aa_ri_8r4t11f_ver102_2012_Mar_17_1554.bof)
clocks the FPGA at 150MHz.
Mark Wagner Adding a switching signal generator logic mode 01 test model. 5535810
BIN  bofs/v01_aa_ri_8r4t11f_ver102_2012_Mar_17_1554.bof
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79,667 mdls/mode01/v01_aa_ri_8r4t11f_ver101.mdl
40,541 additions, 39,126 deletions not shown
758,934 mdls/mode01/v01_aa_ri_8r4t11f_ver102.mdl
758,934 additions, 0 deletions not shown
33,332 mdls/ssg/v01_ssg_only.mdl
33,332 additions, 0 deletions not shown

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