A C++ Hardware Description Language and Toolchain
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examples
test
.gitignore
BUGS
CHDL
COPYING
Makefile
TODO
VERSION
adder.h
analysis.cpp
analysis.h
assert.cpp Fix -Wunused. Dec 4, 2014
assert.h
bus.h
bvec-basic-op.h
bvec-basic.h
bvec.h
cassign.h
cdomain.cpp
cdomain.h
chdl.h
chdl_present.cpp Added presence detection function for autotools, etc. Jun 5, 2014
console.cpp
console.h
divider.h
egress.h
enc.h
gateops.h
gates.cpp
gates.h
gatesimpl.cpp
gatesimpl.h
hierarchy.cpp
hierarchy.h
ingress.h
input.cpp
input.h
latch.h
lit.cpp Fix "no return" warning issued by braindead compilers. Jun 2, 2015
lit.h
litimpl.h
llmem.h
memory.cpp
memory.h Initial syncmem outputs now 0. Aug 18, 2015
mult.h Fixed non-static function in header. Oct 3, 2013
mux.h Either GCC 3.7 or the standard is fickle about constants. Jan 2, 2017
netlist.cpp Fix some errors in Verilog output. Sep 27, 2016
netlist.h
node.h
nodeimpl.cpp
nodeimpl.h
opt.cpp
opt.h
order.cpp
printable.cpp
printable.h
reg.h
regimpl.cpp
regimpl.h
reset.cpp
reset.h
shifter.h
sim.cpp Remove unused parameter, but save potentially descriptive name. Dec 4, 2014
sim.h
submodule.cpp
submodule.h
tap.cpp New netlist writing framework to unify verilog/netl generation. Dec 27, 2016
tap.h
techmap.cpp
techmap.h
tickable.cpp
tickable.h
trisimpl.cpp New netlist writing framework to unify verilog/netl generation. Dec 27, 2016
trisimpl.h New netlist writing framework to unify verilog/netl generation. Dec 27, 2016
tristate.cpp
tristate.h
ttable.cpp
ttable.h
vis.cpp
vis.h