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Commits on Aug 18, 2017
  1. Update README.md

    cederom committed Aug 18, 2017
    Added info on pyOCD for DAPLink.
Commits on Aug 15, 2017
  1. Update README.md

    cederom committed Aug 15, 2017
    Invitation to try out the ARM mbed DAPLink project :-)
  2. Merge pull request #16 from andrewparlane/master

    cederom committed Aug 15, 2017
    MEMAP: Fixing bug with auto TAR increment (Issue #15).
Commits on Jun 23, 2017
  1. MEMAP: Fixing bug with auto TAR increment (Issue #15).

    andrewparlane committed Jun 23, 2017
    The TAR register can be auto incremented after every write or read from
    DRW. However this is only guaranteed to work for the lowest 10 bits of
    TAR. Above that it's implementation defined.
    
    On some targets it's just the 10 bits, meaning that something unknown
    <implementation defined> happens if you go over a !KB boundary.
    
    The previous code dealt with this, by rewriting the TAR register every
    1KB. However that doesn't work if you don't start your writes 1KB
    aligned.
    
    For example, if you write 1KB starting at address 0x200, the first 512
    bytes write OK, after that it's implementation defined. On my target it
    wrapped to 0 and wrote the last 512 bytes there.
    
    My fix re-writes the TAR register whenever you hit a 1KB boundary,
    regardless of start address.
Commits on Jun 15, 2017
  1. Updated README with Travis integration.

    cederom committed Jun 15, 2017
    Travis CI integration by Stephen Groat of Qualcomm. Thank you! :-)
  2. Merge pull request #5 from stephengroat/master

    cederom committed Jun 15, 2017
    Simple travis compile tests
Commits on Apr 26, 2017
Commits on Feb 20, 2017
  1. Update README.md

    cederom committed Feb 20, 2017
    added information on new project libswd.com domain.
Commits on Feb 15, 2017
  1. Merge pull request #4 from andrewparlane/master

    cederom committed Feb 15, 2017
    Various fixes by @andrewparlane thank you! :-)
  2. Adding support for Cortex-M0 r0p0

    Andrew Parlane
    Andrew Parlane committed Feb 15, 2017
Commits on Jan 28, 2017
  1. Merge pull request #3 from orthographic-pedant/spell_check/achievements

    cederom committed Jan 28, 2017
    Fixed typographical error, changed achievments to achievements in README.
  2. Merge pull request #2 from orthographic-pedant/spell_check/achievement

    cederom committed Jan 28, 2017
    Fixed typographical error, changed achievment to achievement in README.
Commits on Dec 2, 2016
  1. Tidyup: Fixed compiler.

    andrewparlane committed Dec 2, 2016
    There were various compiler warnings when using gcc v6.1.0 for x86_64.
Commits on Nov 22, 2016
  1. DEBUG: Don't re-read the CPUID register for every target.

    andrewparlane committed Nov 22, 2016
    Previously we iterated through the list of CPUIDs, read the
    specified address and then compared it to the default value.
    
    However all the addresses were the same. It seems silly to read the same
    register N times.
    
    I've changed this to use a define of the address, reading once, and
    comparing to each entry in the CPUID list.
    
    This is much faster especially if the SWD baudrate is slow or there are
    lots of supported CPUIDs.
    
    If in the future we find a chip that has it's CPUID in a different
    location then we will need to change this code again. Maybe to have a
    list of addresses, and for each address a list of pairs of name and
    default value.
  2. DEBUG: Added a define for number of supported CPUIDs.

    andrewparlane committed Nov 22, 2016
    We then use this to iterate over the array, rather than looking for a
    NULL terminator.
  3. WHITESPACE: Replaced tabs with spaces.

    andrewparlane committed Nov 22, 2016
    This matches the rest of the project.
  4. TARGET: Changed the CPUID array terminator to be an actual entry.

    andrewparlane committed Nov 2, 2016
    Previously the terminator was 0, however my compiler didn't support
    that.
    
    This array is only used in one place, and it is looped over until the address field is 0. So my change of just setting the address field to 0 for the terminator entry, works fine.
  5. MEMAP: Fixed byte-laning issues for 8 and 16 bit reads / writes.

    andrewparlane committed Nov 2, 2016
    This builds on top of my earlier commit: "MEMAP: Add support for 16 bit
    non-packed writes."
    
    That previous commit only fixed 16 bit writes. This commit fixes both 8
    and 16 bit reads and writes.
  6. MEMAP: Checking for alignment issues when doing a 16bit or 32bit read…

    andrewparlane committed Nov 2, 2016
    … or write.
    
    The ARM debug interface v5 states that accessing an address that is not
    aligned to the access size is "implementation defined".
    
    I think it's better to not allow this, as otherwise we would have to
    program in support for each implementation method, and work out which
    implementations support which method.
Commits on Sep 30, 2015
Commits on Apr 15, 2015
  1. Updated README.md.

    cederom committed Apr 15, 2015
  2. Merge pull request #1 from andrew-parlane-carallon/master

    cederom committed Apr 15, 2015
    LibSWD changes by Andrew Parlane of Carallon.
Commits on Apr 14, 2015
  1. Revert "CMDQ: Set the last entry in the linked list's next ptr to NULL."

    AndrewP
    AndrewP committed Apr 14, 2015
    This reverts commit f8ee85f.
    
    This commit isn't needed, as calloc() zeros the memory for you.
Commits on Apr 13, 2015
  1. Fixed readline autocompletion portability issue.

    cederom committed Apr 13, 2015
    Fixed build error on Mac OSX caused by GNU extenstions.
Commits on Apr 10, 2015
  1. CMDQ: Set the last entry in the linked list's next ptr to NULL.

    AndrewP
    AndrewP committed Apr 10, 2015
    If the last entry's next ptr is not NULL then we will jump off to random
    addresses when trying to find the end of the list.
  2. MEMAP: Add support for 16 bit non-packed writes.

    AndrewP
    AndrewP committed Apr 10, 2015
    When writing to an address % 4 == 2 (ie. not 4 byte aligned), the 16 bits
    of data to write must be in the top 16 bits of the 32 bit SWD transfer.
    
    See Corsight SOC TRM r1p0 for details.
    
    Note: A similar change is needed for reads, and 8 bit reads / writes.
  3. DAP: Only write to the ABORT register after doing the read.

    AndrewP
    AndrewP committed Apr 10, 2015
    We were seeing reads failing before this change. Additionally scoping the
    SWD bus whilst using a Segger SWD debugger had aborts after the read and
    not before.
  4. TARGET: Added support Cortex M0 based chips.

    AndrewP
    AndrewP committed Apr 10, 2015
Commits on Sep 27, 2014
  1. Various type related fixes.

    cederom committed Sep 27, 2014
    Fixed as suggested by CLANG warnings.