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A collection of HDL cores written in MyHDL.
Python Verilog VHDL Shell
Latest commit e09f036 @cfelton Update
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docs docs and spelling
mn completed the start (basic) avalon memmap interface
scripts/ci ci now use the latest myhdl
test fixed args to test
.gitignore sdram stub, couple other new modules
.travis.yml Update .travis.yml
COPYING initial commit
COPYING.LESSER initial commit Update adding avalon bus object

This project has been merged into rhea.
This project will not be updated or developed further.

The repository will be deleted in the near future.

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