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amdgpu_plugin.c
1831 lines (1522 loc) · 49 KB
/
amdgpu_plugin.c
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#include <errno.h>
#include <fcntl.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include <linux/limits.h>
#include <sys/ioctl.h>
#include <sys/stat.h>
#include <sys/sysmacros.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <stdint.h>
#include <pthread.h>
#include <semaphore.h>
#include <xf86drm.h>
#include <libdrm/amdgpu.h>
#include <libdrm/amdgpu_drm.h>
#include "criu-plugin.h"
#include "plugin.h"
#include "criu-amdgpu.pb-c.h"
#include "kfd_ioctl.h"
#include "xmalloc.h"
#include "criu-log.h"
#include "files.h"
#include "common/list.h"
#include "amdgpu_plugin_drm.h"
#include "amdgpu_plugin_util.h"
#include "amdgpu_plugin_topology.h"
#include "img-streamer.h"
#include "image.h"
#include "cr_options.h"
struct vma_metadata {
struct list_head list;
uint64_t old_pgoff;
uint64_t new_pgoff;
uint64_t vma_entry;
uint32_t new_minor;
int fd;
};
/************************************ Global Variables ********************************************/
/**
* FD of KFD device used to checkpoint. On a multi-process
* tree the order of checkpointing goes from parent to child
* and so on - so saving the FD will not be overwritten
*/
static int kfd_checkpoint_fd;
static LIST_HEAD(update_vma_info_list);
size_t kfd_max_buffer_size;
/**************************************************************************************************/
/* Call ioctl, restarting if it is interrupted */
int kmtIoctl(int fd, unsigned long request, void *arg)
{
int ret, max_retries = 200;
do {
ret = ioctl(fd, request, arg);
} while (ret == -1 && max_retries-- > 0 && (errno == EINTR || errno == EAGAIN));
if (ret == -1 && errno == EBADF)
/* In case pthread_atfork didn't catch it, this will
* make any subsequent hsaKmt calls fail in CHECK_KFD_OPEN.
*/
pr_perror("KFD file descriptor not valid in this process");
return ret;
}
static void free_e(CriuKfd *e)
{
for (int i = 0; i < e->n_bo_entries; i++) {
if (e->bo_entries[i])
xfree(e->bo_entries[i]);
}
for (int i = 0; i < e->n_device_entries; i++) {
if (e->device_entries[i]) {
for (int j = 0; j < e->device_entries[i]->n_iolinks; j++)
xfree(e->device_entries[i]->iolinks[j]);
xfree(e->device_entries[i]);
}
}
xfree(e);
}
static int allocate_device_entries(CriuKfd *e, int num_of_devices)
{
e->device_entries = xmalloc(sizeof(KfdDeviceEntry *) * num_of_devices);
if (!e->device_entries) {
pr_err("Failed to allocate device_entries\n");
return -ENOMEM;
}
for (int i = 0; i < num_of_devices; i++) {
KfdDeviceEntry *entry = xzalloc(sizeof(*entry));
if (!entry) {
pr_err("Failed to allocate entry\n");
return -ENOMEM;
}
kfd_device_entry__init(entry);
e->device_entries[i] = entry;
e->n_device_entries++;
}
return 0;
}
static int allocate_bo_entries(CriuKfd *e, int num_bos, struct kfd_criu_bo_bucket *bo_bucket_ptr)
{
e->bo_entries = xmalloc(sizeof(KfdBoEntry *) * num_bos);
if (!e->bo_entries) {
pr_err("Failed to allocate bo_info\n");
return -ENOMEM;
}
for (int i = 0; i < num_bos; i++) {
KfdBoEntry *entry = xzalloc(sizeof(*entry));
if (!entry) {
pr_err("Failed to allocate botest\n");
return -ENOMEM;
}
kfd_bo_entry__init(entry);
e->bo_entries[i] = entry;
e->n_bo_entries++;
}
return 0;
}
int topology_to_devinfo(struct tp_system *sys, struct device_maps *maps, KfdDeviceEntry **deviceEntries)
{
uint32_t devinfo_index = 0;
struct tp_node *node;
list_for_each_entry(node, &sys->nodes, listm_system) {
KfdDeviceEntry *devinfo = deviceEntries[devinfo_index++];
devinfo->node_id = node->id;
if (NODE_IS_GPU(node)) {
devinfo->gpu_id = maps_get_dest_gpu(maps, node->gpu_id);
if (!devinfo->gpu_id)
return -EINVAL;
devinfo->simd_count = node->simd_count;
devinfo->mem_banks_count = node->mem_banks_count;
devinfo->caches_count = node->caches_count;
devinfo->io_links_count = node->io_links_count;
devinfo->max_waves_per_simd = node->max_waves_per_simd;
devinfo->lds_size_in_kb = node->lds_size_in_kb;
devinfo->num_gws = node->num_gws;
devinfo->wave_front_size = node->wave_front_size;
devinfo->array_count = node->array_count;
devinfo->simd_arrays_per_engine = node->simd_arrays_per_engine;
devinfo->cu_per_simd_array = node->cu_per_simd_array;
devinfo->simd_per_cu = node->simd_per_cu;
devinfo->max_slots_scratch_cu = node->max_slots_scratch_cu;
devinfo->vendor_id = node->vendor_id;
devinfo->device_id = node->device_id;
devinfo->domain = node->domain;
devinfo->drm_render_minor = node->drm_render_minor;
devinfo->hive_id = node->hive_id;
devinfo->num_sdma_engines = node->num_sdma_engines;
devinfo->num_sdma_xgmi_engines = node->num_sdma_xgmi_engines;
devinfo->num_sdma_queues_per_engine = node->num_sdma_queues_per_engine;
devinfo->num_cp_queues = node->num_cp_queues;
devinfo->fw_version = node->fw_version;
devinfo->capability = node->capability;
devinfo->sdma_fw_version = node->sdma_fw_version;
devinfo->vram_public = node->vram_public;
devinfo->vram_size = node->vram_size;
} else {
devinfo->cpu_cores_count = node->cpu_cores_count;
}
if (node->num_valid_iolinks) {
struct tp_iolink *iolink;
uint32_t iolink_index = 0;
devinfo->iolinks = xmalloc(sizeof(DevIolink *) * node->num_valid_iolinks);
if (!devinfo->iolinks)
return -ENOMEM;
list_for_each_entry(iolink, &node->iolinks, listm) {
if (!iolink->valid)
continue;
devinfo->iolinks[iolink_index] = xmalloc(sizeof(DevIolink));
if (!devinfo->iolinks[iolink_index])
return -ENOMEM;
dev_iolink__init(devinfo->iolinks[iolink_index]);
devinfo->iolinks[iolink_index]->type = iolink->type;
devinfo->iolinks[iolink_index]->node_to_id = iolink->node_to_id;
iolink_index++;
}
devinfo->n_iolinks = iolink_index;
}
}
return 0;
}
int devinfo_to_topology(KfdDeviceEntry *devinfos[], uint32_t num_devices, struct tp_system *sys)
{
for (int i = 0; i < num_devices; i++) {
struct tp_node *node;
KfdDeviceEntry *devinfo = devinfos[i];
node = sys_add_node(sys, devinfo->node_id, devinfo->gpu_id);
if (!node)
return -ENOMEM;
if (devinfo->cpu_cores_count) {
node->cpu_cores_count = devinfo->cpu_cores_count;
} else {
node->simd_count = devinfo->simd_count;
node->mem_banks_count = devinfo->mem_banks_count;
node->caches_count = devinfo->caches_count;
node->io_links_count = devinfo->io_links_count;
node->max_waves_per_simd = devinfo->max_waves_per_simd;
node->lds_size_in_kb = devinfo->lds_size_in_kb;
node->num_gws = devinfo->num_gws;
node->wave_front_size = devinfo->wave_front_size;
node->array_count = devinfo->array_count;
node->simd_arrays_per_engine = devinfo->simd_arrays_per_engine;
node->cu_per_simd_array = devinfo->cu_per_simd_array;
node->simd_per_cu = devinfo->simd_per_cu;
node->max_slots_scratch_cu = devinfo->max_slots_scratch_cu;
node->vendor_id = devinfo->vendor_id;
node->device_id = devinfo->device_id;
node->domain = devinfo->domain;
node->drm_render_minor = devinfo->drm_render_minor;
node->hive_id = devinfo->hive_id;
node->num_sdma_engines = devinfo->num_sdma_engines;
node->num_sdma_xgmi_engines = devinfo->num_sdma_xgmi_engines;
node->num_sdma_queues_per_engine = devinfo->num_sdma_queues_per_engine;
node->num_cp_queues = devinfo->num_cp_queues;
node->fw_version = devinfo->fw_version;
node->capability = devinfo->capability;
node->sdma_fw_version = devinfo->sdma_fw_version;
node->vram_public = devinfo->vram_public;
node->vram_size = devinfo->vram_size;
}
for (int j = 0; j < devinfo->n_iolinks; j++) {
struct tp_iolink *iolink;
DevIolink *devlink = (devinfo->iolinks[j]);
iolink = node_add_iolink(node, devlink->type, devlink->node_to_id);
if (!iolink)
return -ENOMEM;
}
}
return 0;
}
void getenv_bool(const char *var, bool *value)
{
char *value_str = getenv(var);
if (value_str) {
if (!strcmp(value_str, "0") || !strcasecmp(value_str, "NO"))
*value = false;
else if (!strcmp(value_str, "1") || !strcasecmp(value_str, "YES"))
*value = true;
else
pr_err("Ignoring invalid value for %s=%s, expecting (YES/NO)\n", var, value_str);
}
pr_info("param: %s:%s\n", var, *value ? "Y" : "N");
}
void getenv_size_t(const char *var, size_t *value)
{
char *value_str = getenv(var);
char *endp = value_str;
int sh = 0;
size_t size;
pr_info("Value str: %s\n", value_str);
if (value_str) {
size = (size_t)strtoul(value_str, &endp, 0);
if (errno || value_str == endp) {
pr_err("Ignoring invalid value for %s=%s, expecting a positive integer\n", var, value_str);
return;
}
switch (*endp) {
case 'k':
case 'K':
sh = 10;
break;
case 'M':
sh = 20;
break;
case 'G':
sh = 30;
break;
case '\0':
sh = 0;
break;
default:
pr_err("Ignoring invalid size suffix for %s=%s, expecting 'K'/k', 'M', or 'G'\n", var, value_str);
return;
}
if (SIZE_MAX >> sh < size) {
pr_err("Ignoring invalid value for %s=%s, exceeds SIZE_MAX\n", var, value_str);
return;
}
*value = size << sh;
}
pr_info("param: %s:0x%lx\n", var, *value);
}
int amdgpu_plugin_init(int stage)
{
pr_info("initialized: %s (AMDGPU/KFD)\n", CR_PLUGIN_DESC.name);
topology_init(&src_topology);
topology_init(&dest_topology);
maps_init(&checkpoint_maps);
maps_init(&restore_maps);
if (stage == CR_PLUGIN_STAGE__RESTORE) {
/* Default Values */
kfd_fw_version_check = true;
kfd_sdma_fw_version_check = true;
kfd_caches_count_check = true;
kfd_num_gws_check = true;
kfd_vram_size_check = true;
kfd_numa_check = true;
kfd_capability_check = true;
getenv_bool("KFD_FW_VER_CHECK", &kfd_fw_version_check);
getenv_bool("KFD_SDMA_FW_VER_CHECK", &kfd_sdma_fw_version_check);
getenv_bool("KFD_CACHES_COUNT_CHECK", &kfd_caches_count_check);
getenv_bool("KFD_NUM_GWS_CHECK", &kfd_num_gws_check);
getenv_bool("KFD_VRAM_SIZE_CHECK", &kfd_vram_size_check);
getenv_bool("KFD_NUMA_CHECK", &kfd_numa_check);
getenv_bool("KFD_CAPABILITY_CHECK", &kfd_capability_check);
}
kfd_max_buffer_size = 0;
getenv_size_t("KFD_MAX_BUFFER_SIZE", &kfd_max_buffer_size);
return 0;
}
void amdgpu_plugin_fini(int stage, int ret)
{
pr_info("finished %s (AMDGPU/KFD)\n", CR_PLUGIN_DESC.name);
if (stage == CR_PLUGIN_STAGE__RESTORE)
sys_close_drm_render_devices(&dest_topology);
maps_free(&checkpoint_maps);
maps_free(&restore_maps);
topology_free(&src_topology);
topology_free(&dest_topology);
}
CR_PLUGIN_REGISTER("amdgpu_plugin", amdgpu_plugin_init, amdgpu_plugin_fini)
struct thread_data {
pthread_t thread;
uint64_t num_of_bos;
uint32_t gpu_id;
pid_t pid;
struct kfd_criu_bo_bucket *bo_buckets;
KfdBoEntry **bo_entries;
int drm_fd;
int ret;
int id; /* File ID used by CRIU to identify KFD image for this process */
};
int amdgpu_plugin_handle_device_vma(int fd, const struct stat *st_buf)
{
struct stat st_kfd;
int ret = 0;
pr_debug("Enter %s\n", __func__);
ret = stat(AMDGPU_KFD_DEVICE, &st_kfd);
if (ret == -1) {
pr_perror("stat error for /dev/kfd");
return ret;
}
/* If input device is KFD return device as supported */
if (major(st_buf->st_rdev) == major(st_kfd.st_rdev)) {
pr_debug("Known non-regular mapping, kfd-renderD%d -> OK\n", minor(st_buf->st_rdev));
return 0;
}
/* Determine if input is a DRM device and therefore is supported */
ret = amdgpu_plugin_drm_handle_device_vma(fd, st_buf);
if (ret)
pr_perror("%s(), Can't handle VMAs of input device", __func__);
return ret;
}
CR_PLUGIN_REGISTER_HOOK(CR_PLUGIN_HOOK__HANDLE_DEVICE_VMA, amdgpu_plugin_handle_device_vma)
int alloc_and_map(amdgpu_device_handle h_dev, uint64_t size, uint32_t domain, amdgpu_bo_handle *ph_bo,
amdgpu_va_handle *ph_va, uint64_t *p_gpu_addr, void **p_cpu_addr)
{
struct amdgpu_bo_alloc_request alloc_req;
amdgpu_bo_handle h_bo;
amdgpu_va_handle h_va;
uint64_t gpu_addr;
void *cpu_addr;
int err;
memset(&alloc_req, 0, sizeof(alloc_req));
alloc_req.alloc_size = size;
alloc_req.phys_alignment = 0x1000;
alloc_req.preferred_heap = domain;
alloc_req.flags = 0;
err = amdgpu_bo_alloc(h_dev, &alloc_req, &h_bo);
if (err) {
pr_perror("failed to alloc BO");
return err;
}
err = amdgpu_va_range_alloc(h_dev, amdgpu_gpu_va_range_general, size, 0x1000, 0, &gpu_addr, &h_va, 0);
if (err) {
pr_perror("failed to alloc VA");
goto err_va;
}
err = amdgpu_bo_va_op(h_bo, 0, size, gpu_addr, 0, AMDGPU_VA_OP_MAP);
if (err) {
pr_perror("failed to GPU map BO");
goto err_gpu_map;
}
if (p_cpu_addr) {
err = amdgpu_bo_cpu_map(h_bo, &cpu_addr);
if (err) {
pr_perror("failed to CPU map BO");
goto err_cpu_map;
}
*p_cpu_addr = cpu_addr;
}
*ph_bo = h_bo;
*ph_va = h_va;
*p_gpu_addr = gpu_addr;
return 0;
err_cpu_map:
amdgpu_bo_va_op(h_bo, 0, size, gpu_addr, 0, AMDGPU_VA_OP_UNMAP);
err_gpu_map:
amdgpu_va_range_free(h_va);
err_va:
amdgpu_bo_free(h_bo);
return err;
}
void free_and_unmap(uint64_t size, amdgpu_bo_handle h_bo, amdgpu_va_handle h_va, uint64_t gpu_addr, void *cpu_addr)
{
if (cpu_addr)
amdgpu_bo_cpu_unmap(h_bo);
amdgpu_bo_va_op(h_bo, 0, size, gpu_addr, 0, AMDGPU_VA_OP_UNMAP);
amdgpu_va_range_free(h_va);
amdgpu_bo_free(h_bo);
}
static int sdma_copy_bo(struct kfd_criu_bo_bucket bo_bucket, FILE *storage_fp,
void *buffer, size_t buffer_size, amdgpu_device_handle h_dev,
uint64_t max_copy_size, enum sdma_op_type type)
{
uint64_t size, src_bo_size, dst_bo_size, buffer_bo_size, bytes_remain, buffer_space_remain;
uint64_t gpu_addr_src, gpu_addr_dst, gpu_addr_ib, copy_src, copy_dst, copy_size;
amdgpu_va_handle h_va_src, h_va_dst, h_va_ib;
amdgpu_bo_handle h_bo_src, h_bo_dst, h_bo_ib;
struct amdgpu_bo_import_result res = { 0 };
struct amdgpu_cs_ib_info ib_info;
amdgpu_bo_list_handle h_bo_list;
struct amdgpu_cs_request cs_req;
amdgpu_bo_handle resources[3];
struct amdgpu_cs_fence fence;
uint32_t expired;
amdgpu_context_handle h_ctx;
uint32_t *ib = NULL;
int j, err, shared_fd, packets_per_buffer;
shared_fd = bo_bucket.dmabuf_fd;
size = bo_bucket.size;
buffer_bo_size = min(size, buffer_size);
packets_per_buffer = ((buffer_bo_size - 1) / max_copy_size) + 1;
src_bo_size = (type == SDMA_OP_VRAM_WRITE) ? buffer_bo_size : size;
dst_bo_size = (type == SDMA_OP_VRAM_READ) ? buffer_bo_size : size;
plugin_log_msg("Enter %s\n", __func__);
/* prepare src buffer */
switch (type) {
case SDMA_OP_VRAM_WRITE:
err = amdgpu_create_bo_from_user_mem(h_dev, buffer, src_bo_size, &h_bo_src);
if (err) {
pr_perror("failed to create userptr for sdma");
return -EFAULT;
}
break;
case SDMA_OP_VRAM_READ:
err = amdgpu_bo_import(h_dev, amdgpu_bo_handle_type_dma_buf_fd, shared_fd, &res);
if (err) {
pr_perror("failed to import dmabuf handle from libdrm");
return -EFAULT;
}
h_bo_src = res.buf_handle;
break;
default:
pr_perror("Invalid sdma operation");
return -EINVAL;
}
err = amdgpu_va_range_alloc(h_dev, amdgpu_gpu_va_range_general, src_bo_size, 0x1000, 0, &gpu_addr_src,
&h_va_src, 0);
if (err) {
pr_perror("failed to alloc VA for src bo");
goto err_src_va;
}
err = amdgpu_bo_va_op(h_bo_src, 0, src_bo_size, gpu_addr_src, 0, AMDGPU_VA_OP_MAP);
if (err) {
pr_perror("failed to GPU map the src BO");
goto err_src_bo_map;
}
plugin_log_msg("Source BO: GPU VA: %lx, size: %lx\n", gpu_addr_src, src_bo_size);
/* prepare dest buffer */
switch (type) {
case SDMA_OP_VRAM_WRITE:
err = amdgpu_bo_import(h_dev, amdgpu_bo_handle_type_dma_buf_fd, shared_fd, &res);
if (err) {
pr_perror("failed to import dmabuf handle from libdrm");
goto err_dst_bo_prep;
}
h_bo_dst = res.buf_handle;
break;
case SDMA_OP_VRAM_READ:
err = amdgpu_create_bo_from_user_mem(h_dev, buffer, dst_bo_size, &h_bo_dst);
if (err) {
pr_perror("failed to create userptr for sdma");
goto err_dst_bo_prep;
}
break;
default:
pr_perror("Invalid sdma operation");
goto err_dst_bo_prep;
}
err = amdgpu_va_range_alloc(h_dev, amdgpu_gpu_va_range_general, dst_bo_size, 0x1000, 0, &gpu_addr_dst,
&h_va_dst, 0);
if (err) {
pr_perror("failed to alloc VA for dest bo");
goto err_dst_va;
}
err = amdgpu_bo_va_op(h_bo_dst, 0, dst_bo_size, gpu_addr_dst, 0, AMDGPU_VA_OP_MAP);
if (err) {
pr_perror("failed to GPU map the dest BO");
goto err_dst_bo_map;
}
plugin_log_msg("Dest BO: GPU VA: %lx, size: %lx\n", gpu_addr_dst, dst_bo_size);
/* prepare ring buffer/indirect buffer for command submission
* each copy packet is 7 dwords so we need to alloc 28x size for ib
*/
err = alloc_and_map(h_dev, packets_per_buffer * 28, AMDGPU_GEM_DOMAIN_GTT, &h_bo_ib, &h_va_ib, &gpu_addr_ib,
(void **)&ib);
if (err) {
pr_perror("failed to allocate and map ib/rb");
goto err_ib_gpu_alloc;
}
plugin_log_msg("Indirect BO: GPU VA: %lx, size: %lx\n", gpu_addr_ib, packets_per_buffer * 28);
resources[0] = h_bo_src;
resources[1] = h_bo_dst;
resources[2] = h_bo_ib;
err = amdgpu_bo_list_create(h_dev, 3, resources, NULL, &h_bo_list);
if (err) {
pr_perror("failed to create BO resources list");
goto err_bo_list;
}
bytes_remain = size;
if (type == SDMA_OP_VRAM_WRITE)
copy_dst = gpu_addr_dst;
else
copy_src = gpu_addr_src;
while (bytes_remain > 0) {
memset(&cs_req, 0, sizeof(cs_req));
memset(&fence, 0, sizeof(fence));
memset(ib, 0, packets_per_buffer * 28);
if (type == SDMA_OP_VRAM_WRITE) {
err = read_fp(storage_fp, buffer, min(bytes_remain, buffer_bo_size));
if (err) {
pr_perror("failed to read from storage");
goto err_bo_list;
}
}
buffer_space_remain = buffer_bo_size;
if (type == SDMA_OP_VRAM_WRITE)
copy_src = gpu_addr_src;
else
copy_dst = gpu_addr_dst;
j = 0;
while (bytes_remain > 0 && buffer_space_remain > 0) {
copy_size = min(min(bytes_remain, max_copy_size), buffer_space_remain);
ib[j++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
ib[j++] = copy_size;
ib[j++] = 0;
ib[j++] = 0xffffffff & copy_src;
ib[j++] = (0xffffffff00000000 & copy_src) >> 32;
ib[j++] = 0xffffffff & copy_dst;
ib[j++] = (0xffffffff00000000 & copy_dst) >> 32;
copy_src += copy_size;
copy_dst += copy_size;
bytes_remain -= copy_size;
buffer_space_remain -= copy_size;
}
/* pad the IB to the required number of dw with SDMA_NOP */
while (j & 7)
ib[j++] = SDMA_NOP;
ib_info.ib_mc_address = gpu_addr_ib;
ib_info.size = j;
cs_req.ip_type = AMDGPU_HW_IP_DMA;
/* possible future optimization: may use other rings, info available in
* amdgpu_query_hw_ip_info()
*/
cs_req.ring = 0;
cs_req.number_of_ibs = 1;
cs_req.ibs = &ib_info;
cs_req.resources = h_bo_list;
cs_req.fence_info.handle = NULL;
err = amdgpu_cs_ctx_create(h_dev, &h_ctx);
if (err) {
pr_perror("failed to create context for SDMA command submission");
goto err_ctx;
}
err = amdgpu_cs_submit(h_ctx, 0, &cs_req, 1);
if (err) {
pr_perror("failed to submit command for SDMA IB");
goto err_cs_submit_ib;
}
fence.context = h_ctx;
fence.ip_type = AMDGPU_HW_IP_DMA;
fence.ip_instance = 0;
fence.ring = 0;
fence.fence = cs_req.seq_no;
err = amdgpu_cs_query_fence_status(&fence, AMDGPU_TIMEOUT_INFINITE, 0, &expired);
if (err) {
pr_perror("failed to query fence status");
goto err_cs_submit_ib;
}
if (!expired) {
pr_err("IB execution did not complete\n");
err = -EBUSY;
goto err_cs_submit_ib;
}
if (type == SDMA_OP_VRAM_READ) {
err = write_fp(storage_fp, buffer, buffer_bo_size - buffer_space_remain);
if (err) {
pr_perror("failed to write out to storage");
goto err_cs_submit_ib;
}
}
err_cs_submit_ib:
amdgpu_cs_ctx_free(h_ctx);
if (err)
break;
}
err_ctx:
amdgpu_bo_list_destroy(h_bo_list);
err_bo_list:
free_and_unmap(packets_per_buffer * 28, h_bo_ib, h_va_ib, gpu_addr_ib, ib);
err_ib_gpu_alloc:
err = amdgpu_bo_va_op(h_bo_dst, 0, size, gpu_addr_dst, 0, AMDGPU_VA_OP_UNMAP);
if (err)
pr_perror("failed to GPU unmap the dest BO %lx, size = %lx", gpu_addr_dst, size);
err_dst_bo_map:
err = amdgpu_va_range_free(h_va_dst);
if (err)
pr_perror("dest range free failed");
err_dst_va:
err = amdgpu_bo_free(h_bo_dst);
if (err)
pr_perror("dest bo free failed");
err_dst_bo_prep:
err = amdgpu_bo_va_op(h_bo_src, 0, size, gpu_addr_src, 0, AMDGPU_VA_OP_UNMAP);
if (err)
pr_perror("failed to GPU unmap the src BO %lx, size = %lx", gpu_addr_src, size);
err_src_bo_map:
err = amdgpu_va_range_free(h_va_src);
if (err)
pr_perror("src range free failed");
err_src_va:
err = amdgpu_bo_free(h_bo_src);
if (err)
pr_perror("src bo free failed");
plugin_log_msg("Leaving sdma_copy_bo, err = %d\n", err);
return err;
}
void *dump_bo_contents(void *_thread_data)
{
struct thread_data *thread_data = (struct thread_data *)_thread_data;
struct kfd_criu_bo_bucket *bo_buckets = thread_data->bo_buckets;
struct amdgpu_gpu_info gpu_info = { 0 };
amdgpu_device_handle h_dev;
size_t max_bo_size = 0, image_size = 0, buffer_size;
uint64_t max_copy_size;
uint32_t major, minor;
int num_bos = 0;
int i, ret = 0;
FILE *bo_contents_fp = NULL;
void *buffer = NULL;
char img_path[40];
pr_info("Thread[0x%x] started\n", thread_data->gpu_id);
ret = amdgpu_device_initialize(thread_data->drm_fd, &major, &minor, &h_dev);
if (ret) {
pr_perror("failed to initialize device");
goto exit;
}
plugin_log_msg("libdrm initialized successfully\n");
ret = amdgpu_query_gpu_info(h_dev, &gpu_info);
if (ret) {
pr_perror("failed to query gpuinfo via libdrm");
goto exit;
}
max_copy_size = (gpu_info.family_id >= AMDGPU_FAMILY_AI) ? SDMA_LINEAR_COPY_MAX_SIZE :
SDMA_LINEAR_COPY_MAX_SIZE - 1;
for (i = 0; i < thread_data->num_of_bos; i++) {
if (bo_buckets[i].gpu_id == thread_data->gpu_id &&
(bo_buckets[i].alloc_flags & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))) {
image_size += bo_buckets[i].size;
if (bo_buckets[i].size > max_bo_size)
max_bo_size = bo_buckets[i].size;
}
}
buffer_size = kfd_max_buffer_size > 0 ? min(kfd_max_buffer_size, max_bo_size) : max_bo_size;
posix_memalign(&buffer, sysconf(_SC_PAGE_SIZE), buffer_size);
if (!buffer) {
pr_perror("Failed to alloc aligned memory. Consider setting KFD_MAX_BUFFER_SIZE.");
ret = -ENOMEM;
goto exit;
}
snprintf(img_path, sizeof(img_path), IMG_KFD_PAGES_FILE, thread_data->id, thread_data->gpu_id);
bo_contents_fp = open_img_file(img_path, true, &image_size);
if (!bo_contents_fp) {
pr_perror("Cannot fopen %s", img_path);
ret = -EIO;
goto exit;
}
for (i = 0; i < thread_data->num_of_bos; i++) {
if (bo_buckets[i].gpu_id != thread_data->gpu_id)
continue;
if (!(bo_buckets[i].alloc_flags & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)))
continue;
num_bos++;
/* perform sDMA based vram copy */
ret = sdma_copy_bo(bo_buckets[i], bo_contents_fp, buffer, buffer_size, h_dev, max_copy_size,
SDMA_OP_VRAM_READ);
if (ret) {
pr_err("Failed to drain the BO using sDMA: bo_buckets[%d]\n", i);
break;
}
}
exit:
pr_info("Thread[0x%x] done num_bos:%d ret:%d\n", thread_data->gpu_id, num_bos, ret);
if (bo_contents_fp)
fclose(bo_contents_fp);
xfree(buffer);
amdgpu_device_deinitialize(h_dev);
thread_data->ret = ret;
return NULL;
};
void *restore_bo_contents(void *_thread_data)
{
struct thread_data *thread_data = (struct thread_data *)_thread_data;
struct kfd_criu_bo_bucket *bo_buckets = thread_data->bo_buckets;
size_t image_size = 0, total_bo_size = 0, max_bo_size = 0, buffer_size;
struct amdgpu_gpu_info gpu_info = { 0 };
amdgpu_device_handle h_dev;
uint64_t max_copy_size;
uint32_t major, minor;
FILE *bo_contents_fp = NULL;
void *buffer = NULL;
char img_path[40];
int num_bos = 0;
int i, ret = 0;
pr_info("Thread[0x%x] started\n", thread_data->gpu_id);
ret = amdgpu_device_initialize(thread_data->drm_fd, &major, &minor, &h_dev);
if (ret) {
pr_perror("failed to initialize device");
goto exit;
}
plugin_log_msg("libdrm initialized successfully\n");
ret = amdgpu_query_gpu_info(h_dev, &gpu_info);
if (ret) {
pr_perror("failed to query gpuinfo via libdrm");
goto exit;
}
max_copy_size = (gpu_info.family_id >= AMDGPU_FAMILY_AI) ? SDMA_LINEAR_COPY_MAX_SIZE :
SDMA_LINEAR_COPY_MAX_SIZE - 1;
snprintf(img_path, sizeof(img_path), IMG_KFD_PAGES_FILE, thread_data->id, thread_data->gpu_id);
bo_contents_fp = open_img_file(img_path, false, &image_size);
if (!bo_contents_fp) {
pr_perror("Cannot fopen %s", img_path);
ret = -errno;
goto exit;
}
for (i = 0; i < thread_data->num_of_bos; i++) {
if (bo_buckets[i].gpu_id == thread_data->gpu_id &&
(bo_buckets[i].alloc_flags & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))) {
total_bo_size += bo_buckets[i].size;
if (bo_buckets[i].size > max_bo_size)
max_bo_size = bo_buckets[i].size;
}
}
if (total_bo_size != image_size) {
pr_err("%s size mismatch (current:%ld:expected:%ld)\n", img_path, image_size, total_bo_size);
ret = -EINVAL;
goto exit;
}
buffer_size = kfd_max_buffer_size > 0 ? min(kfd_max_buffer_size, max_bo_size) : max_bo_size;
posix_memalign(&buffer, sysconf(_SC_PAGE_SIZE), buffer_size);
if (!buffer) {
pr_perror("Failed to alloc aligned memory. Consider setting KFD_MAX_BUFFER_SIZE.");
ret = -ENOMEM;
goto exit;
}
for (i = 0; i < thread_data->num_of_bos; i++) {
if (bo_buckets[i].gpu_id != thread_data->gpu_id)
continue;
if (!(bo_buckets[i].alloc_flags & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)))
continue;
num_bos++;
ret = sdma_copy_bo(bo_buckets[i], bo_contents_fp, buffer, buffer_size, h_dev, max_copy_size,
SDMA_OP_VRAM_WRITE);
if (ret) {
pr_err("Failed to fill the BO using sDMA: bo_buckets[%d]\n", i);
break;
}
plugin_log_msg("** Successfully filled the BO using sDMA: bo_buckets[%d] **\n", i);
}
exit:
pr_info("Thread[0x%x] done num_bos:%d ret:%d\n", thread_data->gpu_id, num_bos, ret);
if (bo_contents_fp)
fclose(bo_contents_fp);
xfree(buffer);
amdgpu_device_deinitialize(h_dev);
thread_data->ret = ret;
return NULL;
};
int check_hsakmt_shared_mem(uint64_t *shared_mem_size, uint32_t *shared_mem_magic)
{
int ret;
struct stat st;
ret = stat(HSAKMT_SHM_PATH, &st);
if (ret) {
*shared_mem_size = 0;
return 0;
}
*shared_mem_size = st.st_size;
/* First 4 bytes of shared file is the magic */
ret = read_file(HSAKMT_SHM_PATH, shared_mem_magic, sizeof(*shared_mem_magic));
if (ret)
pr_perror("Failed to read shared mem magic");
else
plugin_log_msg("Shared mem magic:0x%x\n", *shared_mem_magic);
return 0;
}
int restore_hsakmt_shared_mem(const uint64_t shared_mem_size, const uint32_t shared_mem_magic)
{
int ret, fd;
struct stat st;
sem_t *sem = SEM_FAILED;
if (!shared_mem_size)
return 0;
if (!stat(HSAKMT_SHM_PATH, &st)) {
pr_debug("%s already exists\n", HSAKMT_SHM_PATH);
} else {
pr_info("Warning:%s was missing. Re-creating new file but we may lose perf counters\n",
HSAKMT_SHM_PATH);
fd = shm_open(HSAKMT_SHM, O_CREAT | O_RDWR, 0666);
ret = ftruncate(fd, shared_mem_size);
if (ret < 0) {
pr_err("Failed to truncate shared mem %s\n", HSAKMT_SHM);
close(fd);
return -errno;
}
ret = write(fd, &shared_mem_magic, sizeof(shared_mem_magic));
if (ret != sizeof(shared_mem_magic)) {
pr_perror("Failed to restore shared mem magic");
close(fd);
return -errno;
}
close(fd);
}
sem = sem_open(HSAKMT_SEM, O_CREAT, 0666, 1);
if (sem == SEM_FAILED) {
pr_perror("Failed to create %s", HSAKMT_SEM);
return -EACCES;
}
sem_close(sem);
return 0;
}
static int unpause_process(int fd)
{
int ret = 0;
struct kfd_ioctl_criu_args args = { 0 };
args.op = KFD_CRIU_OP_UNPAUSE;
ret = kmtIoctl(fd, AMDKFD_IOC_CRIU_OP, &args);
if (ret) {
pr_perror("Failed to unpause process");
goto exit;
}
// Reset the KFD FD