Fairwaves version of the UHD drivers, tweaked to support Fairwaves UmTRX.
|firmware||ZPU: DEBUG: Output assert() message before aborting ZPU due to failed…|
|fpga||FPGA: Max sample rate was fixed.|
|host||Host: Power down DC comparators in LMS to improve Rx linearity (as pe…|
|README||document present directory layout and interface dependencies|
Overview ======== This branch includes changes to UHD to make it working with Fairwaves UmTRX hardware. Among other changes it includes ICAP and other assorted FPGA timing issues: 26-JAN-2012: * Fix ICAP timing problems for UmTRX: the maximum clock rate for the ICAP module on the Spartan-6 FPGA is 20 MHz * Add a clk_icap to top level UmTRX design (13 MHz, 180 deg. phase clock generated by pll_clk.xco, a COREGEN module). * Add pipeline registers pps signal in ./fpga/usrp2/timing/time_64bit.v * Create ./fpga/usrp2/s6_icap_wb.v to clock Spartan-6 ICAP IP Core with clk_icap * Modify ./fpga/usrp2/top/N2x0/u2plus_umtrx.v and u2plus_core.v to connect clk_icap (not connected for non-UmTRX designs) * Change ISE tool settings based on smartXplorer parameters that meet timing and modify Makefile.UmTRX accordingly. Implementation ============== host/lib/usrp/dboard/db_lms.cpp - standard UHD description of UmTRX embedded dboard (including frequency range and so on). host/lib/usrp/umtrx/* - implementation of UmTRX-specifix dboard interface and other classes. host/lib/usrp/usrp2/usrp2_impl.hpp - common registration\detection functions shared with USRP2 host/lib/usrp/usrp2/usrp2_iface.hpp - also used in UmTRX host/lib/usrp/usrp2/fw_common.h - place for shared protocol constants to communicate with ZPU host/lib/usrp/umtrx/umtrx_impl.cpp - the place where SPI debug functions could be inserted into so they are triggered upon multi_usrp init: for example reg_dump(); Testing ======= Insert your SPI debug calls into usrp2_impl.cpp, run make in host/build/utils/ and run following command to trigger debug: ./usrp_burn_mb_eeprom --key hardware 2>&1 > test.out This command will not modify anything on dboard or LMS unless specifically asked to in usrp2_impl.cpp Notes ===== If MAP fails when remaking the UmTRX FPGA bitstream under Ubuntu Linux for ISE v13.3 and below, define: LD_PRELOAD="$XILINX/lib/lin/libboost_serialization-gcc41-mt-p-1_38.so.1.38.0" after sourcing the Xilinx settings and before issuing: make -f Makefile.UmTRX