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Remove dependency on plib

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1 parent c2f1d87 commit 8920e48e8da2a371a6283707fe9793dcf31836a0 @GeneApperson GeneApperson committed Feb 13, 2013
Showing with 1,465 additions and 337 deletions.
  1. +5 −15 hardware/pic32/cores/pic32/HardwareSerial.cpp
  2. +0 −2 hardware/pic32/cores/pic32/HardwareSerial_cdcacm.c
  3. +2 −1 hardware/pic32/cores/pic32/HardwareSerial_usb.c
  4. +2 −2 hardware/pic32/cores/pic32/System_Defs.h
  5. +15 −12 hardware/pic32/cores/pic32/Tone.cpp
  6. +3 −2 hardware/pic32/cores/pic32/WInterrupts.c
  7. +655 −0 hardware/pic32/cores/pic32/WSystem.c
  8. +148 −2 hardware/pic32/cores/pic32/p32_defs.h
  9. +30 −13 hardware/pic32/cores/pic32/task_manager.c
  10. +26 −43 hardware/pic32/cores/pic32/wiring.c
  11. +25 −14 hardware/pic32/cores/pic32/wiring.h
  12. +40 −44 hardware/pic32/cores/pic32/wiring_analog.c
  13. +1 −1 hardware/pic32/cores/pic32/wiring_digital.c
  14. +5 −0 hardware/pic32/cores/pic32/wiring_private.h
  15. +24 −7 hardware/pic32/libraries/EEPROM/utility/Deeprom.c
  16. +16 −0 hardware/pic32/libraries/EEPROM/utility/Deeprom.h
  17. +246 −0 hardware/pic32/libraries/EEPROM/utility/flash.c
  18. +78 −0 hardware/pic32/libraries/EEPROM/utility/flash.h
  19. +45 −17 hardware/pic32/libraries/SD/utility/Sd2Card.cpp
  20. +56 −72 hardware/pic32/libraries/SD/utility/Sd2PinMap.h
  21. +3 −3 hardware/pic32/libraries/Servo/Servo.cpp
  22. +2 −1 hardware/pic32/libraries/Servo/utility/int.c
  23. +1 −1 hardware/pic32/libraries/Servo/utility/int.h
  24. +11 −10 hardware/pic32/libraries/SoftPWMServo/SoftPWMServo.cpp
  25. +1 −1 hardware/pic32/libraries/Wire/utility/twi.c
  26. +4 −17 hardware/pic32/variants/Fubarino_Mini/Board_Data.c
  27. +9 −19 hardware/pic32/variants/Max32/Board_Data.c
  28. +4 −12 hardware/pic32/variants/fubarino_sd_v10/Board_Data.c
  29. +4 −10 hardware/pic32/variants/fubarino_sd_v11/Board_Data.c
  30. +4 −16 hardware/pic32/variants/quicK240/Board_Data.c
View
20 hardware/pic32/cores/pic32/HardwareSerial.cpp
@@ -60,8 +60,9 @@
//* Sep 8, 2012 <BrianSchmalz> Fix dropping bytes on USB RX bug
//* Jul 26, 2012 <GeneApperson> Added PPS support for PIC32MX1xx/MX2xx devices
//* Nov 23, 2012 <BrianSchmalz> Auto-detect when to use BRGH = 1 (high baud rates)
+//* Feb 6, 2013 <GeneApperson> Removed dependencies on the Microchip plib library
//************************************************************************
-#ifndef __LANGUAGE_C__
+#if !defined(__LANGUAGE_C__)
#define __LANGUAGE_C__
#endif
@@ -70,7 +71,7 @@
#include <inttypes.h>
#include <p32xxxx.h>
-#include <plib.h>
+#include <sys/attribs.h>
#include "wiring.h"
#include "wiring_private.h"
@@ -193,20 +194,9 @@ void HardwareSerial::begin(unsigned long baudRate)
mapPps(pinRx, ppsRx);
#endif
- /* Compute the address of the interrupt priority control
- ** registers used by this UART
- */
- ipc = ((p32_regset *)&IPC0) + (vec / 4); //interrupt priority control reg set
-
- /* Compute the number of bit positions to shift to get to the
- ** correct position for the priority bits for this IRQ.
- */
- irq_shift = 8 * (vec % 4);
-
/* Set the interrupt privilege level and sub-privilege level
*/
- ipc->clr = (0x1F << irq_shift);
- ipc->set = ((ipl << 2) + spl) << irq_shift;
+ setIntPriority(vec, ipl, spl);
/* Clear the interrupt flags, and set the interrupt enables for the
** interrupts used by this UART.
@@ -573,7 +563,7 @@ void USBSerial::begin(unsigned long baudRate)
DebugViaSerial0("returned from cdcacm_register");
// Must enable glocal interrupts - in this case, we are using multi-vector mode
- INTEnableSystemMultiVectoredInt();
+ //INTEnableSystemMultiVectoredInt();
DebugViaSerial0("INTEnableSystemMultiVectoredInt");
}
View
2 hardware/pic32/cores/pic32/HardwareSerial_cdcacm.c
@@ -19,8 +19,6 @@
//************************************************************************
-#include <plib.h>
-
//#include "main.h"
#include "HardwareSerial.h"
//* make sure the cpu selected has a usb port
View
3 hardware/pic32/cores/pic32/HardwareSerial_usb.c
@@ -18,7 +18,8 @@
//************************************************************************
-#include <plib.h>
+#include <p32xxxx.h>
+#include <sys/attribs.h>
#include "HardwareSerial.h"
View
4 hardware/pic32/cores/pic32/System_Defs.h
@@ -118,11 +118,11 @@
*/
#if defined(__PIC32MX1XX__) || defined(__PIC32MX2XX__)
#define _CT_IPL_ISR IPL7SOFT
-#define _CT_IPL_IPC CT_INT_PRIOR_7
+#define _CT_IPL_IPC 7
#define _CT_SPL_IPC 0
#else
#define _CT_IPL_ISR IPL7SRS
-#define _CT_IPL_IPC CT_INT_PRIOR_7
+#define _CT_IPL_IPC 7
#define _CT_SPL_IPC 0
#endif
View
27 hardware/pic32/cores/pic32/Tone.cpp
@@ -37,13 +37,12 @@
//* Oct 15, 2010 Started on Tone.cpp for PIC32
//* Aug 7, 2011 <GeneApperson> Completed implementation for single tone.
//* Oct 5, 2011 <MLS> Issue #132 Tone fails when the frequency is 0 fixed
+// Feb 6, 2013 <GeneApperson> Removed dependencies on the Microchip plib library
//************************************************************************
#define LANGUAGE_C
#define __LANGUAGE_C__
-//* the Microchip .h files do not know about C++
-#include <plib.h>
//#define DEBUG_TONE
@@ -56,12 +55,15 @@
#include "HardwareSerial.h"
#endif
+#include <p32xxxx.h>
+#include <sys/attribs.h>
+
#include "wiring.h"
#define OPT_SYSTEM_INTERNAL
#define OPT_BOARD_INTERNAL //pull in internal symbol definitons
-#include "pins_arduino.h"
#include "p32_defs.h"
+#include "pins_arduino.h"
// timerx_toggle_count:
// > 0 - duration specified
@@ -100,9 +102,10 @@ uint8_t port;
if (tone_pin == 255)
{
// No tone currently playing. Init the timer.
- T1CON = T1_PS_1_256;
- mT1ClearIntFlag();
- ConfigIntTimer1(T1_INT_ON | _T1_IPL_IPC | (_T1_SPL_IPC << 4));
+ T1CON = TACON_PS_256;
+ clearIntFlag(_TIMER_1_IRQ);
+ setIntPriority(_TIMER_1_VECTOR, _T1_IPL_IPC, _T1_SPL_IPC);
+ setIntEnable(_TIMER_1_IRQ);
}
else if (_pin != tone_pin)
{
@@ -130,17 +133,17 @@ uint8_t port;
timer1_toggle_count = -1;
}
- TMR1 = 0;
- PR1 = ((F_CPU / 256) / 2 / frequency);
- T1CONSET = T1_ON;
+ TMR1 = 0;
+ PR1 = ((__PIC32_pbClk / 256) / 2 / frequency);
+ T1CONSET = TACON_ON;
}
}
//************************************************************************
void disableTimer(uint8_t _timer)
{
- mT1IntEnable(0);
- T1CON = 0;;
+ clearIntEnable(_TIMER_1_IRQ);
+ T1CON = 0;
tone_pin = 255;
}
@@ -187,7 +190,7 @@ void __ISR(_TIMER_1_VECTOR, _T1_IPL_ISR) Timer1Handler(void)
}
// clear the interrupt flag
- mT1ClearIntFlag();
+ clearIntFlag(_TIMER_1_IRQ);
}
}; //* extern "C"
View
5 hardware/pic32/cores/pic32/WInterrupts.c
@@ -32,18 +32,19 @@
//* Aug 30, 2011 <GeneApperson> clear interrupt flag after return from
//* user interrupt function (issue #109)
//* Jul 26, 2012 <GeneApperson> Added PPS support for PIC32MX1xx/MX2xx devices
+// Feb 6, 2012 <GeneApperson> Removed dependencies on the Microchip plib library
//************************************************************************
-#include <plib.h>
#include <p32xxxx.h>
+#include <sys/attribs.h>
#include <inttypes.h>
#include <stdio.h>
#define OPT_SYSTEM_INTERNAL
#define OPT_BOARD_INTERNAL //pull in internal symbol definitons
-#include "pins_arduino.h"
#include "p32_defs.h"
+#include "pins_arduino.h"
#include "WConstants.h"
#include "wiring_private.h"
View
655 hardware/pic32/cores/pic32/WSystem.c
@@ -0,0 +1,655 @@
+/************************************************************************/
+/* */
+/* WSystem.c -- Low Level System Management Functions */
+/* */
+/************************************************************************/
+/* Author: Gene Apperson */
+/* Copyright 2012, Digilent. All rights reserved */
+/************************************************************************/
+/* Module Description: */
+/* */
+/* This module contains functions for low level system control and */
+/* management of the processor. This includes things like interrupt */
+/* management and processor configuration. */
+/* */
+/************************************************************************/
+//* This module is free software; you can redistribute it and/or
+//* modify it under the terms of the GNU Lesser General Public
+//* License as published by the Free Software Foundation; either
+//* version 2.1 of the License, or (at your option) any later version.
+//*
+//* This library is distributed in the hope that it will be useful,
+//* but WITHOUT ANY WARRANTY; without even the implied warranty of
+//* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+//* Lesser General Public License for more details.
+//*
+//* You should have received a copy of the GNU Lesser General
+//* Public License along with this library; if not, write to the
+//* Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+//* Boston, MA 02111-1307 USA
+/************************************************************************/
+/* Revision History: */
+/* */
+/* 08/23/2012(GeneApperson): Created */
+/* */
+/************************************************************************/
+
+
+/* ------------------------------------------------------------ */
+/* Include File Definitions */
+/* ------------------------------------------------------------ */
+
+#include <p32xxxx.h>
+
+#define OPT_SYSTEM_INTERNAL
+#include <System_Defs.h>
+#include <p32_defs.h>
+
+#include "wiring.h"
+
+/* ------------------------------------------------------------ */
+/* Local Type Definitions */
+/* ------------------------------------------------------------ */
+
+
+/* ------------------------------------------------------------ */
+/* Global Variables */
+/* ------------------------------------------------------------ */
+
+
+/* ------------------------------------------------------------ */
+/* Local Variables */
+/* ------------------------------------------------------------ */
+
+
+/* ------------------------------------------------------------ */
+/* Forward Declarations */
+/* ------------------------------------------------------------ */
+
+
+/* ------------------------------------------------------------ */
+/* Public Interface Functions */
+/* ------------------------------------------------------------ */
+/* Interrupt Management Functions */
+/* ------------------------------------------------------------ */
+/*** enableInterrupts
+**
+** Parameters:
+** none
+**
+** Return Value:
+** Previous state of the global interrupt enable flag
+**
+** Errors:
+** none
+**
+** Description:
+** This function sets the global interrupt enable flag,
+** enabling all interrupts.
+*/
+
+uint32_t __attribute__((nomips16)) enableInterrupts(void)
+{
+ uint32_t status = 0;
+
+ asm volatile("ei %0" : "=r"(status));
+
+ return status;
+}
+
+/* ------------------------------------------------------------ */
+/*** disableInterrutps
+**
+** Parameters:
+** none
+**
+** Return Value:
+** Previous state fo the global interrupt enable flag
+**
+** Errors:
+** none
+**
+** Description:
+** This function clears the global interrupt enable flag,
+** disabling all interrupts.
+*/
+
+uint32_t __attribute__((nomips16)) disableInterrupts(void)
+{
+ uint32_t status = 0;
+
+ asm volatile("di %0" : "=r"(status));
+
+ return status;
+}
+
+/* ------------------------------------------------------------ */
+/*** restoreInterrupts
+**
+** Parameters:
+** st - Previous state of global interrupt enable flag
+**
+** Return Value:
+** none
+**
+** Errors:
+** none
+**
+** Description:
+** This function restores the state of the global interrupt
+** enable flag to a previous state. The value passed in for
+** st should be a value previously returned by either
+** enableInterrupts() or disableInterrupts().
+*/
+
+void __attribute__((nomips16)) restoreInterrupts(uint32_t st)
+{
+ if (st & 0x00000001)
+ {
+ asm volatile("ei");
+ }
+ else
+ {
+ asm volatile("di");
+ }
+}
+
+/* ------------------------------------------------------------ */
+/*** getIntFlag
+**
+** Parameters:
+** irq - Interrupt request number
+**
+** Return Value:
+** Returns the state of the request interrupt flag.
+**
+** Errors:
+** none
+**
+** Description:
+** Return the state of the interrupt request flag for the
+** specified interrupt. The return value will be 0 if the
+** flag is not set, and non-zero if the flag is set.
+*/
+
+uint32_t getIntFlag(int irq)
+{
+ p32_regset * ifs;
+
+ ifs = ((p32_regset *)&IFS0) + (irq / 32);
+ return (ifs->reg & (1 << (irq % 32))) != 0;
+}
+
+
+/* ------------------------------------------------------------ */
+/*** clearIntFlag
+**
+** Parameters:
+** irq - Interrupt request number
+**
+** Return Value:
+** none
+**
+** Errors:
+** none
+**
+** Description:
+** Clear the interrupt request flag for the specified interrupt.
+*/
+
+void clearIntFlag(int irq)
+{
+ p32_regset * ifs;
+
+ ifs = ((p32_regset *)&IFS0) + (irq / 32);
+ ifs->clr = 1 << (irq % 32);
+}
+
+/* ------------------------------------------------------------ */
+/*** setIntEnable
+**
+** Parameters:
+** irq - Interrupt request number
+**
+** Return Value:
+** Returns the previous state of the specified interrupt enable flag
+**
+** Errors:
+** none
+**
+** Description:
+** Set the interrupt enable flag for the specified interrupt
+** request. This will enable whatever peripheral interrupt is
+** associated with the specified interrupt request.
+*/
+
+uint32_t setIntEnable(int irq)
+{
+ p32_regset * iec;
+ uint32_t st;
+
+ iec = ((p32_regset *)&IEC0) + (irq / 32);
+ st = iec->reg;
+ iec->set = 1 << (irq % 32);
+ return st;
+}
+
+/* ------------------------------------------------------------ */
+/*** clearIntEnable
+**
+** Parameters:
+** irq - interrupt request number
+**
+** Return Value:
+** Returns the previous state of the specified interrupt enable flag
+**
+** Errors:
+** none
+**
+** Description:
+** Disable the interrupt for the specified interrupt request
+*/
+
+uint32_t clearIntEnable(int irq)
+{
+ p32_regset * iec;
+ uint32_t st;
+
+ iec = ((p32_regset *)&IEC0) + (irq / 32);
+ st = iec->reg;
+ iec->clr = 1 << (irq % 32);
+ return st;
+}
+
+/* ------------------------------------------------------------ */
+/*** restoreIntEnable
+**
+** Parameters:
+** irq - interrupt request number
+** st - previous enable state to restore
+**
+** Return Value:
+** none
+**
+** Errors:
+** none
+**
+** Description:
+** This function restores the interrupt enable flag to a
+** previous state. The value specified in the st parameter
+** should be a value previously returned by setIntEnable()
+** or clearIntEnable()
+*/
+
+void restoreIntEnable(int irq, uint32_t st)
+{
+ p32_regset * iec;
+ uint32_t bit;
+
+ iec = ((p32_regset *)&IEC0) + (irq / 32);
+ bit = (1 << (irq % 32));
+ if ((st & bit) != 0)
+ {
+ iec->set = bit;
+ }
+ else
+ {
+ iec->clr = bit;
+ }
+}
+
+/* ------------------------------------------------------------ */
+/*** setIntPriority
+**
+** Parameters:
+** vec - interrupt vector number
+** ipl - interrupt priority level to set
+** spl - interrupt sub-priority level to set
+**
+** Return Value:
+** none
+**
+** Errors:
+** none
+**
+** Description:
+** This function sets interrupt priority and sub-priority levels
+** for the specified interrupt vector.
+*/
+
+void setIntPriority(int vec, int ipl, int spl)
+{
+ p32_regset * ipc;
+ int bn;
+
+ /* Compute the address of the interrupt priority control register used
+ ** by this interrupt vector
+ */
+ ipc = ((p32_regset *)&IPC0) + (vec / 4);
+
+ /* Compute the number of bit positions to shift to get to the
+ ** correct position for the priority bits for this vector.
+ */
+ bn = 8 * (vec % 4);
+
+ /* Set the interrupt privilege level and sub-privilege level
+ */
+ ipc->clr = (0x1F << bn);
+ ipc->set = ((ipl << 2) + spl) << bn;
+}
+
+/* ------------------------------------------------------------ */
+/*** getIntPriority
+**
+** Parameters:
+** vec - interrupt vector number
+** pipl - pointer to variable to receive priority
+** pspl - pointer to variable to receive sub-priority
+**
+** Return Value:
+** none
+**
+** Errors:
+** none
+**
+** Description:
+** This function sets interrupt priority and sub-priority levels
+** for the specified interrupt vector.
+*/
+
+void getIntPriority(int vec, int * pipl, int * pspl)
+{
+ p32_regset * ipc;
+ int bn;
+
+ /* Compute the address of the interrupt priority control register used
+ ** by this interrupt vector
+ */
+ ipc = ((p32_regset *)&IPC0) + (vec / 4);
+
+ /* Compute the number of bit positions to shift to get to the
+ ** correct position for the priority bits for this vector.
+ */
+ bn = 8 * (vec % 4);
+
+ /* Set the interrupt privilege level and sub-privilege level
+ */
+ *pipl = (ipc->reg >> (bn+2)) & 0x07;
+ *pspl = (ipc->reg >> bn) & 0x03;
+
+}
+
+/* ------------------------------------------------------------ */
+/* Misc Processor Support Functions */
+/* ------------------------------------------------------------ */
+/*** getPeripheralClock()
+**
+** Parameters:
+** none
+**
+** Return Value:
+** Returns the current peripheral bus clock frequency
+**
+** Errors:
+** none
+**
+** Description:
+** Get the peripheral bus clock frequency
+*/
+
+uint32_t getPeripheralClock()
+{
+ uint32_t clkPb;
+
+ clkPb = F_CPU;
+ clkPb >>= OSCCONbits.PBDIV;
+
+ return clkPb;
+
+}
+
+/* ------------------------------------------------------------ */
+/*** readCoreTimer
+**
+** Parameters:
+** none
+**
+** Return Value:
+** Returns core timer count value
+**
+** Errors:
+** none
+**
+** Description:
+** Returns the current value of the core timer.
+*/
+
+uint32_t __attribute__((nomips16)) readCoreTimer(void)
+{
+ uint32_t tmr;
+
+ // Get the value of the core timer count register.
+ asm volatile("mfc0 %0, $9" : "=r"(tmr));
+
+ return tmr;
+}
+
+/* ------------------------------------------------------------ */
+/*** writeCoreTimer
+**
+** Parameters:
+** tmr - value to write to core timer counter
+**
+** Return Value:
+** none
+**
+** Errors:
+** none
+**
+** Description:
+** Writes the specified value to the core timer count register.
+*/
+
+void __attribute__((nomips16)) writeCoreTimer(uint32_t tmr)
+{
+ // Write the value to the core timer count register
+ asm volatile("mtc0 %0, $9": "+r"(tmr));
+
+}
+
+/* ------------------------------------------------------------ */
+/* Private System Configuration Functions */
+/* ------------------------------------------------------------ */
+/*** configSystem
+**
+** Parameters:
+** clk - processor master clock frequency
+**
+** Return Value:
+** none
+**
+** Errors:
+** none
+**
+** Description:
+** Configure the processor. This disables data ram wait states,
+** sets the number of flash wait states and enables predictive
+** prefetch for both cached and non-cached memory segments.
+*/
+
+void __attribute__ ((nomips16)) _configSystem(uint32_t clk)
+{
+ uint32_t stInt;
+#ifdef _PCACHE
+ uint32_t stCache;
+ uint32_t wait;
+ register unsigned long tmp;
+#endif
+
+ stInt = disableInterrupts();
+
+ /* Disable wait states in data ram.
+ */
+ BMXCONCLR = (1 << _BMXCON_BMXWSDRM_POSITION);
+
+#ifdef _PCACHE
+
+ stCache = CHECON;
+
+ /* Configure predictive prefetch caching for both cached and
+ ** non-cached memory regions.
+ */
+ stCache |= (3 << _CHECON_PREFEN_POSITION);
+
+ /* Turn on caching for KSEG0
+ */
+ asm("mfc0 %0,$16,0" : "=r"(tmp));
+ tmp = (tmp & ~7) | 3;
+ asm("mtc0 %0,$16,0" :: "r" (tmp));
+
+ /* Configure the number of wait states in the program flash
+ */
+ wait = 0;
+
+ while(clk > FLASH_SPEED_HZ)
+ {
+ wait += 1;
+ clk -= FLASH_SPEED_HZ;
+ }
+
+ stCache &= ~_CHECON_PFMWS_MASK;
+ stCache |= (wait << _CHECON_PFMWS_POSITION);
+
+ CHECON = stCache;
+
+#endif
+
+
+ restoreInterrupts(stInt);
+}
+
+/* ------------------------------------------------------------ */
+/*** _enableMultiVectorInterrupts
+**
+** Parameters:
+** none
+**
+** Return Value:
+** none
+**
+** Errors:
+** none
+**
+** Description:
+** Configure the system for vectored interrupts and turn
+** interrupts on.
+*/
+
+void __attribute__ ((nomips16)) _enableMultiVectorInterrupts()
+{
+ unsigned int val;
+
+ /* Set the CP0 bit so that interrupt exceptions use the
+ ** special interrupt vector and not the general exception vector.
+ */
+ asm volatile("mfc0 %0,$13" : "=r"(val));
+ val |= 0x00800000;
+ asm volatile("mtc0 %0,$13" : "+r"(val));
+
+ /* Turn on multi-vectored interrupts.
+ */
+ INTCONSET = _INTCON_MVEC_MASK;
+
+ /* Enable interrupts.
+ */
+ enableInterrupts();
+
+}
+
+/* ------------------------------------------------------------ */
+/*** _initCoreTimer
+**
+** Parameters:
+** prd - Core timer interrupt period
+**
+** Return Value:
+** none
+**
+** Errors:
+** none
+**
+** Description:
+** Clear the core timer counter and initialize the compare
+** period register.
+*/
+
+void __attribute__((nomips16)) _initCoreTimer(uint32_t prd)
+{
+ /* Clear the core timer counter
+ */
+ asm volatile("mtc0 $0,$9");
+
+ /* Store the requested value in the compare register
+ */
+ asm volatile("mtc0 %0,$11" : "+r"(prd));
+}
+
+/* ------------------------------------------------------------ */
+/*** _softwareReset
+**
+** Parameters:
+** none
+**
+** Return Value:
+** Does not return
+**
+** Errors:
+** none
+**
+** Description:
+** This function performs a software reset of the processor. This
+** requires the following steps: Unlock the processor; Set the SWRST
+** bit in the RSWRT register; Read the RSWRT register.
+**
+** Note:
+** Something like the while(1) needs to be performed after the read
+** to ensure that no other instructions are executed before the
+** actual reset occurs.
+*/
+
+ void __attribute__((noreturn)) _softwareReset(void)
+{
+ volatile int * p = &RSWRST;
+
+ // Unlock the system
+ disableInterrupts();
+ SYSKEY = 0;
+ SYSKEY = 0xAA996655;
+ SYSKEY = 0x556699AA;
+
+ // Perform the software reset
+ RSWRSTSET=_RSWRST_SWRST_MASK;
+ *p;
+
+ // Wait for the rest to take place
+ while(1);
+
+}
+
+/* ------------------------------------------------------------ */
+/*** ProcName
+**
+** Parameters:
+**
+** Return Value:
+**
+** Errors:
+**
+** Description:
+**
+*/
+
+/* ------------------------------------------------------------ */
+
+/************************************************************************/
+
View
150 hardware/pic32/cores/pic32/p32_defs.h
@@ -36,14 +36,21 @@
//************************************************************************
//* Oct 2, 2011 <Gene Apperson> created
//* Jul 26, 2012 <GeneApperson> Added PPS support for PIC32MX1xx/MX2xx devices
+//* Feb 6, 2013 <GeneApperson> Added bit definitions for several peripherals
//************************************************************************
-#ifndef _P32_DEFS_H
+#if !defined(_P32_DEFS_H)
#define _P32_DEFS_H
#include "cpudefs.h"
-#include <inttypes.h>
+#include <inttypes.h>
+
+/* ------------------------------------------------------------ */
+/* Misc. Declarations */
+/* ------------------------------------------------------------ */
+
+#define FLASH_SPEED_HZ 30000000
/* ------------------------------------------------------------ */
/* Register Declarations */
@@ -193,13 +200,124 @@ typedef struct {
volatile p32_regset tmxPr;
} p32_timer;
+/* Define bits in the timer control register.
+** Type A timers (timer1) have different control bits
+** than Type B timers (timer2 - timer5)
+*/
+// Type A timer - Timer1
+#define _BN_TACON_ON 15
+#define _BN_TACON_FRZ 14
+#define _BN_TACON_SIDL 13
+#define _BN_TACON_TWDIS 12
+#define _BN_TACON_TWIP 11
+#define _BN_TACON_TGATE 7
+#define _BN_TACON_TCKPS 4
+#define _BN_TACON_TSYNC 2
+#define _BN_TACON_TCS 1
+
+#define TACON_ON (1 << _BN_TACON_ON)
+#define TACON_OFF (0)
+#define TACON_FRZ_ON (1 << _BN_TACON_FRZ)
+#define TACON_FRZ_OFF (0)
+#define TACON_IDLE_STOP (1 << _BN_TACON_SIDL)
+#define TACON_IDLE_RUN (0)
+#define TACON_TWDIS_ON (1 << _BN_TACON_TWDIS)
+#define TACON_TWDIS_OFF (0)
+#define TACON_TWIP (1 << _BN_TACON_TWIP)
+#define TACON_TGATE_ON (1 << _BN_TACON_TGATE)
+#define TACON_TGATE_OFF (0)
+#define TACON_TSYNC_ON (1 << _BN_TACON_TSYNC)
+#define TACON_TSYNC_OFF (0)
+
+#define TACON_SRC_INT (0 << _BN_TACON_TCS)
+#define TACON_SRC_EXT (1 << _BN_TACON_TCS)
+
+#define TACON_PS_MASK (3 << _BN_TACON_TCKPS)
+#define TACON_PS_1 (0 << _BN_TACON_TCKPS)
+#define TACON_PS_8 (1 << _BN_TACON_TCKPS)
+#define TACON_PS_64 (2 << _BN_TACON_TCKPS)
+#define TACON_PS_256 (3 << _BN_TACON_TCKPS)
+
+// Type B timer - Timer2-Timer5
+#define _BN_TBCON_ON 15
+#define _BN_TBCON_FRZ 14
+#define _BN_TBCON_SIDL 13
+#define _BN_TBCON_TGATE 7
+#define _BN_TBCON_TCKPS 4
+#define _BN_TBCON_T32 3
+#define _BN_TBCON_TCS 1
+
+#define TBCON_ON (1 << _BN_TBCON_ON)
+#define TBCON_OFF (0)
+#define TBCON_FRZ_ON (1 << _BN_TBCON_FRZ)
+#define TBCON_FRZ_OFF (0)
+#define TBCON_IDLE_STOP (1 << _BN_TBCON_SIDL)
+#define TBCON_IDLE_RUN (0)
+#define TBCON_TGATE_ON (1 << _BN_TBCON_TGATE)
+#define TBCON_TGATE_OFF (0)
+
+#define TBCON_PS_MASK (7 << _BN_TBCON_TCKPS)
+#define TBCON_PS_1 (0 << _BN_TBCON_TCKPS)
+#define TBCON_PS_2 (1 << _BN_TBCON_TCKPS)
+#define TBCON_PS_4 (2 << _BN_TBCON_TCKPS)
+#define TBCON_PS_8 (3 << _BN_TBCON_TCKPS)
+#define TBCON_PS_16 (4 << _BN_TBCON_TCKPS)
+#define TBCON_PS_32 (5 << _BN_TBCON_TCKPS)
+#define TBCON_PS_64 (6 << _BN_TBCON_TCKPS)
+#define TBCON_PS_256 (7 << _BN_TBCON_TCKPS)
+
+#define TBCON_MODE32 (1 << _BN_TBCON_T32)
+#define TBCON_MODE16 (0)
+#define TBCON_SRC_EXT (1 << _BN_TBCON_TCS)
+#define TBCON_SRC_INT (0)
+
/* This structure defines the registers for a PIC32 Input Capture.
*/
typedef struct {
volatile p32_regset icxCon;
volatile p32_regbuf icxBuf;
} p32_ic;
+/* Define bits in the incput capture control register
+*/
+#define _BN_ICCON_ON 15
+#define _BN_ICCON_FRZ 14
+#define _BN_ICCON_SIDL 13
+#define _BN_ICCON_FEDGE 9
+#define _BN_ICCON_C32 8
+#define _BN_ICCON_ICTMR 7
+#define _BN_ICCON_ICI 5
+#define _BN_ICCON_ICOV 4
+#define _BN_ICCON_ICBNE 3
+#define _BN_ICCON_ICM 0
+
+#define ICCON_ON (1 << _BN_ICCON_ON)
+#define ICCON_OFF (0)
+#define ICCON_FRZ_ON (1 << _BN_ICCON_FRZ)
+#define ICCON_FRZ_OFF (0)
+#define ICCON_IDLE_STOP (1 << _BN_ICCON_SIDL)
+#define ICCON_IDLE_RUN (0)
+#define ICCON_FEDGE_RISING (1 << _BN_ICCON_FEDGE)
+#define ICCON_FEDGE_FALLING (0)
+#define ICCON_WIDTH_32 (1 << _BN_ICCON_C32)
+#define ICCON_WIDTH_16 (0)
+#define ICCON_SOURCE_TIMER2 (1 << _BN_ICCON_ICTMR)
+#define ICCON_SOURCE_TIMER3 (0)
+#define ICCON_INT_FOURTH_EVENT (3 << _BN_ICCON_ICI)
+#define ICCON_INT_THIRD_EVENT (2 << _BN_ICCON_ICI)
+#define ICCON_INT_SECOND_EVENT (1 << _BN_ICCON_ICI)
+#define ICCON_INT_EVERY_EVENT (0 << _BN_ICCON_ICI)
+#define ICCON_OVERFLOW (1 << _BN_ICCON_ICOV)
+#define ICCON_ICBNE (1 << _BN_ICCON_ICBNE)
+#define ICCON_ICM_INTERRUPT (7 << _BN_ICCON_ICM)
+#define ICCON_ICM_EVERY_EDGE (6 << _BN_ICCON_ICM)
+#define ICCON_ICM_RISING_16 (5 << _BN_ICCON_ICM)
+#define ICCON_ICM_RISING_4 (4 << _BN_ICCON_ICM)
+#define ICCON_ICM_RISING_EDGE (3 << _BN_ICCON_ICM)
+#define ICCON_ICM_FALLING_EDGE (2 << _BN_ICCON_ICM)
+#define ICCON_ICM_EDGE_DETECT (1 << _BN_ICCON_ICM)
+#define ICCON_ICM_DISABLE (0 << _BN_ICCON_ICM)
+
/* This structure defines the registers for a PIC32 Output Compare.
*/
typedef struct {
@@ -208,6 +326,34 @@ typedef struct {
volatile p32_regset ocxRs;
} p32_oc;
+/* Define bits in the output compare control register
+*/
+#define _BN_OCCON_ON 15
+#define _BN_OCCON_SIDL 13
+#define _BN_OCCON_OC32 5
+#define _BN_OCCON_OCFLT 4
+#define _BN_OCCON_OCTSEL 3
+#define _BN_OCCON_OCM 0
+
+#define OCCON_ON (1 << _BN_OCCON_ON)
+#define OCCON_OFF (0)
+#define OCCON_IDLE_STOP (1 << _BN_OCCON_SIDL)
+#define OCCON_IDLE_RUN (0)
+#define OCCON_MODE32 (1 << _BN_OCCON_OC32)
+#define OCCON_MODE16 (0)
+#define OCCON_OCFLT (1 << _BN_OCCON_OCFLT)
+#define OCCON_SRC_TIMER3 (1 << _BN_OCCON_OCTSEL)
+#define OCCON_SRC_TIMER2 (0)
+
+#define OCCON_PWM_FAULT_ENABLE (7 << _BN_OCCON_OCM)
+#define OCCON_PWM_FAULT_DISABLE (6 << _BN_OCCON_OCM)
+#define OCCON_PULSE_CONTINUOUS (5 << _BN_OCCON_OCM)
+#define OCCON_PULSE_SINGLE (4 << _BN_OCCON_OCM)
+#define OCCON_PULSE_TOGGLE (3 << _BN_OCCON_OCM)
+#define OCCON_FALLING_EDGE (2 << _BN_OCCON_OCM)
+#define OCCON_RISING_EDGE (1 << _BN_OCCON_OCM)
+#define OCCON_MODE_OFF (0 << _BN_OCCON_OCM)
+
/* This structure defines the registers for a PIC32 A/D converter
*/
typedef struct {
View
43 hardware/pic32/cores/pic32/task_manager.c
@@ -1,6 +1,6 @@
/************************************************************************/
/* */
-/* periodic_task.c -- Periodic Task Management */
+/* task_manager.c -- Periodic Task Management */
/* */
/************************************************************************/
/* Author: Gene Apperson */
@@ -13,16 +13,31 @@
/* of the main execution loop. */
/* */
/************************************************************************/
+//* This module is free software; you can redistribute it and/or
+//* modify it under the terms of the GNU Lesser General Public
+//* License as published by the Free Software Foundation; either
+//* version 2.1 of the License, or (at your option) any later version.
+//*
+//* This library is distributed in the hope that it will be useful,
+//* but WITHOUT ANY WARRANTY; without even the implied warranty of
+//* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+//* Lesser General Public License for more details.
+//*
+//* You should have received a copy of the GNU Lesser General
+//* Public License along with this library; if not, write to the
+//* Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+//* Boston, MA 02111-1307 USA
+/************************************************************************/
/* Revision History: */
/* */
/* 12/08/2011(GeneApperson): Created */
/* 12/20/2011(GeneApperson): Modified to support multiple tasks using */
/* the same task function, and made the task var be a void * rather*/
/* than an unsigned short. */
+/* 02/06/2013(GeneApperson): Removed dependencies on Microchip plib */
/* */
/************************************************************************/
-
/* ------------------------------------------------------------ */
/* Include File Definitions */
/* ------------------------------------------------------------ */
@@ -105,11 +120,13 @@ createTask(taskFunc task, unsigned long period, unsigned short state, void * var
int idSet;
int idFree;
unsigned long tmsCur;
+ unsigned int st;
/* Search the table looking for an empty slot.
*/
+ st = disableInterrupts();
+ tmsCur = millis();
idSet = -1;
- noInterrupts();
for (id = 0; id < NUM_TASKS; id++) {
/* If this is the first vacant slot in the table.
*/
@@ -118,9 +135,6 @@ createTask(taskFunc task, unsigned long period, unsigned short state, void * var
break;
}
}
- interrupts();
-
- tmsCur = millis();
/* We should have the index of the appropriate slot in the table
** in idSet. If idSet == -1, then the table is full.
@@ -135,13 +149,14 @@ createTask(taskFunc task, unsigned long period, unsigned short state, void * var
rgtaskTable[idSet].stTask = state;
rgtaskTable[idSet].fsFlags = 0;
}
+ restoreInterrupts(st);
if (idSet != -1) {
/* Update our notion of when the next task event should occur.
*/
- noInterrupts();
+ st = disableInterrupts();
_updateTaskEvent(tmsCur);
- interrupts();
+ restoreInterrupts(st);
}
/* All done. Return the task id.
@@ -170,7 +185,8 @@ createTask(taskFunc task, unsigned long period, unsigned short state, void * var
void
destroyTask(int id) {
- int itask;
+ int itask;
+ unsigned int st;
/* Remove the specified task from the table.
*/
@@ -184,9 +200,9 @@ destroyTask(int id) {
/* Update when the next task event should occur.
*/
- noInterrupts();
+ st = disableInterrutps();
_updateTaskEvent(millis());
- interrupts();
+ restoreInterrupts(st);
return;
}
@@ -584,11 +600,12 @@ _scheduleTask() {
((tmsNxt < tmsLastEvent) &&
((tmsCur >= tmsNxt) && (tmsCur < tmsLastEvent))) ) {
- /* Update the event time for the next event on this task.
+ /* This task event has timed out. Update the event time for the
+ ** next event on this task.
*/
rgtaskTable[id].tmsNext += rgtaskTable[id].tmsPeriod;
- /* This task event has timed out. Call the event function.
+ /* Call the event function.
*/
rgtaskTable[id].fsFlags |= fsBusy;
(*rgtaskTable[id].pfnTask)(id, rgtaskTable[id].varTask);
View
69 hardware/pic32/cores/pic32/wiring.c
@@ -43,17 +43,18 @@
// Also fixed write_comp() inline assembler
// Also added countdown debug mask to stop the core timer when debugging.
//* Jun 1, 2012 <BPS> Added SoftReset() for software bootload
+// Feb 6, 2013 <GeneApperson> Removed dependencies on the Microchip plib library
//************************************************************************
-#include <plib.h>
+
#include <p32xxxx.h>
+#include <sys/attribs.h>
#define OPT_SYSTEM_INTERNAL
#define OPT_BOARD_INTERNAL //pull in internal symbol definitons
#include "pins_arduino.h"
#include "p32_defs.h"
#include "wiring_private.h"
-#include "peripheral/reset.h"
#undef _ENABLE_PIC_RTC_
@@ -118,25 +119,23 @@ unsigned long millis()
//************************************************************************
unsigned long micros()
{
-unsigned int cur_timer_val = 0;
-unsigned int micros_delta = 0;
+ uint32_t st;
+ unsigned int cur_timer_val = 0;
+ unsigned int micros_delta = 0;
unsigned int result;
- INTDisableInterrupts();
+ st = disableInterrupts();
result = gTimer0_millis * 1000;
cur_timer_val = ReadCoreTimer();
cur_timer_val -= gCore_timer_last_val;
cur_timer_val += CORETIMER_TICKS_PER_MICROSECOND/2; // rounding
cur_timer_val /= CORETIMER_TICKS_PER_MICROSECOND; // convert to microseconds
- INTEnableInterrupts();
+ restoreInterrupts(st);
return (result + cur_timer_val);
}
-//#define mCTClearIntFlag() (IFS0CLR = _IFS0_CTIF_MASK)
-//#define mCTGetIntFlag() (IFS0bits.CTIF)
-//#define GetSystemClock() (80000000ul)
//************************************************************************
// Delay for a given number of milliseconds.
void delay(unsigned long ms)
@@ -168,6 +167,7 @@ unsigned long startMicros = micros();
void init()
{
+#if defined(DEAD)
#ifdef _ENABLE_PIC_RTC_
// Configure the device for maximum performance but do not change the PBDIV
// Given the options, this function will change the flash wait states, RAM
@@ -177,30 +177,37 @@ void init()
#else
__PIC32_pbClk = SYSTEMConfigPerformance(F_CPU);
#endif
+#endif
+ // Configure the processor for the proper number of wait states and caching.
+ _configSystem(F_CPU);
- OpenCoreTimer(CORE_TICK_RATE);
+ // Enable multi-vector interrupts
+ _enableMultiVectorInterrupts();
- // set up the core timer interrupt with a prioirty of 2 and zero sub-priority
- mConfigIntCoreTimer(CT_INT_ON | _CT_IPL_IPC | (_CT_SPL_IPC << 4));
+ // Initialize the core timer for use to maintain the system timer tick.
+ _initCoreTimer(CORE_TICK_RATE);
+ setIntPriority(_CORE_TIMER_VECTOR, _CT_IPL_IPC, _CT_SPL_IPC);
+ setIntEnable(_CORE_TIMER_IRQ);
- // enable multi-vector interrupts
- INTEnableSystemMultiVectoredInt();
+ // Save the peripheral bus frequency for later use.
+ __PIC32_pbClk = getPeripheralClock();
+ // allow for debugging, this will stop the core timer when the debugger takes control
+ _CP0_BIC_DEBUG(_CP0_DEBUG_COUNTDM_MASK);
+#if defined(DEAD)
#ifdef _ENABLE_PIC_RTC_
RtccInit(); // init the RTCC
// while(RtccGetClkStat() != RTCC_CLK_ON); // wait for the SOSC to be actually running and RTCC to have its clock source
// could wait here at most 32ms
- // allow for debugging, this will stop the core timer when the debugger takes control
- _CP0_BIC_DEBUG(_CP0_DEBUG_COUNTDM_MASK);
-
// time is MSb: hour, min, sec, rsvd. date is MSb: year, mon, mday, wday.
RtccOpen(0x10073000, 0x11010901, 0);
RtccSetTimeDate(0x10073000, 0x10101701);
// please note that the rsvd field has to be 0 in the time field!
#endif
+#endif
delay(50);
@@ -323,31 +330,6 @@ boolean mapPps(uint8_t pin, ppsFunctionType func)
#endif // defined(__PIC32MX1XX__) || defined(__PIC32MX2XX__)
//************************************************************************
-//* Interrupts are enabled by setting the IE bit in the status register
-//************************************************************************
-unsigned int __attribute__((nomips16)) INTEnableInterrupts(void)
-{
- unsigned int status = 0;
-
- asm volatile("ei %0" : "=r"(status));
-
- return status;
-}
-
-
-//************************************************************************
-//* Interrupts are disabled by clearing the IE bit in the status register
-//************************************************************************
-unsigned int __attribute__((nomips16)) INTDisableInterrupts(void)
-{
- unsigned int status = 0;
-
- asm volatile("di %0" : "=r"(status));
-
- return status;
-}
-
-//************************************************************************
//* Deal with the 'virtual' program button and SoftReset(). This allows
//* a sketch to cause the board to reboot, and either force entry into
//* the bootloader, or not.
@@ -406,7 +388,7 @@ unsigned int executeSoftReset(uint32_t options)
RCONbits.EXTR = 0;
// Now perform the software reset
- SoftReset();
+ _softwareReset();
return(true); // never will be executed.
}
@@ -460,6 +442,7 @@ uint32_t millisecondCoreTimerService(uint32_t curTime);
#define write_comp(src) __asm__ __volatile__("mtc0 %0,$11" : : "r" (src))
#define mCTSetIntFlag() (IFS0SET = _IFS0_CTIF_MASK)
+#define mCTClearIntFlag() (IFS0CLR = _IFS0_CTIF_MASK)
typedef uint32_t (*CoreTimerService)(uint32_t);
View
39 hardware/pic32/cores/pic32/wiring.h
@@ -30,22 +30,20 @@
//* May ?, 2011 Brian Schmalz worked on micros timers
//* May 18, 2011 <MLS> Added prog_xxx defs because there is no "pgmspace.h" file for pic32
//* May 23, 2011 <MLS> Added definitions for PROGMEM, pgm_read_byte_near, pgm_read_byte_far
+//* Feb 6, 2012 <Gene Appeson> Added declarations for new functions in WSystem.c
//************************************************************************
#ifndef Wiring_h
#define Wiring_h
-#if defined(__AVR__)
- #include <avr/io.h>
-#elif defined(__PIC32MX__)
- #include "p32_defs.h"
-#endif
#include <inttypes.h>
#include "binary.h"
+#include <p32xxxx.h>
+#include "p32_defs.h"
#include "cpudefs.h" //* This file is designed to provide some of the cpu specific definitions
//* that are available for avr chips and not for other chips (i.e. pic32)
- //* It now contains PIC32 speciffic defines as well.
+ //* It now contains PIC32 specific defines as well.
#ifdef __cplusplus
extern "C"{
@@ -103,8 +101,8 @@ extern "C"{
#define degrees(rad) ((rad)*RAD_TO_DEG)
#define sq(x) ((x)*(x))
-#define interrupts() INTEnableInterrupts()
-#define noInterrupts() INTDisableInterrupts()
+#define interrupts() enableInterrupts()
+#define noInterrupts() disableInterrupts()
#define clockCyclesPerMicrosecond() ( F_CPU / 1000000L )
#define clockCyclesToMicroseconds(a) ( (a) / clockCyclesPerMicrosecond() )
@@ -144,8 +142,6 @@ int digitalRead(uint8_t pin);
int analogRead(uint8_t);
void analogReference(uint8_t mode);
void analogWrite(uint8_t, int);
-unsigned int __attribute__((nomips16)) INTEnableInterrupts(void);
-unsigned int __attribute__((nomips16)) INTDisableInterrupts(void);
unsigned long millis(void);
@@ -158,6 +154,22 @@ void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, byte val);
void attachInterrupt(uint8_t, void (*)(void), int mode);
void detachInterrupt(uint8_t);
+
+uint32_t __attribute__((nomips16)) enableInterrupts(void);
+uint32_t __attribute__((nomips16)) disableInterrupts(void);
+void __attribute__((nomips16)) restoreInterrupts(uint32_t st);
+uint32_t getIntFlag(int irq);
+void clearIntFlag(int irq);
+uint32_t setIntEnable(int irq);
+uint32_t clearIntEnable(int irq);
+void restoreIntEnable(int irq, uint32_t st);
+void setIntPriority(int vec, int ipl, int spl);
+void getIntPriority(int vec, int * pipl, int * pspl);
+uint32_t getPeripheralClock();
+uint32_t __attribute__((nomips16)) readCoreTimer(void);
+void __attribute__((nomips16)) writeCoreTimer(uint32_t tmr);
+
+
unsigned int executeSoftReset(uint32_t options);
unsigned int attachCoreTimerService(uint32_t (*)(uint32_t count));
@@ -253,9 +265,6 @@ void loop(void);
typedef void (* FNIMGJMP) (void);
-#pragma pack(push,2)
-
-
// The RAM Header is filled in by the bootloader, however it is specified by the sketch in the linker script
// The sketch must place it in the first 1.5K of RAM, as this is the space perserved by the bootloader for the sketch's
// Debug data, RAM Header, and persistent data. The bootloader will only fill in the RAM Header and will not touch
@@ -264,10 +273,12 @@ typedef void (* FNIMGJMP) (void);
// will not stray into its own data space, so the bootloader may not write all bytes specified by the sketch if that
// exceeds the 1.5K of reserved space. On return, cbBlHeader is the number of bytes written by the bootloader, any
// data beyond this not touched by the bootloader.
+#pragma pack(push,2)
typedef struct {
uint32_t cbBlRamHeader; // the number of bytes of this header as written by the bootloader
uint32_t rcon; // value of RCON before the bootloader clears it
} RAM_HEADER_INFO;
+#pragma pack(pop)
// The header is reserved by the sketch's linker script but
// written by both the sketch's linker script and by the bootloader.
@@ -277,6 +288,7 @@ typedef struct {
// all bootloader supplied values will be 0xFFFFFFFF; as this is the unprogramed value of flash.
// Check the MSB of the capabilities and if it is set, then none of the bootloader supplied values are valid.
// In all cases, a value of all FFs is reserved as unknown and should be checked before using.
+#pragma pack(push,2)
typedef struct {
uint32_t cbHeader; // length of this structure
uint32_t verBootloader; // version of the booloader that loaded the sketch, it will be 0xFFFFFFFF if the bootloader did not write the version.
@@ -296,7 +308,6 @@ typedef struct {
uint32_t cbRamHeader; // length of the ram header as specified by the linker and will be cleared/used by the bootloader
uint32_t cbBlPreservedRam; // the amount RAM the bootloader will not touch, 0xA0000000 -> 0xA0000000 + cbBlPerservedRam; Debug data, Ram Header and Persistent data must be in this section
} IMAGE_HEADER_INFO;
-
#pragma pack(pop)
extern const IMAGE_HEADER_INFO _image_header_info; // this is the header info right before .rodata, defined by the linker
View
84 hardware/pic32/cores/pic32/wiring_analog.c
@@ -40,18 +40,18 @@
//* Aug 7, 2011 <Gene Apperson> Added necessary code for analogReference (Issue #69)
//* Nov 12, 2011 <Gene Apperson> modified for board variant support
//* Jul 26, 2012 <GeneApperson> Added PPS support for PIC32MX1xx/MX2xx devices
+// Feb 6, 2013 <Gene Apperson> Removed dependencies on the Microchip plib library
//************************************************************************
-// Master header file for all peripheral library includes
-#include <plib.h>
+#include <p32xxxx.h>
#include "wiring_private.h"
#define OPT_BOARD_INTERNAL //pull in internal symbol definitons
-#include "pins_arduino.h"
#include "p32_defs.h"
+#include "pins_arduino.h"
-#define PWM_TIMER_PERIOD ((F_CPU / 256) / 490)
+#define PWM_TIMER_PERIOD ((__PIC32_pbClk / 256) / 490)
uint32_t analog_reference = 0; //default to AVDD, AVSS
@@ -135,7 +135,8 @@ int tmp;
** analog pin number. Map the input so that it is guaranteed to be
** an analog pin number.
*/
- if ((ain = digitalPinToAnalog(pin)) == NOT_ANALOG_PIN) {
+ ain = (pin < NUM_DIGITAL_PINS) ? digitalPinToAnalog(pin) : NOT_ANALOG_PIN;
+ if (ain == NOT_ANALOG_PIN) {
return 0;
}
@@ -252,7 +253,7 @@ int _board_analogWrite(uint8_t pin, int val);
/* Determine if this is actually a PWM capable pin or not.
** The value in timer will be the output compare number associated with
** the pin, or NOT_ON_TIMER if no OC is connected to the pin.
- ** The values 0 or >=255 have the side effect of turning off PWM on
+ ** The values 0 or >=255 have the side effect of turning off PWM on
** pins that are PWM capable.
*/
timer = digitalPinToTimerOC(pin) >> _BN_TIMER_OC;
@@ -266,36 +267,35 @@ int _board_analogWrite(uint8_t pin, int val);
** of turning off PWM on the pin if it happens to be a
** PWM capable pin.
*/
- pinMode(pin, OUTPUT);
-
- if (val < 128)
- {
- digitalWrite(pin, LOW);
- }
- else
- {
- digitalWrite(pin, HIGH);
- }
- }
+ pinMode(pin, OUTPUT);
+ if (val < 128)
+ {
+ digitalWrite(pin, LOW);
+ }
else
{
- /* It's a PWM capable pin. Timer 2 is used for the time base
+ digitalWrite(pin, HIGH);
+ }
+ }
+
+ else
+ {
+ /* It's a PWM capable pin. Timer 2 is used for the time base
** for analog output, so if no PWM are currently active then
** Timer 2 needs to be initialized
*/
- if (pwm_active == 0)
- {
- T2CON = T2_PS_1_256;
- TMR2 = 0;
- PR2 = PWM_TIMER_PERIOD;
- T2CONSET = T2_ON;
- }
+ if (pwm_active == 0)
+ {
+ T2CON = TBCON_PS_256;
+ TMR2 = 0;
+ PR2 = PWM_TIMER_PERIOD;
+ T2CONSET = TBCON_ON;
+ }
/* Generate bit mask for this output compare.
- ** We should assert(timer < 8) here, but assertions aren't being used
*/
- pwm_mask = (1 << (timer - (_TIMER_OC1 >> _BN_TIMER_OC)));
+ pwm_mask = (1 << (timer - (_TIMER_OC1 >> _BN_TIMER_OC)));
/* Obtain a pointer to the output compare being being used
** NOTE: as of 11/15/2011 All existing PIC32 devices
@@ -305,16 +305,12 @@ int _board_analogWrite(uint8_t pin, int val);
*/
ocp = (p32_oc *)(_OCMP1_BASE_ADDRESS + (0x200 * (timer - (_TIMER_OC1 >> _BN_TIMER_OC))));
- /* If the requested PWM isn't active, init its output compare. Enabling
+ /* If the requested PWM isn't active, init its output compare. Enabling
** the output compare takes over control of pin direction and forces the
** pin to be an output.
*/
- if ((pwm_active & pwm_mask) == 0)
- {
- /* The pin isn't currently being used to drive a PWM output. Make
- ** sure it's an output.
- */
- pinMode(pin, OUTPUT);
+ if ((pwm_active & pwm_mask) == 0)
+ {
#if defined(__PIC32MX1XX__) || defined(__PIC32MX2XX__)
volatile uint32_t * pps;
@@ -325,18 +321,18 @@ int _board_analogWrite(uint8_t pin, int val);
pps = ppsOutputRegister(timerOCtoDigitalPin(timer));
*pps = ppsOutputSelect(timerOCtoOutputSelect(timer));
#endif
- ocp->ocxR.reg = ((PWM_TIMER_PERIOD*val)/256);
- ocp->ocxCon.reg = OC_TIMER2_SRC | OC_PWM_FAULT_PIN_DISABLE;
- ocp->ocxCon.set = OC_ON;
+ ocp->ocxR.reg = ((PWM_TIMER_PERIOD*val)/256);
+ ocp->ocxCon.reg = OCCON_SRC_TIMER2 | OCCON_PWM_FAULT_DISABLE;
+ ocp->ocxCon.set = OCCON_ON;
- pwm_active |= pwm_mask;
- }
+ pwm_active |= pwm_mask;
+ }
- /* Set the duty cycle register for the requested output compare
+ /* Set the duty cycle register for the requested output compare
*/
- ocp->ocxRs.reg = ((PWM_TIMER_PERIOD*val)/256);
+ ocp->ocxRs.reg = ((PWM_TIMER_PERIOD*val)/256);
- }
+ }
}
@@ -348,14 +344,14 @@ void turnOffPWM(uint8_t timer)
/* Disable the output compare.
*/
ocp = (p32_oc *)(_OCMP1_BASE_ADDRESS + (0x200 * (timer - (_TIMER_OC1 >> _BN_TIMER_OC))));
- ocp->ocxCon.clr = OC_ON;
+ ocp->ocxCon.clr = OCCON_ON;
// Turn off the bit saying that this PWM is active.
pwm_active &= ~(1 << (timer - (_TIMER_OC1 >> _BN_TIMER_OC)));
// If no PWM are active, turn off the timer.
if (pwm_active == 0)
{
- T2CONCLR = T2_ON;
+ T2CONCLR = TBCON_ON;
}
}
View
2 hardware/pic32/cores/pic32/wiring_digital.c
@@ -39,9 +39,9 @@
#define OPT_BOARD_INTERNAL //pull in internal symbol definitons
#include <p32xxxx.h>
+#include "p32_defs.h"
#include "wiring_private.h"
#include "pins_arduino.h"
-#include "p32_defs.h"
//************************************************************************
void pinMode(uint8_t pin, uint8_t mode)
View
5 hardware/pic32/cores/pic32/wiring_private.h
@@ -78,6 +78,11 @@
void turnOffPWM(uint8_t timer);
+ void _configSystem(uint32_t clk);
+ void _enableMultiVectorInterrupts();
+ void _initCoreTimer(uint32_t prd);
+ void __attribute__((noreturn)) _softwareReset(void);
+
typedef void (*voidFuncPtr)(void);
#ifdef __cplusplus
View
31 hardware/pic32/libraries/EEPROM/utility/Deeprom.c
@@ -6,13 +6,30 @@
/* Author: Oliver Jones */
/* Copyright 2011, Digilent Inc. */
/************************************************************************/
+/*
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+/************************************************************************/
/* Module Description: */
/* */
/* */
/************************************************************************/
/* Revision History: */
/* */
-/* 09/01/2011(OliverJ): created */
+/* 09/01/2011(OliverJ): created */
+/* 02/06/2013(GeneA): removed dependencies on Microchip plib library */
/* */
/************************************************************************/
@@ -23,13 +40,13 @@
#include <p32xxxx.h>
#include <stdint.h>
-#include <peripheral/nvm.h>
#include <alloca.h>
#define OPT_BOARD_INTERNAL
#include <pins_arduino.h>
#include "Deeprom.h"
+#include "flash.h"
/* ------------------------------------------------------------ */
/* Global Variables */
@@ -112,7 +129,7 @@ void clearEeprom()
//Clear page
for(i=0; i < _EEPROM_PAGE_COUNT; i++) {
- NVMErasePage(&eedata_addr[i][0]);
+ eraseFlashPage(&eedata_addr[i][0]);
}
}
@@ -153,7 +170,7 @@ BOOL writeEeprom(uint32_t address, uint8_t data)
putBuffer(&eedata_addr[i][0], tempBuffer);
//Clear page
- NVMErasePage(&eedata_addr[i][0]);
+ eraseFlashPage(&eedata_addr[i][0]);
//Put buffer back to page
getBuffer(&eedata_addr[i][0], tempBuffer);
@@ -249,7 +266,7 @@ BOOL putEeprom(eeSeg * eeprom, uint32_t address, uint8_t data)
else {
tempSeg = eeprom[i];
tempSeg.temp.valid = 0;
- NVMWriteWord((void*)&eeprom[i],tempSeg.data);
+ writeFlashWord((void*)&eeprom[i],tempSeg.data);
// If data is 0xFF return
if(data == 0xFF) {
@@ -271,7 +288,7 @@ BOOL putEeprom(eeSeg * eeprom, uint32_t address, uint8_t data)
//Pack address with data and write to flash
tempSeg = pack(address,data);
- NVMWriteWord((void*)&eeprom[i],tempSeg.data);
+ writeFlashWord((void*)&eeprom[i],tempSeg.data);
return fTrue;
}
@@ -389,7 +406,7 @@ void getBuffer(eeSeg * eeprom, uint8_t * buffer)
if(buffer[i] != 0xFF) {
tempData = buffer[i];
tempSeg = pack(i, tempData);
- NVMWriteWord((void*)&eeprom[i],tempSeg.data);
+ writeFlashWord((void*)&eeprom[i],tempSeg.data);
}
}
}
View
16 hardware/pic32/libraries/EEPROM/utility/Deeprom.h
@@ -6,6 +6,22 @@
/* Author: Oliver Jones */
/* Copyright 2011, Digilent Inc. */
/************************************************************************/
+/*
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+/************************************************************************/
/* Module Description: */
/* */
/* */
View
246 hardware/pic32/libraries/EEPROM/utility/flash.c
@@ -0,0 +1,246 @@
+/********************************************************************************/
+/* */
+/* flash.c -- Flash Memory Operation Functions */
+/* */
+/********************************************************************************/
+/* Author: Gene Apperson */
+/* Copyright 2012, Digilent Inc. */
+/********************************************************************************/
+//*
+//* This library is free software; you can redistribute it and/or
+//* modify it under the terms of the GNU Lesser General Public
+//* License as published by the Free Software Foundation; either
+//* version 2.1 of the License, or (at your option) any later version.
+//*
+//* This library is distributed in the hope that it will be useful,
+//* but WITHOUT ANY WARRANTY; without even the implied warranty of
+//* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.//* See the GNU
+//* Lesser General Public License for more details.
+//*
+//* You should have received a copy of the GNU Lesser General
+//* Public License along with this library; if not, write to the
+//* Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+//* Boston, MA 02111-1307 USA
+//*
+/********************************************************************************/
+/* Module Description: */
+/* */
+/* */
+/********************************************************************************/
+/* Revision History: */
+/* */
+/* 08/27/2012 <Gene Apperson> Created */
+/* */
+/********************************************************************************/
+
+
+/* ------------------------------------------------------------ */
+/* Include File Definitions */
+/* ------------------------------------------------------------ */
+
+#include <p32xxxx.h>
+#include <stdint.h>
+#include <sys/kmem.h>
+#include "flash.h"
+
+/* ------------------------------------------------------------ */
+/* Local Type Definitions */
+/* ------------------------------------------------------------ */
+
+
+/* ------------------------------------------------------------ */
+/* Global Variables */
+/* ------------------------------------------------------------ */
+
+
+/* ------------------------------------------------------------ */
+/* Local Variables */
+/* ------------------------------------------------------------ */
+
+
+/* ------------------------------------------------------------ */
+/* Forward Declarations */
+/* ------------------------------------------------------------ */
+
+
+/* ------------------------------------------------------------ */
+/* Procedure Definitions */
+/* ------------------------------------------------------------ */
+/*** eraseFlashPage
+**
+** Parameters:
+** adr - memory address of page to erase
+**
+** Return Value:
+** Returns status code
+**
+** Errors:
+** Returns zero if operation succeeds, non-zero if not.
+**
+** Description:
+** This function will erase the flash memory page specified
+** by adr.
+*/
+
+uint32_t eraseFlashPage(void * adr)
+{
+ uint32_t st;
+
+ /* Convert the given address into a physical address
+ */
+ NVMADDR = KVA_TO_PA((unsigned int) adr);
+
+ /* Perform the erase operation.
+ */
+ st = _doNvmOp(nvmopErasePage);
+
+ return st;
+
+}
+
+/* ------------------------------------------------------------ */
+/*** writeFlashWord
+**
+** Parameters:
+** adr - word address
+** val - word value
+**
+** Return Value:
+** Returns status of operation
+**
+** Errors:
+** Returns 0 if successful, non-zero if not
+**
+** Description:
+** Write the specified word to the flash memory at the specified
+** address.
+*/
+
+uint32_t writeFlashWord(void * adr, uint32_t val)
+{
+ uint32_t st;
+
+ /* Convert the given address into a physical address
+ */
+ NVMADDR = KVA_TO_PA((unsigned int) adr);
+
+ /* Place the data in the NVM data register in preparation
+ ** for writing.
+ */
+ NVMDATA = val;
+
+ /* Perform the write operation.
+ */
+ st = _doNvmOp(nvmopWriteWord);
+
+ return st;
+}
+
+/* ------------------------------------------------------------ */
+/*** clearNvmError
+**
+** Parameters:
+** none
+**
+** Return Value:
+** Returns error status
+**
+** Errors:
+** Returns 0 if successful, non-zero if error
+**
+** Description:
+** Clear the error status in the NVM controller.
+*/
+
+uint32_t clearNvmError()
+{
+
+ return _doNvmOp(nvmopNop);
+
+}
+
+/* ------------------------------------------------------------ */
+/*** _doNvmOp
+**
+** Parameters:
+** nvmop - NVM operation to perform
+**
+** Return Value:
+** Returns status code
+**
+** Errors:
+** Returns 0 if success, non-zero if not
+**
+** Description:
+** This function performs an operation on the flash memory.
+*/
+
+uint32_t __attribute__((nomips16)) _doNvmOp(uint32_t nvmop)
+{
+ int nvmSt;
+ int intSt;
+ uint32_t tm;
+
+
+ // M00TODO: When DMA operations are suppored in the core, need
+ // to add code here to suspend DMA during the NVM operation.
+
+ intSt = disableInterrupts();
+
+ /* Store the operation code into the NVMCON register.
+ */
+ NVMCON = NVMCON_WREN | nvmop;
+
+ /* We need to wait at least 6uS before performing the operation.
+ ** We can use the core timer to determine elapsed time based on
+ ** the CPU operating frequency.
+ */
+ {
+ tm = _CP0_GET_COUNT();
+ while (_CP0_GET_COUNT() - tm < ((F_CPU * 6) / 2000000));
+ }
+
+ /* Unlock so that we can perform the operation.
+ */
+ NVMKEY = 0xAA996655;
+ NVMKEY = 0x556699AA;
+ NVMCONSET = NVMCON_WR;
+
+ /* Wait for WR bit to clear indicating that the operation has completed.
+ */
+ while (NVMCON & NVMCON_WR)
+ {
+ ;
+ }
+
+ /* Clear the write enable bit in NVMCON to lock the flash again.
+ */
+ NVMCONCLR = NVMCON_WREN;
+
+ //M00TODO: Resume a suspended DMA operation
+
+ restoreInterrupts(intSt);
+
+ /* Return the success state of the operation.
+ */
+ return(isNvmError());
+
+}
+
+/* ------------------------------------------------------------ */
+/*** ProcName
+**
+** Parameters:
+**
+** Return Value:
+**
+** Errors:
+**
+** Description:
+**
+*/
+
+/* ------------------------------------------------------------ */
+
+/************************************************************************/
+
View
78 hardware/pic32/libraries/EEPROM/utility/flash.h
@@ -0,0 +1,78 @@
+/********************************************************************************/
+/* */
+/* flash.h -- Interface for Flash Memory Operations Functions */
+/* */
+/********************************************************************************/
+/* Author: Gene Apperson */
+/* Copyright 2012, Digilent Inc. */
+/********************************************************************************/
+//*
+//* This library is free software; you can redistribute it and/or
+//* modify it under the terms of the GNU Lesser General Public
+//* License as published by the Free Software Foundation; either
+//* version 2.1 of the License, or (at your option) any later version.
+//*
+//* This library is distributed in the hope that it will be useful,
+//* but WITHOUT ANY WARRANTY; without even the implied warranty of
+//* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.//* See the GNU
+//* Lesser General Public License for more details.
+//*
+//* You should have received a copy of the GNU Lesser General
+//* Public License along with this library; if not, write to the
+//* Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+//* Boston, MA 02111-1307 USA
+//*
+/********************************************************************************/
+/* File Description: */
+/* */
+/* */
+/********************************************************************************/
+/* Revision History: */
+/* */
+/* 08/27/2012 <Gene Apperson> Created */
+/* */
+/********************************************************************************/
+
+
+/* ------------------------------------------------------------ */
+/* Miscellaneous Declarations */
+/* ------------------------------------------------------------ */
+
+
+
+/* ------------------------------------------------------------ */
+/* General Type Declarations */
+/* ------------------------------------------------------------ */
+
+/* NVM operation codes.
+*/
+#define nvmopNop 0x4000
+#define nvmopWriteWord 0x4001
+#define nvmopErasePage 0x4004
+
+#define isNvmError() (NVMCON & (_NVMCON_WRERR_MASK | _NVMCON_LVDERR_MASK))
+
+/* ------------------------------------------------------------ */
+/* Object Class Declarations */
+/* ------------------------------------------------------------ */
+
+
+
+/* ------------------------------------------------------------ */
+/* Variable Declarations */
+/* ------------------------------------------------------------ */
+
+
+
+/* ------------------------------------------------------------ */
+/* Procedure Declarations */
+/* ------------------------------------------------------------ */
+
+uint32_t eraseFlashPage (void * adr);
+uint32_t writeFlashWord(void * adr, uint32_t val);
+uint32_t clearNvmError();
+uint32_t __attribute__((nomips16)) _doNvmOp(uint32_t nvmop);
+
+/* ------------------------------------------------------------ */
+
+/************************************************************************/
View
62 hardware/pic32/libraries/SD/utility/Sd2Card.cpp
@@ -18,13 +18,26 @@
* along with the Arduino Sd2Card Library. If not, see
* <http://www.gnu.org/licenses/>.
*/
+//* ***************************************************************************
+//* Revision History:
+//* Feb 7, 2013 <Gene Apperson> Changed bit-banged SPI code to remove dependency
+//* on the Microchip plib library.
#include <p32xxxx.h>
-#include <plib.h>
-
#include <WProgram.h>
#include "Sd2Card.h"
+/* The following are used for direct access to the processor pins
+** for the bit-banged SPI implementation.
+*/
+#define bitSDO (1 << BN_SDO)
+#define bitSDI (1 << BN_SDI)
+#define bitSCK (1 << BN_SCK)
+
+p32_ioport * iopSDO = (p32_ioport *)&IOPORT_SDO;
+p32_ioport * iopSDI = (p32_ioport *)&IOPORT_SDI;
+p32_ioport * iopSCK = (p32_ioport *)&IOPORT_SCK;
+
/* SPIxCON
*/
#define bnOn 15
@@ -50,21 +63,28 @@ uint32_t interrupt_state = 0;
uint8_t spiRec(void) {
uint8_t data = 0;
// output pin high - like sending 0XFF
- PORTSetBits(prtSDO, bnSDO);
+ //PORTSetBits(prtSDO, bnSDO);
+ iopSDO->lat.set = bitSDO;
for (uint8_t i = 0; i < 8; i++) {
- PORTSetBits(prtSCK, bnSCK);
+ //PORTSetBits(prtSCK, bnSCK);
+ iopSCK->lat.set = bitSCK;
data <<= 1;
// adjust so SCK is nice
asm("nop");
asm("nop");
- if (PORTReadBits(prtSDI,bnSDI)) data |= 1;
+ //if (PORTReadBits(prtSDI,bnSDI)) data |= 1;
+ if ((iopSDI->port.reg & bitSDI) != 0)
+ {
+ data |= 1;
+ }
- PORTClearBits(prtSCK, bnSCK);
+ //PORTClearBits(prtSCK, bnSCK);
+ iopSCK->lat.clr = bitSCK;
}
return data;
@@ -76,22 +96,26 @@ void spiSend(uint8_t data) {
for (uint8_t i = 0; i < 8; i++) {
if(data & 0X80) {
- PORTSetBits(prtSDO, bnSDO);
+ //PORTSetBits(prtSDO, bnSDO);
+ iopSDO->lat.set = bitSDO;
}
else
{
- PORTClearBits(prtSDO, bnSDO);
+ //PORTClearBits(prtSDO, bnSDO);
+ iopSDO->lat.clr = bitSDO;
}
- PORTClearBits(prtSCK, bnSCK);
+ //PORTClearBits(prtSCK, bnSCK);
+ iopSCK->lat.clr = bitSCK;
asm("nop");
asm("nop");
asm("nop");
data <<= 1;
- PORTSetBits(prtSCK, bnSCK);
+ //PORTSetBits(prtSCK, bnSCK);
+ iopSCK->lat.set = bitSCK;
}
// hold SCK high for a few ns
@@ -100,7 +124,8 @@ void spiSend(uint8_t data) {
asm("nop");
asm("nop");
- PORTClearBits(prtSCK, bnSCK);
+ //PORTClearBits(prtSCK, bnSCK);
+ iopSCK->lat.clr = bitSCK;
}
//------------------------------------------------------------------------------
// send command and return error code. Return zero for OK
@@ -164,7 +189,7 @@ void Sd2Card::chipSelectHigh(void) {
{
SPI2CON = spi_state;
fspi_state_saved = false;
- INTRestoreInterrupts(interrupt_state);
+ restoreInterrupts(interrupt_state);
}
#endif
}
@@ -173,7 +198,7 @@ void Sd2Card::chipSelectLow(void) {
#if defined(_BOARD_MEGA_) || defined(_BOARD_UNO_) || defined(_BOARD_UC32_)
if(!fspi_state_saved)
{
- interrupt_state = INTDisableInterrupts();
+ interrupt_state = disableInterrupts();
spi_state = SPI2CON;
SPI2CONbits.ON = 0;
fspi_state_saved = true;
@@ -259,10 +284,13 @@ uint8_t Sd2Card::init(uint8_t sckRateID, uint8_t chipSelectPin) {
pinMode(chipSelectPin_, OUTPUT);
- PORTSetPinsDigitalOut(prtSCK, bnSCK);
- PORTSetPinsDigitalOut(prtSDO, bnSDO);
- PORTSetPinsDigitalIn(prtSDI, bnSDI);
-
+ //PORTSetPinsDigitalOut(prtSCK, bnSCK);
+ //PORTSetPinsDigitalOut(prtSDO, bnSDO);
+ //PORTSetPinsDigitalIn(prtSDI, bnSDI);
+ iopSCK->tris.clr = bitSCK;
+ iopSDO->tris.clr = bitSDO;
+ iopSDI->tris.set = bitSDI;
+
// set pin modes
chipSelectHigh();
View
128 hardware/pic32/libraries/SD/utility/Sd2PinMap.h
@@ -19,118 +19,102 @@
* <http://www.gnu.org/licenses/>.
*/
// Warning this file was generated by a program.
+//* ***************************************************************************
+//* Revision History:
+//* Aug 23, 2012 <Gene Apperson> Changed pin definitions for bit-banged SPI code
+//* to remove dependency on the Microchip plib library.
#ifndef Sd2PinMap_h
#define Sd2PinMap_h
#if defined(_BOARD_MEGA_) || defined(_BOARD_UNO_) || defined(_BOARD_UC32_)
//Pin 11
- #define prtSDO IOPORT_G
- #define trisSDO TRISG
- #define latSDO LATG
- #define bnSDO BIT_8
+ #define IOPORT_SDO TRISG
+ #define BN_SDO 8