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Missing the new files added to the repos from Keith for Interupt Vect…

…ors.

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1 parent 3eecd82 commit d41f80b02a9eb59110469b53bb7da2f7afb62ff3 @ricklon ricklon committed Jul 2, 2013
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102 hardware/pic32/cores/pic32/vector_table.S
@@ -0,0 +1,102 @@
+#include <p32xxxx.h>
+#include <System_Defs.h>
+
+.extern _isr_primary_install
+
+.globl __use_isr_install
+__use_isr_install:
+
+#if (__C32_VERSION__ < 200)
+# define USE_OLD_DOTSECTION
+#endif
+
+#ifdef USE_OLD_DOTSECTION
+# define CODE_SECTION(name) .section name, "ax", @progbits
+#else
+# define CODE_SECTION(name) .section name, code
+#endif
+#define VECTOR_SYMBOLNAME(number) __vector_ ## number
+#define VECTOR_SECTIONNAME(number) .vector_new_ ## number
+
+#define NEWLINE_MACRO \n
+
+#define VECTOR_ENTRY(number) \
+ .globl VECTOR_SYMBOLNAME(number); \
+ CODE_SECTION(VECTOR_SECTIONNAME(number)); \
+ .align 2; \
+ .set nomips16; \
+ .set nomicromips; \
+ .ent VECTOR_SYMBOLNAME(number); \
+ .type VECTOR_SYMBOLNAME(number), @function; \
+ VECTOR_SYMBOLNAME(number):;\
+ lui k0,%hi(_isr_primary_install); \
+ addiu k0,k0,%lo(_isr_primary_install); \
+ lw k0,4 * number (k0); \
+ jr k0; \
+ .end VECTOR_SYMBOLNAME(number); \
+ .size VECTOR_SYMBOLNAME(number), .-VECTOR_SYMBOLNAME(number);
+
+ VECTOR_ENTRY(0)
+ VECTOR_ENTRY(1)
+ VECTOR_ENTRY(2)
+ VECTOR_ENTRY(3)
+ VECTOR_ENTRY(4)
+ VECTOR_ENTRY(5)
+ VECTOR_ENTRY(6)
+ VECTOR_ENTRY(7)
+ VECTOR_ENTRY(8)
+ VECTOR_ENTRY(9)
+ VECTOR_ENTRY(10)
+ VECTOR_ENTRY(11)
+ VECTOR_ENTRY(12)
+ VECTOR_ENTRY(13)
+ VECTOR_ENTRY(14)
+ VECTOR_ENTRY(15)
+ VECTOR_ENTRY(16)
+ VECTOR_ENTRY(17)
+ VECTOR_ENTRY(18)
+ VECTOR_ENTRY(19)
+ VECTOR_ENTRY(20)
+ VECTOR_ENTRY(21)
+ VECTOR_ENTRY(22)
+ VECTOR_ENTRY(23)
+ VECTOR_ENTRY(24)
+ VECTOR_ENTRY(25)
+ VECTOR_ENTRY(26)
+ VECTOR_ENTRY(27)
+ VECTOR_ENTRY(28)
+ VECTOR_ENTRY(29)
+ VECTOR_ENTRY(30)
+ VECTOR_ENTRY(31)
+ VECTOR_ENTRY(32)
+ VECTOR_ENTRY(33)
+ VECTOR_ENTRY(34)
+ VECTOR_ENTRY(35)
+ VECTOR_ENTRY(36)
+ VECTOR_ENTRY(37)
+ VECTOR_ENTRY(38)
+ VECTOR_ENTRY(39)
+ VECTOR_ENTRY(40)
+ VECTOR_ENTRY(41)
+ VECTOR_ENTRY(42)
+ VECTOR_ENTRY(43)
+ VECTOR_ENTRY(44)
+ VECTOR_ENTRY(45)
+ VECTOR_ENTRY(46)
+ VECTOR_ENTRY(47)
+ VECTOR_ENTRY(48)
+ VECTOR_ENTRY(49)
+ VECTOR_ENTRY(50)
+ VECTOR_ENTRY(51)
+ VECTOR_ENTRY(52)
+ VECTOR_ENTRY(53)
+ VECTOR_ENTRY(54)
+ VECTOR_ENTRY(55)
+ VECTOR_ENTRY(56)
+ VECTOR_ENTRY(57)
+ VECTOR_ENTRY(58)
+ VECTOR_ENTRY(59)
+ VECTOR_ENTRY(60)
+ VECTOR_ENTRY(61)
+ VECTOR_ENTRY(62)
+ VECTOR_ENTRY(63)
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729 hardware/pic32/variants/Cmod/Board_Data.c
@@ -0,0 +1,729 @@
+/************************************************************************/
+/* */
+/* Board_Data.c -- Cmod Customization Data Declarations */
+/* */
+/************************************************************************/
+/* Author: Gene Apperson */
+/* Copyright 2011, Digilent. All rights reserved */
+/************************************************************************/
+/* File Description: */
+/* */
+/* This file contains the board specific declartions and data structure */
+/* to customize the chipKIT MPIDE for use with a CmodCK1 board using a */
+/* PIC32 part in a 44-pin package. */
+/* */
+/* This code is based on earlier work: */
+/* Copyright (c) 2010, 2011 by Mark Sproul */
+/* Copyright (c) 2005, 2006 by David A. Mellis */
+/* */
+/************************************************************************/
+/* Revision History: */
+/* */
+/* 11/28/2011(GeneA): Created by splitting data out of Board_Defs.h */
+/* 01/23/2013(KeithV): Modified for CK1 board */
+/* */
+/************************************************************************/
+//* This library is free software; you can redistribute it and/or
+//* modify it under the terms of the GNU Lesser General Public
+//* License as published by the Free Software Foundation; either
+//* version 2.1 of the License, or (at your option) any later version.
+//*
+//* This library is distributed in the hope that it will be useful,
+//* but WITHOUT ANY WARRANTY; without even the implied warranty of
+//* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+//* Lesser General Public License for more details.
+//*
+//* You should have received a copy of the GNU Lesser General
+//* Public License along with this library; if not, write to the
+//* Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+//* Boston, MA 02111-1307 USA
+/************************************************************************/
+
+#if !defined(BOARD_DATA_C)
+#define BOARD_DATA_C
+
+#include <inttypes.h>
+
+/* ------------------------------------------------------------ */
+/* Data Tables */
+/* ------------------------------------------------------------ */
+/* The following declarations define data used in pin mapping. */
+/* ------------------------------------------------------------ */
+
+#if defined(OPT_BOARD_DATA)
+
+/* ------------------------------------------------------------ */
+/* This table is used to map from port number to the address of
+** the TRIS register for the port. This is used for setting the
+** pin direction.
+*/
+const uint32_t port_to_tris_PGM[] = {
+ NOT_A_PORT, //index value 0 is not used
+
+#if defined(_PORTA)
+ (uint32_t)&TRISA,
+#else
+ NOT_A_PORT,
+#endif
+
+#if defined(_PORTB)
+ (uint32_t)&TRISB,
+#else
+ NOT_A_PORT,
+#endif
+
+#if defined(_PORTC)
+ (uint32_t)&TRISC,
+#else
+ NOT_A_PORT,
+#endif
+
+#if defined(_PORTD)
+ (uint32_t)&TRISD,
+#else
+ NOT_A_PORT,
+#endif
+
+#if defined(_PORTE)
+ (uint32_t)&TRISE,
+#else
+ NOT_A_PORT,
+#endif
+
+#if defined(_PORTF)
+ (uint32_t)&TRISF,
+#else
+ NOT_A_PORT,
+#endif
+
+#if defined(_PORTG)
+ (uint32_t)&TRISG,
+#else
+ NOT_A_PORT,
+#endif
+
+ NOT_A_PORT,
+};
+
+/* ------------------------------------------------------------ */
+/* This table is used to map the digital pin number to the port
+** containing that pin. The default mapping is to assign pin numbers
+** for every possible port bit in order from PORTA to PORTG.
+*/
+const uint8_t digital_pin_to_port_PGM[] = {
+ // Pins 0 through 38
+ NOT_A_PIN, // 0
+ NOT_A_PIN, // 1
+ NOT_A_PIN, // 2
+ NOT_A_PIN, // 3
+ _IOPORT_PB, // 4 RB9 RPB9/SDA1/CTED4/PMD3/RB9
+ _IOPORT_PC, // 5 RC6 RPC6/PMA1/RC6
+ _IOPORT_PC, // 6 RC7 RPC7/PMA0/RC7
+ _IOPORT_PC, // 7 RC8 RPC8/PMA5/RC8
+ _IOPORT_PC, // 8 RC9 RPC9/CTED7/PMA6/RC9
+ NOT_A_PIN, // 9
+ _IOPORT_PB, // 10 RB10 PGED2/RPB10/CTED11/PMD2/RB10
+ _IOPORT_PB, // 11 RB11 PGEC2/RPB11/PMD1/RB11
+ _IOPORT_PB, // 12 RB12 AN12/PMD0/RB12
+ _IOPORT_PB, // 13 RB13 AN11/RPB13/CTPLS/PMRD/RB13
+ _IOPORT_PA, // 14 RA10 PGED(4)/TMS/PMA10/RA10
+ _IOPORT_PA, // 15 RA7 PGEC(4)/TCK/CTED8/PMA7/RA7
+ _IOPORT_PB, // 16 RB14 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
+ _IOPORT_PB, // 17 RB15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
+ _IOPORT_PA, // 18 RA0 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
+ _IOPORT_PA, // 19 RA1 VREF-/CVREF-/AN1/RPA1/CTED2/RA1
+ _IOPORT_PB, // 20 RB0 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
+ _IOPORT_PB, // 21 RB1 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
+ _IOPORT_PB, // 22 RB2 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
+ _IOPORT_PB, // 23 RB3 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
+ _IOPORT_PC, // 24 RC0 AN6/RPC0/RC0
+ _IOPORT_PC, // 25 RC1 AN7/RPC1/RC1
+ _IOPORT_PC, // 26 RC2 AN8/RPC2/PMA2/RC2
+ _IOPORT_PA, // 27 RA8 TDO/RPA8/PMA8/RA8
+ NOT_A_PIN, // 28
+ _IOPORT_PB, // 29 RB4 SOSCI/RPB4/RB4
+ _IOPORT_PA, // 30 RA4 SOSCO/RPA4/T1CK/CTED9/RA4
+ _IOPORT_PA, // 31 RA9 TDI/RPA9/PMA9/RA9
+ _IOPORT_PC, // 32 RC3 RPC3/RC3
+ _IOPORT_PC, // 33 RC4 RPC4/PMA4/RC4
+ _IOPORT_PC, // 34 RC5 RPC5/PMA3/RC5
+ _IOPORT_PB, // 35 RB5 PGED3/RPB5/PMD7/RB5
+ _IOPORT_PB, // 36 RB6 PGEC3/RPB6/PMD6/RB6
+ _IOPORT_PB, // 37 RB7 RPB7/CTED3/PMD5/INT0/RB7
+ _IOPORT_PB, // 38 RB8 RPB8/SCL1/CTED10/PMD4/RB8
+};
+
+/* ------------------------------------------------------------ */
+/* This table is used to map from digital pin number to a bit mask
+** for the corresponding bit within the port.
+*/
+const uint16_t digital_pin_to_bit_mask_PGM[] = {
+ // Pins 0 through 38
+ NOT_A_PIN, // 0
+ NOT_A_PIN, // 1
+ NOT_A_PIN, // 2
+ NOT_A_PIN, // 3
+ _BV( 9 ) , // 4 RB9 RPB9/SDA1/CTED4/PMD3/RB9
+ _BV( 6 ) , // 5 RC6 RPC6/PMA1/RC6
+ _BV( 7 ), // 6 RC7 RPC7/PMA0/RC7
+ _BV( 8 ), // 7 RC8 RPC8/PMA5/RC8
+ _BV( 9 ) , // 8 RC9 RPC9/CTED7/PMA6/RC9
+ NOT_A_PIN, // 9
+ _BV( 10 ) , // 10 RB10 PGED2/RPB10/CTED11/PMD2/RB10
+ _BV( 11 ) , // 11 RB11 PGEC2/RPB11/PMD1/RB11
+ _BV( 12 ), // 12 RB12 AN12/PMD0/RB12
+ _BV( 13 ), // 13 RB13 AN11/RPB13/CTPLS/PMRD/RB13
+ _BV( 10 ) , // 14 RA10 PGED(4)/TMS/PMA10/RA10
+ _BV( 7 ) , // 15 RA7 PGEC(4)/TCK/CTED8/PMA7/RA7
+ _BV( 14 ) , // 16 RB14 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
+ _BV( 15 ) , // 17 RB15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
+ _BV( 0 ) , // 18 RA0 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
+ _BV( 1 ) , // 19 RA1 VREF-/CVREF-/AN1/RPA1/CTED2/RA1
+ _BV( 0 ) , // 20 RB0 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
+ _BV( 1 ) , // 21 RB1 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
+ _BV( 2 ) , // 22 RB2 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
+ _BV( 3 ) , // 23 RB3 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
+ _BV( 0 ) , // 24 RC0 AN6/RPC0/RC0
+ _BV( 1 ) , // 25 RC1 AN7/RPC1/RC1
+ _BV( 2 ) , // 26 RC2 AN8/RPC2/PMA2/RC2
+ _BV( 8 ) , // 27 RA8 TDO/RPA8/PMA8/RA8
+ NOT_A_PIN, // 28
+ _BV( 4 ) , // 29 RB4 SOSCI/RPB4/RB4
+ _BV( 4 ) , // 30 RA4 SOSCO/RPA4/T1CK/CTED9/RA4
+ _BV( 9 ) , // 31 RA9 TDI/RPA9/PMA9/RA9
+ _BV( 3 ) , // 32 RC3 RPC3/RC3
+ _BV( 4 ) , // 33 RC4 RPC4/PMA4/RC4
+ _BV( 5 ) , // 34 RC5 RPC5/PMA3/RC5
+ _BV( 5 ) , // 35 RB5 PGED3/RPB5/PMD7/RB5
+ _BV( 6 ) , // 36 RB6 PGEC3/RPB6/PMD6/RB6
+ _BV( 7 ) , // 37 RB7 RPB7/CTED3/PMD5/INT0/RB7
+ _BV( 8 ) , // 38 RB8 RPB8/SCL1/CTED10/PMD4/RB8
+};
+
+/* ------------------------------------------------------------ */
+/* This table is used to map from digital pin number to the output
+** compare number, input capture number, and timer external clock
+** input associated with that pin.
+*/
+const uint8_t digital_pin_to_timer_PGM[] = {
+ // Pins 0 through 38
+ NOT_A_PIN, // 0
+ NOT_A_PIN, // 1
+ NOT_A_PIN, // 2
+ NOT_A_PIN, // 3
+ _TIMER_OC3, // 4 RB9 RPB9/SDA1/CTED4/PMD3/RB9
+ NOT_ON_TIMER, // 5 RC6 RPC6/PMA1/RC6
+ NOT_ON_TIMER, // 6 RC7 RPC7/PMA0/RC7
+ NOT_ON_TIMER, // 7 RC8 RPC8/PMA5/RC8
+ NOT_ON_TIMER, // 8 RC9 RPC9/CTED7/PMA6/RC9
+ NOT_A_PIN, // 9
+ _TIMER_IC2, // 10 RB10 PGED2/RPB10/CTED11/PMD2/RB10
+ NOT_ON_TIMER, // 11 RB11 PGEC2/RPB11/PMD1/RB11
+ NOT_ON_TIMER, // 12 RB12 AN12/PMD0/RB12
+ _TIMER_OC5, // 13 RB13 AN11/RPB13/CTPLS/PMRD/RB13
+ NOT_ON_TIMER, // 14 RA10 PGED(4)/TMS/PMA10/RA10
+ NOT_ON_TIMER, // 15 RA7 PGEC(4)/TCK/CTED8/PMA7/RA7
+ NOT_ON_TIMER, // 16 RB14 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
+ NOT_ON_TIMER, // 17 RB15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
+ _TIMER_TCK2, // 18 RA0 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
+ NOT_ON_TIMER, // 19 RA1 VREF-/CVREF-/AN1/RPA1/CTED2/RA1
+ NOT_ON_TIMER, // 20 RB0 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
+ NOT_ON_TIMER, // 21 RB1 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
+ _TIMER_OC4, // 22 RB2 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
+ NOT_ON_TIMER, // 23 RB3 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
+ NOT_ON_TIMER, // 24 RC0 AN6/RPC0/RC0
+ _TIMER_IC5, // 25 RC1 AN7/RPC1/RC1
+ _TIMER_TCK5, // 26 RC2 AN8/RPC2/PMA2/RC2
+ _TIMER_TCK3, // 27 RA8 TDO/RPA8/PMA8/RA8
+ NOT_A_PIN, // 28
+ _TIMER_OC1 , // 29 RB4 SOSCI/RPB4/RB4
+ _TIMER_TCK1, // 30 RA4 SOSCO/RPA4/T1CK/CTED9/RA4
+ _TIMER_IC3, // 31 RA9 TDI/RPA9/PMA9/RA9
+ _TIMER_TCK4, // 32 RC3 RPC3/RC3
+ NOT_ON_TIMER, // 33 RC4 RPC4/PMA4/RC4
+ NOT_ON_TIMER, // 34 RC5 RPC5/PMA3/RC5
+ NOT_ON_TIMER, // 35 RB5 PGED3/RPB5/PMD7/RB5
+ _TIMER_IC1, // 36 RB6 PGEC3/RPB6/PMD6/RB6
+ _TIMER_IC4, // 37 RB7 RPB7/CTED3/PMD5/INT0/RB7
+ _TIMER_OC2, // 38 RB8 RPB8/SCL1/CTED10/PMD4/RB8
+};
+
+/* ------------------------------------------------------------ */
+/* This table maps from a digital pin number to the corresponding
+** PPS register. This register is used to select the peripheral output
+** connected to the pin. The register is set to 0 to disconnedt the
+** pin from any peripheral so it can be used as GPIO.
+** For PIC32MX1xx/2xx series devices, the PPS output select registers
+** are arranged as a contiguous series of 32 bit registers. This table
+** treats these registers as an array of DWORDs an stores the index
+** to the register.
+*/
+const uint8_t digital_pin_to_pps_out_PGM[] = {
+ // Pins 0 through 38
+ NOT_A_PIN, // 0
+ NOT_A_PIN, // 1
+ NOT_A_PIN, // 2
+ NOT_A_PIN, // 3
+ _PPS_OUT(_PPS_RPB9R), // 4 RB9 RPB9/SDA1/CTED4/PMD3/RB9
+ _PPS_OUT(_PPS_RPC6R), // 5 RC6 RPC6/PMA1/RC6
+ _PPS_OUT(_PPS_RPC7R), // 6 RC7 RPC7/PMA0/RC7
+ _PPS_OUT(_PPS_RPC8R), // 7 RC8 RPC8/PMA5/RC8
+ _PPS_OUT(_PPS_RPC9R), // 8 RC9 RPC9/CTED7/PMA6/RC9
+ NOT_A_PIN, // 9
+ _PPS_OUT(_PPS_RPB10R), // 10 RB10 PGED2/RPB10/CTED11/PMD2/RB10
+ _PPS_OUT(_PPS_RPB11R), // 11 RB11 PGEC2/RPB11/PMD1/RB11
+ NOT_PPS_PIN, // 12 RB12 AN12/PMD0/RB12
+ _PPS_OUT(_PPS_RPB13R), // 13 RB13 AN11/RPB13/CTPLS/PMRD/RB13
+ NOT_PPS_PIN, // 14 RA10 PGED(4)/TMS/PMA10/RA10
+ NOT_PPS_PIN, // 15 RA7 PGEC(4)/TCK/CTED8/PMA7/RA7
+ _PPS_OUT(_PPS_RPB14R), // 16 RB14 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
+ _PPS_OUT(_PPS_RPB15R), // 17 RB15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
+ _PPS_OUT(_PPS_RPA0R), // 18 RA0 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
+ _PPS_OUT(_PPS_RPA1R), // 19 RA1 VREF-/CVREF-/AN1/RPA1/CTED2/RA1
+ _PPS_OUT(_PPS_RPB0R), // 20 RB0 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
+ _PPS_OUT(_PPS_RPB1R), // 21 RB1 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
+ _PPS_OUT(_PPS_RPB2R), // 22 RB2 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
+ _PPS_OUT(_PPS_RPB3R), // 23 RB3 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
+ _PPS_OUT(_PPS_RPC0R), // 24 RC0 AN6/RPC0/RC0
+ _PPS_OUT(_PPS_RPC1R), // 25 RC1 AN7/RPC1/RC1
+ _PPS_OUT(_PPS_RPC2R), // 26 RC2 AN8/RPC2/PMA2/RC2
+ _PPS_OUT(_PPS_RPA8R), // 27 RA8 TDO/RPA8/PMA8/RA8
+ NOT_A_PIN, // 28
+ _PPS_OUT(_PPS_RPB4R), // 29 RB4 SOSCI/RPB4/RB4
+ _PPS_OUT(_PPS_RPA4R), // 30 RA4 SOSCO/RPA4/T1CK/CTED9/RA4
+ _PPS_OUT(_PPS_RPA9R), // 31 RA9 TDI/RPA9/PMA9/RA9
+ _PPS_OUT(_PPS_RPC3R), // 32 RC3 RPC3/RC3
+ _PPS_OUT(_PPS_RPC4R), // 33 RC4 RPC4/PMA4/RC4
+ _PPS_OUT(_PPS_RPC5R), // 34 RC5 RPC5/PMA3/RC5
+ _PPS_OUT(_PPS_RPB5R), // 35 RB5 PGED3/RPB5/PMD7/RB5
+ _PPS_OUT(_PPS_RPB6R), // 36 RB6 PGEC3/RPB6/PMD6/RB6
+ _PPS_OUT(_PPS_RPB7R), // 37 RB7 RPB7/CTED3/PMD5/INT0/RB7
+ _PPS_OUT(_PPS_RPB8R), // 38 RB8 RPB8/SCL1/CTED10/PMD4/RB8
+};
+
+/* ------------------------------------------------------------ */
+/* This table maps from the digital pin number to the value to be
+** loaded into a PPS input select register to select that pin.
+** It also maps from digital pin number to input/output pin set to
+** which the pin belongs. The set mask is in the high four bits,
+** the select value is in the low four bits.
+** Note: if the PIC32 device has more than four pin sets, or more than
+** 16 pin mapping choices per input function, then this table will have
+** to be redefined as a table of uint16_t values and the macros used to
+** access the table redefined as well.
+*/
+const uint8_t digital_pin_to_pps_in_PGM[] = {
+ // Pins 0 through 38
+ NOT_A_PIN, // 0
+ NOT_A_PIN, // 1
+ NOT_A_PIN, // 2
+ NOT_A_PIN, // 3
+ _PPS_IN(_PPS_RPB9), // 4 RB9 RPB9/SDA1/CTED4/PMD3/RB9
+ _PPS_IN(_PPS_RPC6), // 5 RC6 RPC6/PMA1/RC6
+ _PPS_IN(_PPS_RPC7), // 6 RC7 RPC7/PMA0/RC7
+ _PPS_IN(_PPS_RPC8), // 7 RC8 RPC8/PMA5/RC8
+ _PPS_IN(_PPS_RPC9), // 8 RC9 RPC9/CTED7/PMA6/RC9
+ NOT_A_PIN, // 9
+ _PPS_IN(_PPS_RPB10), // 10 RB10 PGED2/RPB10/CTED11/PMD2/RB10
+ _PPS_IN(_PPS_RPB11), // 11 RB11 PGEC2/RPB11/PMD1/RB11
+ NOT_PPS_PIN, // 12 RB12 AN12/PMD0/RB12
+ _PPS_IN(_PPS_RPB13), // 13 RB13 AN11/RPB13/CTPLS/PMRD/RB13
+ NOT_PPS_PIN, // 14 RA10 PGED(4)/TMS/PMA10/RA10
+ NOT_PPS_PIN, // 15 RA7 PGEC(4)/TCK/CTED8/PMA7/RA7
+ _PPS_IN(_PPS_RPB14), // 16 RB14 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
+ _PPS_IN(_PPS_RPB15), // 17 RB15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
+ _PPS_IN(_PPS_RPA0), // 18 RA0 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
+ _PPS_IN(_PPS_RPA1), // 19 RA1 VREF-/CVREF-/AN1/RPA1/CTED2/RA1
+ _PPS_IN(_PPS_RPB0), // 20 RB0 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
+ _PPS_IN(_PPS_RPB1), // 21 RB1 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
+ _PPS_IN(_PPS_RPB2), // 22 RB2 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
+ _PPS_IN(_PPS_RPB3), // 23 RB3 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
+ _PPS_IN(_PPS_RPC0), // 24 RC0 AN6/RPC0/RC0
+ _PPS_IN(_PPS_RPC1), // 25 RC1 AN7/RPC1/RC1
+ _PPS_IN(_PPS_RPC2), // 26 RC2 AN8/RPC2/PMA2/RC2
+ _PPS_IN(_PPS_RPA8), // 27 RA8 TDO/RPA8/PMA8/RA8
+ NOT_A_PIN, // 28
+ _PPS_IN(_PPS_RPB4), // 29 RB4 SOSCI/RPB4/RB4
+ _PPS_IN(_PPS_RPA4), // 30 RA4 SOSCO/RPA4/T1CK/CTED9/RA4
+ _PPS_IN(_PPS_RPA9), // 31 RA9 TDI/RPA9/PMA9/RA9
+ _PPS_IN(_PPS_RPC3), // 32 RC3 RPC3/RC3
+ _PPS_IN(_PPS_RPC4), // 33 RC4 RPC4/PMA4/RC4
+ _PPS_IN(_PPS_RPC5), // 34 RC5 RPC5/PMA3/RC5
+ _PPS_IN(_PPS_RPB5), // 35 RB5 PGED3/RPB5/PMD7/RB5
+ _PPS_IN(_PPS_RPB6), // 36 RB6 PGEC3/RPB6/PMD6/RB6
+ _PPS_IN(_PPS_RPB7), // 37 RB7 RPB7/CTED3/PMD5/INT0/RB7
+ _PPS_IN(_PPS_RPB8), // 38 RB8 RPB8/SCL1/CTED10/PMD4/RB8
+};
+
+/* ------------------------------------------------------------ */
+/* This table maps from a digital pin number to the corresponding
+** analog pin number.
+*/
+//#if defined(_NOT_USED_)
+const uint8_t digital_pin_to_analog_PGM[] = {
+ // Pins 0 through 38
+ NOT_A_PIN, // 0
+ NOT_A_PIN, // 1
+ NOT_A_PIN, // 2
+ NOT_A_PIN, // 3
+ NOT_ANALOG_PIN, // 4 RB9 RPB9/SDA1/CTED4/PMD3/RB9
+ NOT_ANALOG_PIN, // 5 RC6 RPC6/PMA1/RC6
+ NOT_ANALOG_PIN, // 6 RC7 RPC7/PMA0/RC7
+ NOT_ANALOG_PIN, // 7 RC8 RPC8/PMA5/RC8
+ NOT_ANALOG_PIN, // 8 RC9 RPC9/CTED7/PMA6/RC9
+ NOT_A_PIN, // 9
+ NOT_ANALOG_PIN, // 10 RB10 PGED2/RPB10/CTED11/PMD2/RB10
+ NOT_ANALOG_PIN, // 11 RB11 PGEC2/RPB11/PMD1/RB11
+ _BOARD_AN12, // 12 RB12 AN12/PMD0/RB12
+ _BOARD_AN11, // 13 RB13 AN11/RPB13/CTPLS/PMRD/RB13
+ NOT_ANALOG_PIN, // 14 RA10 PGED(4)/TMS/PMA10/RA10
+ NOT_ANALOG_PIN, // 15 RA7 PGEC(4)/TCK/CTED8/PMA7/RA7
+ _BOARD_AN10, // 16 RB14 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
+ _BOARD_AN9, // 17 RB15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
+ _BOARD_AN0, // 18 RA0 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
+ _BOARD_AN1, // 19 RA1 VREF-/CVREF-/AN1/RPA1/CTED2/RA1
+ _BOARD_AN2, // 20 RB0 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
+ _BOARD_AN3, // 21 RB1 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
+ _BOARD_AN4, // 22 RB2 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
+ _BOARD_AN5, // 23 RB3 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
+ _BOARD_AN6, // 24 RC0 AN6/RPC0/RC0
+ _BOARD_AN7, // 25 RC1 AN7/RPC1/RC1
+ _BOARD_AN8, // 26 RC2 AN8/RPC2/PMA2/RC2
+ NOT_ANALOG_PIN, // 27 RA8 TDO/RPA8/PMA8/RA8
+ NOT_A_PIN, // 28
+ NOT_ANALOG_PIN, // 29 RB4 SOSCI/RPB4/RB4
+ NOT_ANALOG_PIN, // 30 RA4 SOSCO/RPA4/T1CK/CTED9/RA4
+ NOT_ANALOG_PIN, // 31 RA9 TDI/RPA9/PMA9/RA9
+ NOT_ANALOG_PIN, // 32 RC3 RPC3/RC3
+ NOT_ANALOG_PIN, // 33 RC4 RPC4/PMA4/RC4
+ NOT_ANALOG_PIN, // 34 RC5 RPC5/PMA3/RC5
+ NOT_ANALOG_PIN, // 35 RB5 PGED3/RPB5/PMD7/RB5
+ NOT_ANALOG_PIN, // 36 RB6 PGEC3/RPB6/PMD6/RB6
+ NOT_ANALOG_PIN, // 37 RB7 RPB7/CTED3/PMD5/INT0/RB7
+ NOT_ANALOG_PIN, // 38 RB8 RPB8/SCL1/CTED10/PMD4/RB8
+};
+//#endif
+
+/* ------------------------------------------------------------ */
+/* This table is used to map from the analog pin number to the
+** actual A/D converter channel used for that pin.
+** In the default case, where there is a one-to-one mapping, this
+** table isn't needed as the analogInPinToChannel() macro is defined
+** to provide the mapping.
+*/
+//#if defined(_NOT_USED_)
+const uint8_t analog_pin_to_channel_PGM[] = {
+ //* Arduino Pin PIC32 Analog channel
+ 0, //* A0 1 to 1 mapping
+ 1, //* A1
+ 2, //* A2
+ 3, //* A3
+ 4, //* A4
+ 5, //* A5
+ 6, //* A6
+ 7, //* A7
+ 8, //* A8
+ 9, //* A9
+ 10, //* A10
+ 11, //* A11
+ 12, //* A12
+};
+//#endif
+
+/* ------------------------------------------------------------ */
+/* This table maps from an output compare number as stored in the
+** digital_pin_to_timer_PGM table to the digital pin number of the
+** pin that OC is connected to. This table is only required for
+** devices that support peripheral pin select (PPS), i.e. PIC32MX1xx/2xx
+** devices.
+*/
+
+const uint8_t output_compare_to_digital_pin_PGM[] = {
+ PIN_OC1, // RPB4 (RPB4R = 5)
+ PIN_OC2, // RPB8 (RPB8R = 5)
+ PIN_OC3, // RPB9 (RPB9R = 5)
+ PIN_OC4, // RPB2 (RPB2R = 5)
+ PIN_OC5, // RPB13(RPB13R = 6)
+};
+
+/* ------------------------------------------------------------ */
+/* This table maps from an external interrupt number to the digital
+** pin for that interrupt.
+*/
+
+const uint8_t external_int_to_digital_pin_PGM[] = {
+ NOT_PPS_PIN, // INT0 is not mappable; RB7
+ PIN_INT1, // RPC4 J2-07, RC4 used for UART2 INT (INT1R = 7)
+ PIN_INT2, // RPB13 (INT2R = 3)
+ PIN_INT3, // RPC8 J1-07, RC8 used for SPI1 INT (INT3R = 6)
+ PIN_INT4 // RPB7 (INT4R = 4)
+};
+
+/* ------------------------------------------------------------ */
+/* Include Files for Board Customization Functions */
+/* ------------------------------------------------------------ */
+#if (OPT_BOARD_INIT != 0)
+#include <plib.h>
+#endif
+
+/* ------------------------------------------------------------ */
+/* Board Customization Functions */
+/* ------------------------------------------------------------ */
+/* */
+/* The following can be used to customize the behavior of some */
+/* of the core API functions. These provide hooks that can be */
+/* used to extend or replace the default behavior of the core */
+/* functions. To use one of these functions, add the desired */
+/* code to the function skeleton below and then set the value */
+/* of the appropriate compile switch above to 1. This will */
+/* cause the hook function to be compiled into the build and */
+/* to cause the code to call the hook function to be compiled */
+/* into the appropriate core function. */
+/* */
+/* ------------------------------------------------------------ */
+/*** _board_init
+**
+** Parameters:
+** none
+**
+** Return Value:
+** none
+**
+** Errors:
+** none
+**
+** Description:
+** This function is called from the core init() function.
+** This can be used to perform any board specific init
+** that needs to be done when the processor comes out of
+** reset and before the user sketch is run.
+*/
+#if (OPT_BOARD_INIT != 0)
+
+void _board_init(void) {
+
+}
+
+#endif
+
+/* ------------------------------------------------------------ */
+/*** _board_pinMode
+**
+** Parameters:
+** pin - digital pin number to configure
+** mode - mode to which the pin should be configured
+**
+** Return Value:
+** Returns 0 if not handled, !0 if handled.
+**
+** Errors:
+** none
+**
+** Description:
+** This function is called at the beginning of the pinMode
+** function. It can perform any special processing needed
+** when setting the pin mode. If this function returns zero,
+** control will pass through the normal pinMode code. If
+** it returns a non-zero value the normal pinMode code isn't
+** executed.
+*/
+#if (OPT_BOARD_DIGITAL_IO != 0)
+
+int _board_pinMode(uint8_t pin, uint8_t mode) {
+
+ return 0;
+
+}
+
+#endif
+
+/* ------------------------------------------------------------ */
+/*** _board_getPinMode
+**
+** Parameters:
+** pin - digital pin number
+** mode - pointer to variable to receive mode value
+**
+** Return Value:
+** Returns 0 if not handled, !0 if handled.
+**
+** Errors:
+** none
+**
+** Description:
+** This function is called at the beginning of the getPinMode
+** function. It can perform any special processing needed
+** when getting the pin mode. If this function returns zero,
+** control will pass through the normal getPinMode code. If
+** it returns a non-zero value the normal getPinMode code isn't
+** executed.
+*/
+#if (OPT_BOARD_DIGITAL_IO != 0)
+
+int _board_getPinMode(uint8_t pin, uint8_t * mode) {
+
+ return 0;
+
+}
+
+#endif
+
+/* ------------------------------------------------------------ */
+/*** _board_digitalWrite
+**
+** Parameters:
+** pin - digital pin number
+** val - value to write to the pin
+**
+** Return Value:
+** Returns 0 if not handled, !0 if handled.
+**
+** Errors:
+** none
+**
+** Description:
+** This function is called at the beginning of the digitalWrite
+** function. It can perform any special processing needed
+** in writing to the pin. If this function returns zero,
+** control will pass through the normal digitalWrite code. If
+** it returns a non-zero value the normal digitalWrite code isn't
+** executed.
+*/#if (OPT_BOARD_DIGITAL_IO != 0)
+
+int _board_digitalWrite(uint8_t pin, uint8_t val) {
+
+ return 0;
+
+}
+
+#endif
+
+/* ------------------------------------------------------------ */
+/*** _board_digitalRead
+**
+** Parameters:
+** pin - digital pin number
+** val - pointer to variable to receive pin value
+**
+** Return Value:
+** Returns 0 if not handled, !0 if handled.
+**
+** Errors:
+** none
+**
+** Description:
+** This function is called at the beginning of the digitalRead
+** function. It can perform any special processing needed
+** in reading from the pin. If this function returns zero,
+** control will pass through the normal digitalRead code. If
+** it returns a non-zero value the normal digitalRead code isn't
+** executed.
+*/
+#if (OPT_BOARD_DIGITAL_IO != 0)
+
+int _board_digitalRead(uint8_t pin, uint8_t * val) {
+
+ return 0;
+
+}
+
+#endif
+
+/* ------------------------------------------------------------ */
+/*** _board_analogRead
+**
+** Parameters:
+** pin - analog channel number
+** val - pointer to variable to receive analog value
+**
+** Return Value:
+** Returns 0 if not handled, !0 if handled.
+**
+** Errors:
+** none
+**
+** Description:
+** This function is called at the beginning of the analogRead
+** function. It can perform any special processing needed
+** in reading from the pin. If this function returns zero,
+** control will pass through the normal analogRead code. If
+** it returns a non-zero value the normal analogRead code isn't
+** executed.
+*/
+#if (OPT_BOARD_ANALOG_READ != 0)
+
+int _board_analogRead(uint8_t pin, int * val) {
+
+ return 0;
+
+}
+
+#endif
+
+/* ------------------------------------------------------------ */
+/*** _board_analogReference
+**
+** Parameters:
+**
+** Return Value:
+** Returns 0 if not handled, !0 if handled.
+**
+** Errors:
+** none
+**
+** Description:
+** This function is called at the beginning of the analogReference
+** function. It can perform any special processing needed
+** to set the reference voltage. If this function returns zero,
+** control will pass through the normal analogReference code. If
+** it returns a non-zero value the normal analogReference code isn't
+** executed.
+*/
+#if (OPT_BOARD_ANALOG_READ != 0)
+
+int _board_analogReference(uint8_t mode) {
+
+ return 0;
+
+}
+
+#endif
+
+/* ------------------------------------------------------------ */
+/*** _board_analogWrite
+**
+** Parameters:
+** pin - pin number
+** val - analog value to write
+**
+** Return Value:
+** Returns 0 if not handled, !0 if handled.
+**
+** Errors:
+** none
+**
+** Description:
+** This function is called at the beginning of the analogWrite
+** function. It can perform any special processing needed
+** in writing to the pin. If this function returns zero,
+** control will pass through the normal analogWrite code. If
+** it returns a non-zero value the normal analogWrite code isn't
+** executed.
+*/
+#if (OPT_BOARD_ANALOG_WRITE != 0)
+
+int _board_analogWrite(uint8_t pin, int val) {
+
+ return 0;
+
+}
+
+#endif
+
+#endif // OPT_BOARD_DATA
+
+/* ------------------------------------------------------------ */
+
+#endif // BOARD_DATA_C
+
+/************************************************************************/
View
447 hardware/pic32/variants/Cmod/Board_Defs.h
@@ -0,0 +1,447 @@
+/************************************************************************/
+/* */
+/* Board_Defs.h -- CmodCK1 Board Customization Declarations */
+/* */
+/************************************************************************/
+/* Author: Gene Apperson */
+/* Copyright 2011, Digilent. All rights reserved */
+/************************************************************************/
+/* File Description: */
+/* */
+/* This file contains the board specific declartions and data structure */
+/* to customize the chipKIT MPIDE for use with a CmodCK1 board using a */
+/* PIC32 part in a 44-pin package. */
+/* */
+/* This code is based on earlier work: */
+/* Copyright (c) 2010, 2011 by Mark Sproul */
+/* Copyright (c) 2005, 2006 by David A. Mellis */
+/* */
+/************************************************************************/
+/* Revision History: */
+/* */
+/* 10/07/2011(GeneA): Created */
+/* 11/28/2011(GeneA): Moved data definitions and configuration */
+/* functions to Board_Data.c */
+/* 11/29/2011(GeneA): Moved int priority definitions to System_Defs.h */
+/* 01/23/2013(KeithV): Modified for CK1 board */
+/* */
+/************************************************************************/
+//* This library is free software; you can redistribute it and/or
+//* modify it under the terms of the GNU Lesser General Public
+//* License as published by the Free Software Foundation; either
+//* version 2.1 of the License, or (at your option) any later version.
+//*
+//* This library is distributed in the hope that it will be useful,
+//* but WITHOUT ANY WARRANTY; without even the implied warranty of
+//* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+//* Lesser General Public License for more details.
+//*
+//* You should have received a copy of the GNU Lesser General
+//* Public License along with this library; if not, write to the
+//* Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+//* Boston, MA 02111-1307 USA
+/************************************************************************/
+
+#if !defined(BOARD_DEFS_H)
+#define BOARD_DEFS_H
+
+#include <inttypes.h>
+
+/* ------------------------------------------------------------ */
+/* Public Board Declarations */
+/* ------------------------------------------------------------ */
+/* The following define symbols that can be used in a sketch to
+** refer to periperhals on the board generically.
+*/
+
+#define _BOARD_NAME_ "chipKIT Cmod"
+
+/* Define the peripherals available on the board.
+*/
+#define NUM_DIGITAL_PINS 39
+#define NUM_ANALOG_PINS 13
+#define NUM_OC_PINS 5
+#define NUM_IC_PINS 5
+#define NUM_TCK_PINS 5
+#define NUM_INT_PINS 5
+
+#define NUM_SERIAL_PORTS 2 // see comment on serial Port 2 below
+#define NUM_SPI_PORTS 2
+#define NUM_I2C_PORTS 1
+
+#define NUM_DSPI_PORTS 2
+#define NUM_DTWI_PORTS 1
+
+/* Define I/O devices on the board.
+*/
+#define NUM_LED 2
+#define NUM_BTN 0
+#define NUM_SWT 0
+#define NUM_SERVO 0
+
+/* ------------------------------------------------------------ */
+/* LED Declarations */
+/* ------------------------------------------------------------ */
+
+/* Define the pin numbers for the LEDs
+*/
+#define PIN_LED1 14 // 14 RA10 PGED(4)/TMS/PMA10/RA10
+#define PIN_LED2 12 // 12 RB12 AN12/PMD0/RB12
+
+/* ------------------------------------------------------------ */
+/* Button Declarations */
+/* ------------------------------------------------------------ */
+
+/* One button (PRG) for this board
+*/
+///#define PIN_BTN1 1
+/* Also define the virutal program button for soft reset */
+#define USE_VIRTUAL_PROGRAM_BUTTON 1
+#define VIRTUAL_PROGRAM_BUTTON_TRIS TRISAbits.TRISA2
+#define VIRTUAL_PROGRAM_BUTTON LATAbits.LATA2
+
+/* ------------------------------------------------------------ */
+/* Switch Declarations */
+/* ------------------------------------------------------------ */
+
+/* No switches on this board.
+*/
+
+/* ------------------------------------------------------------ */
+/* Servo Pin Declarations */
+/* ------------------------------------------------------------ */
+
+/* No servo connectors on this board.
+*/
+
+/* ------------------------------------------------------------ */
+/* Timer Pin Declarations */
+/* ------------------------------------------------------------ */
+
+#define PIN_OC1 29 // RPB4 (RPB4R = 5)
+#define PIN_OC2 38 // RPB8 (RPB8R = 5)
+#define PIN_OC3 4 // RPB9 (RPB9R = 5)
+#define PIN_OC4 22 // RPB2 (RPB2R = 5)
+#define PIN_OC5 13 // RPB13(RPB13R = 6)
+
+#define PIN_IC1 36 // RPB6 (IC1R = 1)
+#define PIN_IC2 10 // RPB10 (IC2R = 3)
+#define PIN_IC3 31 // RPA9 (IC3R = 7)
+#define PIN_IC4 37 // RPB7 (IC4R = 4)
+#define PIN_IC5 25 // RPC1 (RPC1R = 6)
+
+#define PIN_TCK1 30 // RA4
+#define PIN_TCK2 18 // RPA0 (T1CKR = 0)
+#define PIN_TCK3 27 // RPA8 (T1CKR = 5)
+#define PIN_TCK4 32 // RPC3 (T1CKR = 7)
+#define PIN_TCK5 26 // RPC2 (T1CKR = 6)
+
+/* ------------------------------------------------------------ */
+/* Interrupt Pin Declarations */
+/* ------------------------------------------------------------ */
+
+#define PIN_INT0 37 // RB7 RB7 fixed not a pps pin
+#define PIN_INT1 33 // RPC4 J2-07, RC4 used for UART2 INT (INT1R = 7)
+#define PIN_INT2 13 // RPB13 (INT2R = 3)
+#define PIN_INT3 7 // RPC8 J1-07, RC8 used for SPI1 INT (INT3R = 6)
+#define PIN_INT4 37 // RPB7 (INT4R = 4)
+
+/* ------------------------------------------------------------ */
+/* SPI Pin Declarations */
+/* ------------------------------------------------------------ */
+/* These symbols are defined for compatibility with the original
+** SPI library and the original pins_arduino.h.
+*/
+const static uint8_t SS = 24; // CS1 RC0 SS1R = 6, RPC0R = 3 24 RC0 AN6/RPC0/RC0
+const static uint8_t MISO = 35; // SDI1 RB5 SDI1R = 1 35 RB5 PGED3/RPB5/PMD7/RB5
+const static uint8_t MOSI = 25; // SDO1 RC1 RPC1R = 3 25 RC1 AN7/RPC1/RC1
+const static uint8_t SCK = 16; // SCK1 RB14 RPB14R = 0 16 RB14 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
+
+/* The Digilent DSPI library uses these ports.
+*/
+#define PIN_DSPI0_SS 24 // 24 RC0 AN6/RPC0/RC0
+#define PIN_DSPI1_SS 33 // 33 RC4 RPC4/PMA4/RC4
+
+/* ------------------------------------------------------------ */
+/* Analog Pins */
+/* ------------------------------------------------------------ */
+/* Define symbols for accessing the analog pins. This table is
+** used to map an analog pin number to the corresponding digital
+** pin number.
+*/
+#define A0 18 // RA0 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
+#define A1 19 // RA1 VREF-/CVREF-/AN1/RPA1/CTED2/RA1
+#define A2 20 // RB0 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
+#define A3 21 // RB1 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
+#define A4 22 // RB2 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
+#define A5 23 // RB3 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
+#define A6 24 // RC0 AN6/RPC0/RC0
+#define A7 25 // RC1 AN7/RPC1/RC1
+#define A8 26 // RC2 AN8/RPC2/PMA2/RC2
+#define A9 17 // RB15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
+#define A10 16 // RB14 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
+#define A11 13 // RB13 AN11/RPB13/CTPLS/PMRD/RB13
+#define A12 12 // RB12 AN12/PMD0/RB12
+
+/* ------------------------------------------------------------ */
+/* Change Notice Pins */
+/* ------------------------------------------------------------ */
+/* These define the pin numbers for the various change notice
+** pins.
+*/
+
+//#define PIN_CN0 0 // 0
+//#define PIN_CN1 1 // 1
+//#define PIN_CN2 2 // 2
+//#define PIN_CN3 3 // 3
+#define PIN_CN4 4 // 4 RB9 RPB9/SDA1/CTED4/PMD3/RB9
+#define PIN_CN5 5 // 5 RC6 RPC6/PMA1/RC6
+#define PIN_CN6 6 // 6 RC7 RPC7/PMA0/RC7
+#define PIN_CN7 7 // 7 RC8 RPC8/PMA5/RC8
+#define PIN_CN8 8 // 8 RC9 RPC9/CTED7/PMA6/RC9
+//#define PIN_CN9 9 // 9
+#define PIN_CN10 10 // 10 RB10 PGED2/RPB10/CTED11/PMD2/RB10
+#define PIN_CN11 11 // 11 RB11 PGEC2/RPB11/PMD1/RB11
+#define PIN_CN12 12 // 12 RB12 AN12/PMD0/RB12
+#define PIN_CN13 13 // 13 RB13 AN11/RPB13/CTPLS/PMRD/RB13
+#define PIN_CN14 14 // 14 RA10 PGED(4)/TMS/PMA10/RA10
+#define PIN_CN15 15 // 15 RA7 PGEC(4)/TCK/CTED8/PMA7/RA7
+#define PIN_CN16 16 // 16 RB14 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
+#define PIN_CN17 17 // 17 RB15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
+#define PIN_CN18 18 // 18 RA0 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
+#define PIN_CN19 19 // 19 RA1 VREF-/CVREF-/AN1/RPA1/CTED2/RA1
+#define PIN_CN20 20 // 20 RB0 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
+#define PIN_CN21 21 // 21 RB1 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
+#define PIN_CN22 22 // 22 RB2 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
+#define PIN_CN23 23 // 23 RB3 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
+#define PIN_CN24 24 // 24 RC0 AN6/RPC0/RC0
+#define PIN_CN25 25 // 25 RC1 AN7/RPC1/RC1
+#define PIN_CN26 26 // 26 RC2 AN8/RPC2/PMA2/RC2
+#define PIN_CN27 27 // 27 RA8 TDO/RPA8/PMA8/RA8
+//#define PIN_CN28 28 // 28
+#define PIN_CN29 29 // 29 RB4 SOSCI/RPB4/RB4
+#define PIN_CN30 30 // 30 RA4 SOSCO/RPA4/T1CK/CTED9/RA4
+#define PIN_CN31 31 // 31 RA9 TDI/RPA9/PMA9/RA9
+#define PIN_CN32 32 // 32 RC3 RPC3/RC3
+#define PIN_CN33 33 // 33 RC4 RPC4/PMA4/RC4
+#define PIN_CN34 34 // 34 RC5 RPC5/PMA3/RC5
+#define PIN_CN35 35 // 35 RB5 PGED3/RPB5/PMD7/RB5
+#define PIN_CN36 36 // 36 RB6 PGEC3/RPB6/PMD6/RB6
+#define PIN_CN37 37 // 37 RB7 RPB7/CTED3/PMD5/INT0/RB7
+#define PIN_CN38 38 // 38 RB8 RPB8/SCL1/CTED10/PMD4/RB8
+
+/* ------------------------------------------------------------ */
+/* Pin Mapping Macros */
+/* ------------------------------------------------------------ */
+/* Macros used to access the port and pin mapping tables.
+** These are mostly generic, but some of them may be board specific.
+** These perform slightly better as macros compared to inline functions
+*/
+#undef digitalPinToAnalog
+#define digitalPinToAnalog(P) ( digital_pin_to_analog_PGM[P] )
+
+#undef analogInPinToChannel
+#define analogInPinToChannel(P) ( analog_pin_to_channel_PGM[P] )
+
+/* ------------------------------------------------------------ */
+/* Data Definitions */
+/* ------------------------------------------------------------ */
+
+/* The following declare externals to access the pin mapping
+** tables. These tables are defined in Board_Data.c.
+*/
+
+#if !defined(OPT_BOARD_DATA)
+
+extern const uint32_t port_to_tris_PGM[];
+extern const uint8_t digital_pin_to_port_PGM[];
+extern const uint16_t digital_pin_to_bit_mask_PGM[];
+extern const uint16_t digital_pin_to_timer_PGM[];
+extern const uint8_t digital_pin_to_pps_out_PGM[];
+extern const uint8_t digital_pin_to_pps_in_PGM[];
+extern const uint8_t digital_pin_to_analog_PGM[];
+extern const uint8_t analog_pin_to_channel_PGM[];
+
+extern const uint8_t output_compare_to_digital_pin_PGM[];
+extern const uint8_t external_int_to_digital_pin_PGM[];
+
+#endif
+
+/* ------------------------------------------------------------ */
+/* Internal Declarations */
+/* ------------------------------------------------------------ */
+/* The following declarations are used to map peripherals for */
+/* the core and libraries and to provide configuration options */
+/* for the core. They are not normally needed by a user sketch. */
+/* ------------------------------------------------------------ */
+
+#if defined(OPT_BOARD_INTERNAL)
+
+/* ------------------------------------------------------------ */
+/* Core Configuration Declarations */
+/* ------------------------------------------------------------ */
+/* */
+/* These are conditional compilation switches that control the */
+/* board core configuration functions. These functions provide */
+/* hooks that can call from some of the core functions into */
+/* functions defined below that can be used to extend or */
+/* replace the default behavior of the core function. To use */
+/* this, enter the appropriate code into the appropriate */
+/* function skeleton below and then set the appropriate switch */
+/* value to 1. This will cause the configuration function to be */
+/* compiled into the build and will cause the code to call the */
+/* hook function to be compiled into the core function. */
+/* */
+/* ------------------------------------------------------------ */
+
+#define OPT_BOARD_INIT 1 //board needs special init code
+#define OPT_BOARD_DIGITAL_IO 0 //board does not extend digital i/o functions
+#define OPT_BOARD_ANALOG_READ 0 //board does not extend analogRead
+#define OPT_BOARD_ANALOG_WRITE 0 //board does not extend analogWrite
+
+/* ------------------------------------------------------------ */
+/* Serial Port Declarations */
+/* ------------------------------------------------------------ */
+
+/* Serial port 0 uses UART1 – for the serial monitor
+*/
+#define _SER0_BASE _UART1_BASE_ADDRESS
+#define _SER0_IRQ _UART1_ERR_IRQ
+#define _SER0_VECTOR _UART_1_VECTOR
+#define _SER0_IPL_ISR _UART1_IPL_ISR
+#define _SER0_IPL _UART1_IPL_IPC
+#define _SER0_SPL _UART1_SPL_IPC
+#define _SER0_TX_OUT PPS_OUT_U1TX // FTDI RxD (RPB3R = 0x1) RPB3 <- U1TX
+#define _SER0_TX_PIN 23 // 23 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
+#define _SER0_RX_IN PPS_IN_U1RX // FTDI TxD (U1RXR = 0x5) RPC6 -> U1RX
+#define _SER0_RX_PIN 5 // 5 RC6 RPC6/PMA1/RC6
+
+
+/* Serial port 1 uses UART2
+*/
+#define _SER1_BASE _UART2_BASE_ADDRESS
+#define _SER1_IRQ _UART2_ERR_IRQ
+#define _SER1_VECTOR _UART_2_VECTOR
+#define _SER1_IPL_ISR _UART2_IPL_ISR
+#define _SER1_IPL _UART2_IPL_IPC
+#define _SER1_SPL _UART2_SPL_IPC
+#define _SER1_TX_OUT PPS_OUT_U2TX // J2-2 (RPB0R = 0x2) RPB0 <- U2TX
+#define _SER1_TX_PIN 20 // 20 RB0 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
+#define _SER1_RX_IN PPS_IN_U2RX // J2-3 (U2RXR = 0x2) RPB1 -> U2RX
+#define _SER1_RX_PIN 21 // 21 RB1 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
+
+
+/* Serial port 2 uses UART1
+** There really are not 3 UARTS, this just remaps UART1
+** away from the FTDI Serial Monitor Serial0 FTDI chip and applies UART1 to the lower pins of J1.
+** You can not use Serial0 and Serial2 concurrently.
+*/
+/* Currently Harware Serial will not allow an MX1/2 to have 3 UARTS
+#define _SER2_BASE _UART1_BASE_ADDRESS
+#define _SER2_IRQ _UART1_ERR_IRQ
+#define _SER2_VECTOR _UART_1_VECTOR
+#define _SER2_IPL_ISR _UART1_IPL_ISR
+#define _SER2_IPL _UART1_IPL_IPC
+#define _SER2_SPL _UART1_SPL_IPC
+#define _SER2_TX_OUT PPS_OUT_U1TX // J1-8 (RPC7R = 0x1) RPC7 <- U1TX
+#define _SER2_TX_PIN 6 // 6 RC7 RPC7/PMA0/RC7
+#define _SER2_RX_IN PPS_IN_U1RX // J1-9 (U1RXR = 0x2) RPA4 -> U1RX
+#define _SER2_RX_PIN 30 // 30 RA4 SOSCO/RPA4/T1CK/CTED9/RA4
+*/
+/* ------------------------------------------------------------ */
+/* SPI Port Declarations */
+/* ------------------------------------------------------------ */
+
+/* The default SPI port uses SPI1.
+*/
+#define _SPI_BASE _SPI1_BASE_ADDRESS
+#define _SPI_ERR_IRQ _SPI1_ERR_IRQ
+#define _SPI_RX_IRQ _SPI1_RX_IRQ
+#define _SPI_TX_IRQ _SPI1_TX_IRQ
+#define _SPI_VECTOR _SPI_1_VECTOR
+#define _SPI_IPL_ISR _SPI1_IPL_ISR
+#define _SPI_IPL _SPI1_IPL_IPC
+#define _SPI_SPL _SPI1_SPL_IPC
+
+/* SPI pin declarations
+*/
+#define _SPI_MISO_IN PPS_IN_SDI1
+#define _SPI_MISO_PIN MISO
+#define _SPI_MOSI_OUT PPS_OUT_SDO1
+#define _SPI_MOSI_PIN MOSI
+
+
+/* Full SPI1 on J1
+*/
+#define _DSPI0_BASE _SPI1_BASE_ADDRESS
+#define _DSPI0_ERR_IRQ _SPI1_ERR_IRQ
+#define _DSPI0_RX_IRQ _SPI1_RX_IRQ
+#define _DSPI0_TX_IRQ _SPI1_TX_IRQ
+#define _DSPI0_VECTOR _SPI_1_VECTOR
+#define _DSPI0_IPL_ISR _SPI1_IPL_ISR
+#define _DSPI0_IPL _SPI1_IPL_IPC
+#define _DSPI0_SPL _SPI1_SPL_IPC
+
+#define _DSPI0_MISO_IN PPS_IN_SDI1
+#define _DSPI0_MISO_PIN 35 // SDI1 RB5 SDI1R = 1 35 RB5 PGED3/RPB5/PMD7/RB5
+#define _DSPI0_MOSI_OUT PPS_OUT_SDO1
+#define _DSPI0_MOSI_PIN 25 // SDO1 RC1 RPC1R = 3 25 RC1 AN7/RPC1/RC1
+
+/* non-expanded SPI2 on the lower pins of J2
+*/
+#define _DSPI1_BASE _SPI2_BASE_ADDRESS
+#define _DSPI1_ERR_IRQ _SPI2_ERR_IRQ
+#define _DSPI1_RX_IRQ _SPI2_RX_IRQ
+#define _DSPI1_TX_IRQ _SPI2_TX_IRQ
+#define _DSPI1_VECTOR _SPI_2_VECTOR
+#define _DSPI1_IPL_ISR _SPI2_IPL_ISR
+#define _DSPI1_IPL _SPI2_IPL_IPC
+#define _DSPI1_SPL _SPI2_SPL_IPC
+
+#define _DSPI1_MISO_IN PPS_IN_SDI2
+#define _DSPI1_MISO_PIN 32 // RC3 SDI2 SDI2R = 7
+#define _DSPI1_MOSI_OUT PPS_OUT_SDO2
+#define _DSPI1_MOSI_PIN 36 // RB6 SDO2 RPB6R = 4
+
+/* ------------------------------------------------------------ */
+/* I2C Port Declarations */
+/* ------------------------------------------------------------ */
+
+/* The standard I2C1 port uses I2C1 (SCL1/SDA1).
+** RB8/RB9 pins 38/4
+*/
+#define _TWI_BASE _I2C1_BASE_ADDRESS
+#define _TWI_BUS_IRQ _I2C1_BUS_IRQ
+#define _TWI_SLV_IRQ _I2C1_SLAVE_IRQ
+#define _TWI_MST_IRQ _I2C1_MASTER_IRQ
+#define _TWI_VECTOR _I2C_1_VECTOR
+#define _TWI_IPL_ISR _I2C1_IPL_ISR
+#define _TWI_IPL _I2C1_IPL_IPC
+#define _TWI_SPL _I2C1_SPL_IPC
+
+/* Declarations for Digilent DTWI library.
+** DTWI0 is on RB8/RB9 pins 38/4
+*/
+#define _DTWI0_BASE _I2C1_BASE_ADDRESS
+#define _DTWI0_BUS_IRQ _I2C1_BUS_IRQ
+#define _DTWI0_SLV_IRQ _I2C1_SLAVE_IRQ
+#define _DTWI0_MST_IRQ _I2C1_MASTER_IRQ
+#define _DTWI0_VECTOR _I2C_1_VECTOR
+#define _DTWI0_IPL_ISR _I2C1_IPL_ISR
+#define _DTWI0_IPL _I2C1_IPL_IPC
+#define _DTWI0_SPL _I2C1_SPL_IPC
+
+/* ------------------------------------------------------------ */
+/* A/D Converter Declarations */
+/* ------------------------------------------------------------ */
+
+
+/* ------------------------------------------------------------ */
+
+#endif // OPT_BOARD_INTERNAL
+
+/* ------------------------------------------------------------ */
+
+#endif // BOARD_DEFS_H
+
+/************************************************************************/
View
37 hardware/pic32/variants/Cmod/boards.txt
@@ -0,0 +1,37 @@
+############################################################
+cmod.name=chipKIT Cmod
+cmod.group=chipKIT
+
+# new items
+cmod.platform=pic32
+cmod.board=_BOARD_CMOD_
+cmod.board.define=
+cmod.ccflags=ffff
+cmod.ldscript=chipKIT-application-32MX150F128.ld
+# end of new items
+
+# Use a high -Gnum for devices that have less than 64K of data memory
+# For -G1024, objects 1024 bytes or smaller will be accessed by
+# gp-relative addressing
+cmod.compiler.c.flags=-O2::-c::-mno-smart-io::-w::-ffunction-sections::-fdata-sections::-G1024::-g::-mdebugger::-Wcast-align::-fno-short-double
+cmod.compiler.cpp.flags=-O2::-c::-mno-smart-io::-w::-fno-exceptions::-ffunction-sections::-fdata-sections::-G1024::-g::-mdebugger::-Wcast-align::-fno-short-double
+
+cmod.upload.protocol=stk500v2
+# 128KB - 4K for EEPROM
+cmod.upload.maximum_size=122880
+cmod.upload.speed=115200
+
+cmod.bootloader.low_fuses=0xff
+cmod.bootloader.high_fuses=0xdd
+cmod.bootloader.extended_fuses=0x00
+cmod.bootloader.path=not-supported
+cmod.bootloader.file=not-supported
+cmod.bootloader.unlock_bits=0x3F
+cmod.bootloader.lock_bits=0x0F
+
+cmod.build.mcu=32MX150F128D
+cmod.build.f_cpu=40000000L
+cmod.build.core=pic32
+cmod.build.variant=Cmod
+
+############################################################
View
134 hardware/pic32/variants/Cmod/chipKIT-application-32MX150F128.ld
@@ -0,0 +1,134 @@
+/* Default linker script, for normal executables */
+OUTPUT_FORMAT("elf32-tradlittlemips")
+OUTPUT_ARCH(pic32mx)
+ENTRY(_reset)
+/*
+ * Provide for a minimum stack and heap size
+ * - _min_stack_size - represents the minimum space that must be made
+ * available for the stack. Can be overridden from
+ * the command line using the linker's --defsym option.
+ * - _min_heap_size - represents the minimum space that must be made
+ * available for the heap. Can be overridden from
+ * the command line using the linker's --defsym option.
+ */
+EXTERN (_min_stack_size _min_heap_size)
+PROVIDE(_min_stack_size = 0x800) ;
+PROVIDE(_min_heap_size = 0x800) ;
+
+/*************************************************************************
+ * Processor-specific object file. Contains SFR definitions.
+ *************************************************************************/
+INPUT("processor.o")
+
+/*************************************************************************
+ * Memory Regions
+ *
+ * Memory regions without attributes cannot be used for orphaned sections.
+ * Only sections specifically assigned to these regions can be allocated
+ * into these regions.
+ *************************************************************************/
+MEMORY
+{
+ exception_mem : ORIGIN = 0x9D000000, LENGTH = 0x1000
+ kseg0_program_mem (rx) : ORIGIN = 0x9D001000, LENGTH = 0x1E000
+ kseg0_eeprom_mem : ORIGIN = 0x9D01F000, LENGTH = 0x1000
+ kseg0_boot_mem : ORIGIN = 0x9FC00200, LENGTH = 0
+ kseg1_boot_mem : ORIGIN = 0xBFC00000, LENGTH = 0
+ debug_exec_mem : ORIGIN = 0xBFC00490, LENGTH = 0
+ config3 : ORIGIN = 0xBFC00BF0, LENGTH = 0x4
+ config2 : ORIGIN = 0xBFC00BF4, LENGTH = 0x4
+ config1 : ORIGIN = 0xBFC00BF8, LENGTH = 0x4
+ config0 : ORIGIN = 0xBFC00BFC, LENGTH = 0x4
+ kseg1_data_mem (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x8000
+ sfrs : ORIGIN = 0xBF800000, LENGTH = 0x100000
+ configsfrs : ORIGIN = 0xBFC00BF0, LENGTH = 0x10
+}
+
+/*************************************************************************
+ * Memory Address Equates
+ *************************************************************************/
+_ebase_address = ORIGIN(exception_mem);
+_IMAGE_PTR_TABLE = _ebase_address + 0x0F8;
+_IMAGE_HEADER_ADDR = _ebase_address + 0x0FC;
+_GEN_EXCPT_ADDR = _ebase_address + 0x180;
+_RESET_ADDR = ORIGIN(kseg0_program_mem);
+_EEPROM_ADDR = ORIGIN(kseg0_eeprom_mem);
+_BEV_EXCPT_ADDR = 0xBFC00380;
+_DBG_EXCPT_ADDR = 0xBFC00480;
+_DBG_CODE_ADDR = ORIGIN(debug_exec_mem);
+
+/*************************************************************************
+ * Bootloader program directives.
+ *
+ * _IMAGE_TYPE
+ *
+ * image type:
+ */
+
+_imageReserved = 0x00000000 ;
+_imageMPIDE = 0x00000001 ; /* This is a normal MPIDE sketch */
+_imageBootFlashBootloader = 0x00000002 ; /* This is a boot flash bootloader */
+_imageProgramFlashBootloader = 0x00000004 ; /* This is a program flash bootloader */
+_imageSplitFlashBootloader = 0x00000008 ; /* This has bootloader code in both boot and program flash */
+
+ /*
+ * Instructions for the bootloader
+ */
+
+_imageFullFlashEraseLess4KEEProm = 0x00010000 ; /* The original bootloader method of erasing all of program flash except the last 4K reserved for eeprom */
+_imageJustInTimeFlashErase = 0x00020000 ; /* Only flash pages written too needed by the sketch is erased */
+_imageLinkerSpecifiedFlashErase = 0x00040000 ; /* The linker defines the flash range to erase */
+_imageFullFlashErase = 0x00080000 ; /* All of flash is erased */
+_imageExecutionJumpAddress = 0x01000000 ; /* the bootloader will jump to the execution jump address immediately after programming */
+_imageExecutionJumpToFirstInFlash = 0x02000000 ; /* the bootloader will jump to the first sketch loaded in flash ignoring the execution jump address immediately after programming */
+
+/*
+ * _IMAGE_FLASH_SIZE
+ *
+ * Typically _imageJustInTimeFlashErase is selected to just erase the pages
+ * of flash that code is written too; thus leaving all other flash pages untouched.
+ *
+ * If _imageLinkerSpecifiedFlashErase set, then the range
+ * starting from _ebase_address for _IMAGE_FLASH_SIZE bytes are erased.
+ *
+ * If _imageFullFlashErase is specified, than the whole flash
+ * as known by the bootloader will be erased. This will erase eeprom as well
+ *
+ * if _imageFullFlashEraseLess4KEEProm is set, all of flash less the last 4K is
+ * erased, this is the old default. This bit could be set to make a program flash bootloader
+ * erasing everything but the old flash. If NOTHING is set, this will be the default as this is the old behavior.
+ *
+ * _JUMP_ADDR
+ *
+ * This is the address that the bootloader will jump to start execution
+ * of the sketch. This is almost always _RESET_ADDR.
+ *
+ * However, you can specify an alternate entry execution point for example
+ * if you have alternate starup code that, say, shared
+ * the runtime with other sketches or needed some kind of specific handling
+ *
+ * Immediately after programming (avrdude upload) the bootloader will typically
+ * jump to the just loaded sketch, no matter where it was loaded in flash.
+ * _imageExecutionJumpToFirstInFlash will tell the bootloader to jump to the first
+ * sketch in flash even if the just loaded one is not at the beginning of flash.
+ * This is useful when programming sketches in slots of flash and then always
+ * jumping to the program-flash loader (vector sketch) as if the board was just reset.
+ * This bit does not effect jumping to a sketch already in flash after reset.
+ * As of today, after reset, the first program in flash will always be jumped to.
+ *
+ *************************************************************************/
+ _IMAGE_TYPE = _imageMPIDE | _imageJustInTimeFlashErase | _imageExecutionJumpAddress;
+ _IMAGE_FLASH_SIZE = LENGTH(exception_mem) + LENGTH(kseg0_program_mem);
+_JUMP_ADDR = _RESET_ADDR;
+
+SECTIONS
+{
+ /* Boot Sections */
+ .reset _RESET_ADDR :
+ {
+ KEEP(*(.reset))
+ } > kseg0_program_mem
+}
+
+/* From here out every linker script is the same, so just include it */
+/*INCLUDE "chipKIT-application-COMMON.ld"*/

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