Skip to content
This repository
Browse code

Merge pull request #281 from EmbeddedMan/MX1_MX2

Add in support for MX1/MX2 PIC32 processors
  • Loading branch information...
commit f4f5abd738edfd1ccedfeef68f844cb562cccfed 2 parents 1bf3e05 + 8c71a97
Ricklon authored October 01, 2012

Showing 52 changed files with 7,939 additions and 1,809 deletions. Show diff stats Hide diff stats

  1. 187  build/windows/dist/avrdude.conf
  2. 214  hardware/pic32/boards.txt
  3. 56  hardware/pic32/cores/pic32/HardwareSerial.cpp
  4. 13  hardware/pic32/cores/pic32/HardwareSerial.h
  5. 2  hardware/pic32/cores/pic32/HardwareSerial_cdcacm.c
  6. 16  hardware/pic32/cores/pic32/HardwareSerial_usb.c
  7. 8  hardware/pic32/cores/pic32/System_Defs.h
  8. 2  hardware/pic32/cores/pic32/Tone.cpp
  9. 22  hardware/pic32/cores/pic32/WInterrupts.c
  10. 165  hardware/pic32/cores/pic32/chipKIT-application-32MX120F032-nobootloader.ld
  11. 268  hardware/pic32/cores/pic32/chipKIT-application-32MX120F032.ld
  12. 166  hardware/pic32/cores/pic32/chipKIT-application-32MX250F128-nobootloader.ld
  13. 270  hardware/pic32/cores/pic32/chipKIT-application-32MX250F128.ld
  14. 170  hardware/pic32/cores/pic32/chipKIT-application-32MX320F128-nobootloader.ld
  15. 268  hardware/pic32/cores/pic32/chipKIT-application-32MX320F128.ld
  16. 268  hardware/pic32/cores/pic32/chipKIT-application-32MX340F512.ld
  17. 268  hardware/pic32/cores/pic32/chipKIT-application-32MX360F512.ld
  18. 268  hardware/pic32/cores/pic32/chipKIT-application-32MX440F128.ld
  19. 268  hardware/pic32/cores/pic32/chipKIT-application-32MX440F256.ld
  20. 268  hardware/pic32/cores/pic32/chipKIT-application-32MX440F512.ld
  21. 170  hardware/pic32/cores/pic32/chipKIT-application-32MX460F512-nobootloader.ld
  22. 268  hardware/pic32/cores/pic32/chipKIT-application-32MX460F512.ld
  23. 171  hardware/pic32/cores/pic32/chipKIT-application-32MX795F512-nobootloader.ld
  24. 270  hardware/pic32/cores/pic32/chipKIT-application-32MX795F512.ld
  25. 2  hardware/pic32/cores/pic32/chipKIT-application-COMMON.ld
  26. 211  hardware/pic32/cores/pic32/p32_defs.h
  27. 39  hardware/pic32/cores/pic32/pins_arduino.c
  28. 128  hardware/pic32/cores/pic32/pins_arduino.h
  29. 336  hardware/pic32/cores/pic32/wiring.c
  30. 37  hardware/pic32/cores/pic32/wiring.h
  31. 180  hardware/pic32/cores/pic32/wiring_analog.c
  32. 122  hardware/pic32/cores/pic32/wiring_digital.c
  33. 33  hardware/pic32/variants/Cerebot_32MX4/Board_Defs.h
  34. 33  hardware/pic32/variants/Cerebot_32MX7/Board_Defs.h
  35. 718  hardware/pic32/variants/Cerebot_GA4/Board_Data.c
  36. 395  hardware/pic32/variants/Cerebot_GA4/Board_Defs.h
  37. 33  hardware/pic32/variants/Cerebot_MX3cK/Board_Defs.h
  38. 33  hardware/pic32/variants/Cerebot_MX4cK/Board_Defs.h
  39. 33  hardware/pic32/variants/Cerebot_MX7cK/Board_Defs.h
  40. 30  hardware/pic32/variants/Default_100/Board_Defs.h
  41. 38  hardware/pic32/variants/Default_64/Board_Defs.h
  42. 711  hardware/pic32/variants/Fubarino_Mini/Board_Data.c
  43. 401  hardware/pic32/variants/Fubarino_Mini/Board_Defs.h
  44. 32  hardware/pic32/variants/Max32/Board_Defs.h
  45. 41  hardware/pic32/variants/Uno32/Board_Defs.h
  46. 642  hardware/pic32/variants/Uno32_Pmod_Shield/Board_Data.c
  47. 387  hardware/pic32/variants/Uno32_Pmod_Shield/Board_Defs.h
  48. 19  hardware/pic32/variants/fubarino_sd_v10/Board_Data.c
  49. 2  hardware/pic32/variants/fubarino_sd_v10/Board_Defs.h
  50. 37  hardware/pic32/variants/uC32/Board_Defs.h
  51. 642  hardware/pic32/variants/uC32_Pmod_Shield/Board_Data.c
  52. 387  hardware/pic32/variants/uC32_Pmod_Shield/Board_Defs.h
187  build/windows/dist/avrdude.conf
@@ -17564,3 +17564,190 @@ part
17564 17564
   ;
17565 17565
 
17566 17566
 
  17567
+#------------------------------------------------------------
  17568
+# Pic CPU PIC32MX250F128D added by Brian Schmalz, May 2012
  17569
+#------------------------------------------------------------
  17570
+
  17571
+part
  17572
+    id               = "pic32-250-128";
  17573
+    desc             = "32MX250F128D";
  17574
+    signature        = 0x50 0x49 0x43;
  17575
+    has_jtag         = no;
  17576
+#    stk500_devcode   = 0xB2;
  17577
+#    avr910_devcode   = 0x43;
  17578
+    chip_erase_delay = 9000;
  17579
+    pagel            = 0xD7;
  17580
+    bs2              = 0xA0;
  17581
+    reset            = dedicated;
  17582
+    pgm_enable       = "1 0 1 0  1 1 0 0    0 1 0 1  0 0 1 1",
  17583
+                       "x x x x  x x x x    x x x x  x x x x";
  17584
+
  17585
+    chip_erase       = "1 0 1 0  1 1 0 0    1 0 0 0  0 0 0 0",
  17586
+                       "x x x x  x x x x    x x x x  x x x x";
  17587
+
  17588
+    timeout			= 200;
  17589
+    stabdelay		= 100;
  17590
+    cmdexedelay		= 25;
  17591
+    synchloops		= 32;
  17592
+    bytedelay		= 0;
  17593
+    pollindex		= 3;
  17594
+    pollvalue		= 0x53;
  17595
+    predelay		= 1;
  17596
+    postdelay		= 1;
  17597
+    pollmethod		= 1;
  17598
+
  17599
+    pp_controlstack     =
  17600
+        0x0E, 0x1E, 0x0F, 0x1F, 0x2E, 0x3E, 0x2F, 0x3F,
  17601
+        0x4E, 0x5E, 0x4F, 0x5F, 0x6E, 0x7E, 0x6F, 0x7F,
  17602
+        0x66, 0x76, 0x67, 0x77, 0x6A, 0x7A, 0x6B, 0x7B,
  17603
+        0xBE, 0xFD, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02;
  17604
+    hventerstabdelay    = 100;
  17605
+    progmodedelay       = 0;
  17606
+    latchcycles         = 5;
  17607
+    togglevtg           = 1;
  17608
+    poweroffdelay       = 15;
  17609
+    resetdelayms        = 1;
  17610
+    resetdelayus        = 0;
  17611
+    hvleavestabdelay    = 15;
  17612
+    chiperasepulsewidth = 0;
  17613
+    chiperasepolltimeout = 10;
  17614
+    programfusepulsewidth = 0;
  17615
+    programfusepolltimeout = 5;
  17616
+    programlockpulsewidth = 0;
  17617
+    programlockpolltimeout = 5;
  17618
+
  17619
+    idr                 = 0x31;
  17620
+    spmcr               = 0x57;
  17621
+    rampz               = 0x3b;
  17622
+    allowfullpagebitstream = no;
  17623
+
  17624
+    memory "eeprom"
  17625
+        paged           = no; /* leave this "no" */
  17626
+        page_size       = 8;  /* for parallel programming */
  17627
+        size            = 4096;
  17628
+        min_write_delay = 9000;
  17629
+        max_write_delay = 9000;
  17630
+        readback_p1     = 0x00;
  17631
+        readback_p2     = 0x00;
  17632
+        read            = "  1   0   1   0      0   0   0   0",
  17633
+                          "  x   x   x   x    a11 a10  a9  a8",
  17634
+                          " a7  a6  a5  a4     a3  a2  a1  a0",
  17635
+                          "  o   o   o   o      o   o   o   o";
  17636
+
  17637
+        write           = "  1   1   0   0      0   0   0   0",
  17638
+                          "  x   x   x   x    a11 a10  a9  a8",
  17639
+                          " a7  a6  a5  a4     a3  a2  a1  a0", 
  17640
+                          "  i   i   i   i      i   i   i   i";
  17641
+
  17642
+	loadpage_lo	= "  1   1   0   0      0   0   0   1",
  17643
+			  "  0   0   0   0      0   0   0   0",
  17644
+			  "  0   0   0   0      0  a2  a1  a0",
  17645
+			  "  i   i   i   i      i   i   i   i";
  17646
+
  17647
+	writepage	= "  1   1   0   0      0   0   1   0",
  17648
+			  "  0   0   x   x    a11 a10  a9  a8",
  17649
+			  " a7  a6  a5  a4     a3   0   0   0",
  17650
+			  "  x   x   x   x      x   x   x   x";
  17651
+
  17652
+	mode		= 0x41;
  17653
+	delay		= 10;
  17654
+	blocksize	= 8;
  17655
+	readsize	= 256;
  17656
+      ;
  17657
+
  17658
+    memory "flash"
  17659
+        paged           = yes;
  17660
+        size            = 131072;
  17661
+        page_size       = 256;
  17662
+        num_pages       = 512;
  17663
+        min_write_delay = 4500;
  17664
+        max_write_delay = 4500;
  17665
+        readback_p1     = 0xff;
  17666
+        readback_p2     = 0xff;
  17667
+        read_lo         = "  0   0   1   0      0   0   0   0",
  17668
+                          "a15 a14 a13 a12    a11 a10  a9  a8",
  17669
+                          " a7  a6  a5  a4     a3  a2  a1  a0",
  17670
+                          "  o   o   o   o      o   o   o   o";
  17671
+
  17672
+        read_hi         = "  0   0   1   0      1   0   0   0",
  17673
+                          "a15 a14 a13 a12    a11 a10  a9  a8",
  17674
+                          " a7  a6  a5  a4     a3  a2  a1  a0",
  17675
+                          "  o   o   o   o      o   o   o   o";
  17676
+
  17677
+        loadpage_lo     = "  0   1   0   0      0   0   0   0",
  17678
+                          "  x   x   x   x      x   x   x   x",
  17679
+                          "  x  a6  a5  a4     a3  a2  a1  a0",
  17680
+                          "  i   i   i   i      i   i   i   i";
  17681
+
  17682
+        loadpage_hi     = "  0   1   0   0      1   0   0   0",
  17683
+                          "  x   x   x   x      x   x   x   x",
  17684
+                          "  x  a6  a5  a4     a3  a2  a1  a0",
  17685
+                          "  i   i   i   i      i   i   i   i";
  17686
+
  17687
+        writepage       = "  0   1   0   0      1   1   0   0",
  17688
+                          "a15 a14 a13 a12    a11 a10  a9  a8",
  17689
+                          " a7   x   x   x      x   x   x   x",
  17690
+                          "  x   x   x   x      x   x   x   x";
  17691
+
  17692
+	mode		= 0x41;
  17693
+	delay		= 10;
  17694
+	blocksize	= 128;
  17695
+	readsize	= 256;
  17696
+      ;
  17697
+
  17698
+    memory "lock"
  17699
+        size            = 1;
  17700
+        read            = "0 1 0 1  1 0 0 0   0 0 0 0  0 0 0 0",
  17701
+                          "x x x x  x x x x   x x o o  o o o o";
  17702
+
  17703
+        write           = "1 0 1 0  1 1 0 0   1 1 1 x  x x x x",
  17704
+                          "x x x x  x x x x   1 1 i i  i i i i";
  17705
+        min_write_delay = 9000;
  17706
+        max_write_delay = 9000;
  17707
+      ;
  17708
+
  17709
+    memory "lfuse"
  17710
+        size            = 1;
  17711
+        write           = "1 0 1 0  1 1 0 0  1 0 1 0  0 0 0 0",
  17712
+                          "x x x x  x x x x  i i i i  i i i i";
  17713
+
  17714
+        read            = "0 1 0 1  0 0 0 0  0 0 0 0  0 0 0 0",
  17715
+                          "x x x x  x x x x  o o o o  o o o o";
  17716
+        min_write_delay = 9000;
  17717
+        max_write_delay = 9000;
  17718
+      ;
  17719
+
  17720
+    memory "hfuse"
  17721
+        size            = 1;
  17722
+        write           = "1 0 1 0  1 1 0 0  1 0 1 0  1 0 0 0",
  17723
+                          "x x x x  x x x x  i i i i  i i i i";
  17724
+
  17725
+        read            = "0 1 0 1  1 0 0 0  0 0 0 0  1 0 0 0",
  17726
+                          "x x x x  x x x x  o o o o  o o o o";
  17727
+        min_write_delay = 9000;
  17728
+        max_write_delay = 9000;
  17729
+      ;
  17730
+
  17731
+    memory "efuse"
  17732
+        size            = 1;
  17733
+        write           = "1 0 1 0  1 1 0 0  1 0 1 0  0 1 0 0",
  17734
+                          "x x x x  x x x x  x x x x  x i i i";
  17735
+
  17736
+        read            = "0 1 0 1  0 0 0 0  0 0 0 0  1 0 0 0",
  17737
+                          "x x x x  x x x x  o o o o  o o o o";
  17738
+        min_write_delay = 9000;
  17739
+        max_write_delay = 9000;
  17740
+      ;
  17741
+
  17742
+    memory "calibration"
  17743
+        size            = 1;
  17744
+        read            = "0 0 1 1  1 0 0 0    x x x x  x x x x",
  17745
+                          "0 0 0 0  0 0 0 0    o o o o  o o o o";
  17746
+      ;
  17747
+
  17748
+    memory "signature"
  17749
+        size            = 3;
  17750
+        read            = "0  0  1  1   0  0  0  0   x  x  x  x   x  x  x  x",
  17751
+                          "x  x  x  x   x  x a1 a0   o  o  o  o   o  o  o  o";
  17752
+      ;
  17753
+  ;
214  hardware/pic32/boards.txt
... ...
@@ -1,4 +1,79 @@
1 1
 ############################################################
  2
+cerebot_ga4.name=MX1 Cerebot GA4
  3
+
  4
+# new items
  5
+cerebot_ga4.platform=pic32
  6
+cerebot_ga4.board=_BOARD_CEREBOT_GA4_
  7
+cerebot_ga4.board.define=
  8
+#cerebot_ga4.compiler.define=-Danything_you_want::-Danything=1
  9
+cerebot_ga4.ccflags=ffff
  10
+cerebot_ga4.ldscript=chipKIT-application-32MX120F032D.ld
  11
+# end of new items
  12
+
  13
+# Use a high -Gnum for devices that have less than 64K of data memory
  14
+# For -G1024, objects 1024 bytes or smaller will be accessed by
  15
+# gp-relative addressing
  16
+cerebot_ga4.compiler.c.flags=-O2::-c::-mno-smart-io::-w::-ffunction-sections::-fdata-sections::-G1024::-g::-mdebugger::-Wcast-align::-fno-short-double
  17
+cerebot_ga4.compiler.cpp.flags=-O2::-c::-mno-smart-io::-w::-fno-exceptions::-ffunction-sections::-fdata-sections::-G1024::-g::-mdebugger::-Wcast-align::-fno-short-double
  18
+
  19
+cerebot_ga4.upload.protocol=stk500v2
  20
+cerebot_ga4.upload.maximum_size=28672
  21
+cerebot_ga4.upload.speed=115200
  22
+
  23
+cerebot_ga4.bootloader.low_fuses=0xff
  24
+cerebot_ga4.bootloader.high_fuses=0xdd
  25
+cerebot_ga4.bootloader.extended_fuses=0x00
  26
+cerebot_ga4.bootloader.path=not-supported
  27
+cerebot_ga4.bootloader.file=not-supported
  28
+cerebot_ga4.bootloader.unlock_bits=0x3F
  29
+cerebot_ga4.bootloader.lock_bits=0x0F
  30
+
  31
+cerebot_ga4.build.mcu=32MX120F032D
  32
+cerebot_ga4.build.f_cpu=40000000L
  33
+cerebot_ga4.build.core=pic32
  34
+cerebot_ga4.build.variant=Cerebot_GA4
  35
+#cerebot_ga4.upload.using=
  36
+
  37
+############################################################
  38
+cerebot_ga4_dbg.name=MX1 Cerebot GA4 - MPLAB Debug
  39
+
  40
+# new items
  41
+cerebot_ga4_dbg.platform=pic32
  42
+cerebot_ga4_dbg.board=_BOARD_CEREBOT_GA4_
  43
+cerebot_ga4_dbg.board.define=
  44
+#cerebot_ga4_dbg.compiler.define=-Danything_you_want::-Danything=1
  45
+cerebot_ga4_dbg.ccflags=ffff
  46
+cerebot_ga4_dbg.ldscript=chipKIT-application-32MX120F032D-nobootloader.ld
  47
+# end of new items
  48
+
  49
+# Use a high -Gnum for devices that have less than 64K of data memory
  50
+# For -G1024, objects 1024 bytes or smaller will be accessed by
  51
+# gp-relative addressing
  52
+cerebot_ga4_dbg.compiler.c.flags=-O0::-c::-mno-smart-io::-w::-ffunction-sections::-fdata-sections::-G1024::-g::-mdebugger::-Wcast-align::-fno-short-double
  53
+cerebot_ga4_dbg.compiler.cpp.flags=-O0::-c::-mno-smart-io::-w::-fno-exceptions::-ffunction-sections::-fdata-sections::-G1024::-g::-mdebugger::-Wcast-align::-fno-short-double
  54
+
  55
+cerebot_ga4_dbg.upload.protocol=stk500v2
  56
+cerebot_ga4_dbg.upload.maximum_size=28672
  57
+cerebot_ga4_dbg.upload.speed=115200
  58
+
  59
+cerebot_ga4_dbg.bootloader.low_fuses=0xff
  60
+cerebot_ga4_dbg.bootloader.high_fuses=0xdd
  61
+cerebot_ga4_dbg.bootloader.extended_fuses=0x00
  62
+cerebot_ga4_dbg.bootloader.path=not-supported
  63
+cerebot_ga4_dbg.bootloader.file=not-supported
  64
+cerebot_ga4_dbg.bootloader.unlock_bits=0x3F
  65
+cerebot_ga4_dbg.bootloader.lock_bits=0x0F
  66
+
  67
+cerebot_ga4_dbg.build.mcu=32MX120F032D
  68
+cerebot_ga4_dbg.build.f_cpu=40000000L
  69
+cerebot_ga4_dbg.build.core=pic32
  70
+cerebot_ga4_dbg.build.variant=Cerebot_GA4
  71
+#cerebot_ga4_dbg.upload.using=
  72
+
  73
+############################################################
  74
+############################################################
  75
+############################################################
  76
+############################################################
2 77
 uno_pic32.name=chipKIT UNO32
3 78
 
4 79
 # new items
@@ -68,7 +143,7 @@ mega_usb_pic32.name=chipKIT MAX32-USB for Serial
68 143
 
69 144
 # new items
70 145
 mega_usb_pic32.platform=pic32
71  
-mega_usb_pic32.board=_BOARD_MEGA_USB_
  146
+mega_usb_pic32.board=_BOARD_MEGA_
72 147
 mega_usb_pic32.board.define=-D_USE_USB_FOR_SERIAL_
73 148
 mega_usb_pic32.ccflags=ffff
74 149
 mega_usb_pic32.ldscript=chipKIT-application-32MX795F512.ld
@@ -93,6 +168,41 @@ mega_usb_pic32.build.variant=Max32
93 168
 #mega_usb_pic32.upload.using=
94 169
 
95 170
 ############################################################
  171
+mega_usb_debug_pic32.name=chipKIT MAX32-USB for Serial Debug
  172
+
  173
+# new items
  174
+mega_usb_debug_pic32.platform=pic32
  175
+mega_usb_debug_pic32.board=_BOARD_MEGA_
  176
+mega_usb_debug_pic32.board.define=-D_USE_USB_FOR_SERIAL_
  177
+mega_usb_debug_pic32.ccflags=-Map="map.map"
  178
+mega_usb_debug_pic32.ldscript=chipKIT-MAX32-application-32MX795F512-nobootloader.ld
  179
+# end of new items
  180
+
  181
+# Use a high -Gnum for devices that have less than 64K of data memory
  182
+# For -G1024, objects 1024 bytes or smaller will be accessed by
  183
+# gp-relative addressing
  184
+mega_usb_debug_pic32.compiler.c.flags=-O0::-c::-mno-smart-io::-w::-ffunction-sections::-fdata-sections::-G1024::-g::-mdebugger::-Wcast-align::-fno-short-double
  185
+mega_usb_debug_pic32.compiler.cpp.flags=-O0::-c::-mno-smart-io::-w::-fno-exceptions::-ffunction-sections::-fdata-sections::-G1024::-g::-mdebugger::-Wcast-align::-fno-short-double
  186
+
  187
+mega_usb_debug_pic32.upload.protocol=stk500v2
  188
+mega_usb_debug_pic32.upload.maximum_size=520192
  189
+mega_usb_debug_pic32.upload.speed=115200
  190
+
  191
+mega_usb_debug_pic32.bootloader.low_fuses=0xff
  192
+mega_usb_debug_pic32.bootloader.high_fuses=0xdd
  193
+mega_usb_debug_pic32.bootloader.extended_fuses=0x00
  194
+mega_usb_debug_pic32.bootloader.path=not-supported
  195
+mega_usb_debug_pic32.bootloader.file=not-supported
  196
+mega_usb_debug_pic32.bootloader.unlock_bits=0x3F
  197
+mega_usb_debug_pic32.bootloader.lock_bits=0x0F
  198
+
  199
+mega_usb_debug_pic32.build.mcu=32MX795F512L
  200
+mega_usb_debug_pic32.build.f_cpu=80000000L
  201
+mega_usb_debug_pic32.build.core=pic32
  202
+mega_usb_debug_pic32.build.variant=Max32
  203
+#mega_usb_pic32.upload.using=
  204
+
  205
+############################################################
96 206
 chipkit_uc32.name=chipKIT uC32
97 207
 
98 208
 # new items
@@ -256,6 +366,39 @@ cerebot_mx7ck.build.variant=Cerebot_MX7cK
256 366
 #cerebot_mx7ck.upload.using=
257 367
 
258 368
 ############################################################
  369
+MX7ck_dbg.name=Cerebot MX7cK - MPLAB Debug
  370
+
  371
+# new items
  372
+MX7ck_dbg.platform=pic32
  373
+MX7ck_dbg.board=_BOARD_CEREBOT_MX7CK_
  374
+MX7ck_dbg.board.define=
  375
+MX7ck_dbg.ccflags=ffff
  376
+MX7ck_dbg.ldscript=chipKIT-application-32MX795F512L-nobootloader.ld
  377
+# end of new items
  378
+
  379
+# Override the compiler flags to turn off optimizations
  380
+MX7ck_dbg.compiler.c.flags=-O0::-c::-mno-smart-io::-w::-ffunction-sections::-fdata-sections::-g::-mdebugger::-Wcast-align::-fno-short-double::-save-temps::-g3
  381
+MX7ck_dbg.compiler.cpp.flags=-O0::-c::-mno-smart-io::-w::-fno-exceptions::-ffunction-sections::-fdata-sections::-g::-mdebugger::-Wcast-align::-fno-short-double
  382
+
  383
+MX7ck_dbg.upload.protocol=stk500v2
  384
+MX7ck_dbg.upload.maximum_size=520192
  385
+MX7ck_dbg.upload.speed=115200
  386
+
  387
+MX7ck_dbg.bootloader.low_fuses=0xff
  388
+MX7ck_dbg.bootloader.high_fuses=0xdd
  389
+MX7ck_dbg.bootloader.extended_fuses=0x00
  390
+MX7ck_dbg.bootloader.path=not-supported
  391
+MX7ck_dbg.bootloader.file=not-supported
  392
+MX7ck_dbg.bootloader.unlock_bits=0x3F
  393
+MX7ck_dbg.bootloader.lock_bits=0x0F
  394
+
  395
+MX7ck_dbg.build.mcu=32MX795F512L
  396
+MX7ck_dbg.build.f_cpu=80000000L
  397
+MX7ck_dbg.build.core=pic32
  398
+MX7ck_dbg.build.variant=Cerebot_MX7cK
  399
+#MX7ck_dbg.upload.using=
  400
+
  401
+############################################################
259 402
 cerebot32mx4.name=Cerebot 32MX4
260 403
 
261 404
 # new items
@@ -633,6 +776,75 @@ fubarino_sd.build.core=pic32
633 776
 fubarino_sd.build.variant=fubarino_sd_v11
634 777
 
635 778
 ############################################################
  779
+fubarino_mini.name=Fubarino_Mini
  780
+
  781
+# new items
  782
+fubarino_mini.platform=pic32
  783
+fubarino_mini.board=_BOARD_FUBARINO_MINI_
  784
+fubarino_mini.board.define=-D_USE_USB_FOR_SERIAL_
  785
+fubarino_mini.ccflags=-Map="map.map"
  786
+fubarino_mini.ldscript=chipKIT-application-32MX250F128.ld
  787
+# end of new items
  788
+
  789
+# Use a high -Gnum for devices that have less than 64K of data memory
  790
+# For -G1024, objects 1024 bytes or smaller will be accessed by
  791
+# gp-relative addressing
  792
+fubarino_mini.compiler.c.flags=-O2::-c::-mno-smart-io::-w::-ffunction-sections::-fdata-sections::-G1024::-g::-mdebugger::-Wcast-align::-fno-short-double
  793
+fubarino_mini.compiler.cpp.flags=-O2::-c::-mno-smart-io::-w::-fno-exceptions::-ffunction-sections::-fdata-sections::-G1024::-g::-mdebugger::-Wcast-align::-fno-short-double
  794
+
  795
+fubarino_mini.upload.protocol=stk500v2
  796
+# 128KB - 4K for EEPROM - 4K for bootloader
  797
+fubarino_mini.upload.maximum_size=122880
  798
+fubarino_mini.upload.speed=115200
  799
+
  800
+fubarino_mini.bootloader.low_fuses=0xff
  801
+fubarino_mini.bootloader.high_fuses=0xdd
  802
+fubarino_mini.bootloader.extended_fuses=0x00
  803
+fubarino_mini.bootloader.path=not-supported
  804
+fubarino_mini.bootloader.file=not-supported
  805
+fubarino_mini.bootloader.unlock_bits=0x3F
  806
+fubarino_mini.bootloader.lock_bits=0x0F
  807
+
  808
+fubarino_mini.build.mcu=32MX250F128D
  809
+fubarino_mini.build.f_cpu=40000000L
  810
+fubarino_mini.build.core=pic32
  811
+fubarino_mini.build.variant=Fubarino_Mini
  812
+
  813
+############################################################
  814
+fubarino_mini_dbg.name=Fubarino_Mini Debug
  815
+
  816
+# new items
  817
+fubarino_mini_dbg.platform=pic32
  818
+fubarino_mini_dbg.board=_BOARD_FUBARINO_MINI_
  819
+fubarino_mini_dbg.board.define=-D_USE_USB_FOR_SERIAL_
  820
+fubarino_mini_dbg.ccflags=-Map="map.map"
  821
+fubarino_mini_dbg.ldscript=chipKIT-application-32MX250F128-nobootloader.ld
  822
+# end of new items
  823
+
  824
+# Use a high -Gnum for devices that have less than 64K of data memory
  825
+# For -G1024, objects 1024 bytes or smaller will be accessed by
  826
+# gp-relative addressing
  827
+fubarino_mini_dbg.compiler.c.flags=-O0::-c::-mno-smart-io::-w::-ffunction-sections::-fdata-sections::-G1024::-g::-mdebugger::-Wcast-align::-fno-short-double
  828
+fubarino_mini_dbg.compiler.cpp.flags=-O0::-c::-mno-smart-io::-w::-fno-exceptions::-ffunction-sections::-fdata-sections::-G1024::-g::-mdebugger::-Wcast-align::-fno-short-double
  829
+fubarino_mini_dbg.upload.protocol=stk500v2
  830
+# 128KB - 4K for EEPROM - 4K for bootloader
  831
+fubarino_mini_dbg.upload.maximum_size=122880
  832
+fubarino_mini_dbg.upload.speed=115200
  833
+
  834
+fubarino_mini_dbg.bootloader.low_fuses=0xff
  835
+fubarino_mini_dbg.bootloader.high_fuses=0xdd
  836
+fubarino_mini_dbg.bootloader.extended_fuses=0x00
  837
+fubarino_mini_dbg.bootloader.path=not-supported
  838
+fubarino_mini_dbg.bootloader.file=not-supported
  839
+fubarino_mini_dbg.bootloader.unlock_bits=0x3F
  840
+fubarino_mini_dbg.bootloader.lock_bits=0x0F
  841
+
  842
+fubarino_mini_dbg.build.mcu=32MX250F128D
  843
+fubarino_mini_dbg.build.f_cpu=40000000L
  844
+fubarino_mini_dbg.build.core=pic32
  845
+fubarino_mini_dbg.build.variant=Fubarino_Mini
  846
+
  847
+############################################################
636 848
 quick240_usb_pic32.name=PONTECH quicK240
637 849
 
638 850
 # new items
56  hardware/pic32/cores/pic32/HardwareSerial.cpp
@@ -58,14 +58,17 @@
58 58
 //*	Nov  1,	2011	<MLS> Also fixed some other compatibilty issues
59 59
 //* Nov 12, 2012	<GeneApperson> Rewrite for board variant support
60 60
 //* Sep  8, 2012    <BrianSchmalz> Fix dropping bytes on USB RX bug
  61
+//*	Jul 26, 2012	<GeneApperson> Added PPS support for PIC32MX1xx/MX2xx devices
61 62
 //************************************************************************
  63
+#ifndef __LANGUAGE_C__
62 64
 #define __LANGUAGE_C__
63  
-
  65
+#endif
64 66
 
65 67
 #include <stdio.h>
66 68
 #include <string.h>
67 69
 #include <inttypes.h>
68 70
 
  71
+#include <p32xxxx.h>
69 72
 #include <plib.h>
70 73
 
71 74
 #include "wiring.h"
@@ -109,15 +112,26 @@
109 112
 **		any global variables used by the object.
110 113
 */
111 114
 
112  
-HardwareSerial::HardwareSerial(p32_uart * uartP, int irqP, int vecP, int iplP, int splP)
  115
+#if defined(__PIC32MX1XX__) || defined(__PIC32MX2XX__)
  116
+HardwareSerial::HardwareSerial(p32_uart * uartT, int irqT, int vecT, int iplT, int splT, int pinT, int pinR, ppsFunctionType ppsT, ppsFunctionType ppsR)
  117
+#else
  118
+HardwareSerial::HardwareSerial(p32_uart * uartT, int irqT, int vecT, int iplT, int splT)
  119
+#endif
113 120
 {
114  
-	uart = uartP;
115  
-	irq  = irqP;
116  
-	vec  = vecP;
117  
-	irq  = (uint8_t)irqP;
118  
-	vec  = (uint8_t)vecP;
119  
-	ipl  = (uint8_t)iplP;
120  
-	spl  = (uint8_t)splP;
  121
+	uart = uartT;
  122
+	irq  = irqT;
  123
+	vec  = vecT;
  124
+	irq  = (uint8_t)irqT;
  125
+	vec  = (uint8_t)vecT;
  126
+	ipl  = (uint8_t)iplT;
  127
+	spl  = (uint8_t)splT;
  128
+
  129
+#if defined(__PIC32MX1XX__) || defined(__PIC32MX2XX__)
  130
+	pinTx = (uint8_t)pinT;
  131
+	pinRx = (uint8_t)pinR;
  132
+	ppsTx = ppsT;
  133
+	ppsRx = ppsR;
  134
+#endif
121 135
 
122 136
 	/* The interrupt flag and enable control register addresses and
123 137
 	** the bit numbers for the flag bits can be computed from the
@@ -167,6 +181,16 @@ void HardwareSerial::begin(unsigned long baudRate)
167 181
 	*/
168 182
 	flush();
169 183
 
  184
+#if defined(__PIC32MX1XX__) || defined(__PIC32MX2XX__)
  185
+	/* Map the UART TX to the appropriate pin.
  186
+	*/
  187
+    mapPps(pinTx, ppsTx);
  188
+
  189
+	/* Map the UART RX to the appropriate pin.
  190
+	*/
  191
+    mapPps(pinRx, ppsRx);
  192
+#endif
  193
+
170 194
 	/* Compute the address of the interrupt priority control
171 195
 	** registers used by this UART
172 196
 	*/
@@ -888,22 +912,36 @@ void __ISR(_SER7_VECTOR, _SER7_IPL_ISR) IntSer7Handler(void)
888 912
 */
889 913
 USBSerial		Serial(&rx_bufferUSB);
890 914
 #if defined(_SER0_BASE)
  915
+#if defined(__PIC32MX1XX__) || defined(__PIC32MX2XX__)
  916
+HardwareSerial Serial0((p32_uart *)_SER0_BASE, _SER0_IRQ, _SER0_VECTOR, _SER0_IPL, _SER0_SPL, _SER0_TX_PIN, _SER0_RX_PIN, _SER0_TX_OUT, _SER0_RX_IN);
  917
+#else
891 918
 HardwareSerial Serial0((p32_uart *)_SER0_BASE, _SER0_IRQ, _SER0_VECTOR, _SER0_IPL, _SER0_SPL);
892 919
 #endif
  920
+#endif
893 921
 
894 922
 #else
895 923
 /* If we're not using USB for serial, then hardware serial port 0
896 924
 ** gets instantiated as Serial.
  925
+** NOTE: PIC32MX1xx/2xx devices only have 2 UARTS, so we're not defining more variant
  926
+** object instances for those devices.
897 927
 */
898 928
 #if defined(_SER0_BASE)
  929
+#if defined(__PIC32MX1XX__) || defined(__PIC32MX2XX__)
  930
+HardwareSerial Serial((p32_uart *)_SER0_BASE, _SER0_IRQ, _SER0_VECTOR, _SER0_IPL, _SER0_SPL, _SER0_TX_PIN, _SER0_RX_PIN, _SER0_TX_OUT, _SER0_RX_IN);
  931
+#else
899 932
 HardwareSerial Serial((p32_uart *)_SER0_BASE, _SER0_IRQ, _SER0_VECTOR, _SER0_IPL, _SER0_SPL);
900 933
 #endif
  934
+#endif
901 935
 
902 936
 #endif	//defined(_USB) && defined(_USE_USB_FOR_SERIAL_)
903 937
 
904 938
 #if defined(_SER1_BASE)
  939
+#if defined(__PIC32MX1XX__) || defined(__PIC32MX2XX__)
  940
+HardwareSerial Serial1((p32_uart *)_SER1_BASE, _SER1_IRQ, _SER1_VECTOR, _SER1_IPL, _SER1_SPL, _SER1_TX_PIN, _SER1_RX_PIN, _SER1_TX_OUT, _SER1_RX_IN);
  941
+#else
905 942
 HardwareSerial Serial1((p32_uart *)_SER1_BASE, _SER1_IRQ, _SER1_VECTOR, _SER1_IPL, _SER1_SPL);
906 943
 #endif
  944
+#endif
907 945
 
908 946
 #if defined(_SER2_BASE)
909 947
 HardwareSerial Serial2((p32_uart *)_SER2_BASE, _SER2_IRQ, _SER2_VECTOR, _SER2_IPL, _SER2_SPL);
13  hardware/pic32/cores/pic32/HardwareSerial.h
@@ -18,6 +18,7 @@
18 18
 //*	Nov  1,	2011	<MLS> Issue #140, HardwareSerial not derived from Stream 
19 19
 //*	Nov  1,	2011	<MLS> Also fixed some other compatibilty issues
20 20
 //* Nov 12, 2001	<GeneApperson> Rewrite for board variant support
  21
+//*	Jul 26, 2012	<GeneApperson> Added PPS support for PIC32MX1xx/MX2xx devices
21 22
 //************************************************************************
22 23
 /*
23 24
   HardwareSerial.h - Hardware serial library for Wiring
@@ -40,7 +41,9 @@
40 41
 
41 42
 #ifndef HardwareSerial_h
42 43
 #define HardwareSerial_h
  44
+#ifndef __LANGUAGE_C__
43 45
 #define __LANGUAGE_C__
  46
+#endif
44 47
 
45 48
 #include <inttypes.h>
46 49
 #include <p32xxxx.h>
@@ -85,6 +88,12 @@ class HardwareSerial : public Stream
85 88
 		uint8_t			vec;		//interrupt vector for the UART
86 89
 		uint8_t			ipl;		//interrupt priority level
87 90
 		uint8_t			spl;		//interrupt sub-priority level
  91
+#if defined(__PIC32MX1XX__) || defined(__PIC32MX2XX__)
  92
+		uint8_t			pinTx;		//digital pin number of TX
  93
+		uint8_t			pinRx;		//digital pin number for RX
  94
+		ppsFunctionType	ppsTx;		//PPS select for UART TX
  95
+		ppsFunctionType	ppsRx;		//PPS select for UART RX
  96
+#endif
88 97
 		p32_regset *	ifs;		//interrupt flag register set
89 98
 		p32_regset *	iec;		//interrupt enable control register set
90 99
 		uint32_t		bit_err;	//err interrupt flag bit
@@ -93,7 +102,11 @@ class HardwareSerial : public Stream
93 102
 		ring_buffer		rx_buffer;	//queue used for UART rx data
94 103
 
95 104
 	public:
  105
+#if defined(__PIC32MX1XX__) || defined(__PIC32MX2XX__)
  106
+		HardwareSerial(p32_uart * uartP, int irq, int vec, int ipl, int spl, int pinT, int pinR, ppsFunctionType ppsT, ppsFunctionType ppsR);
  107
+#else
96 108
 		HardwareSerial(p32_uart * uartP, int irq, int vec, int ipl, int spl);
  109
+#endif
97 110
 
98 111
 		void			doSerialInt(void);
99 112
 
2  hardware/pic32/cores/pic32/HardwareSerial_cdcacm.c
@@ -211,7 +211,7 @@ int buffersNeeded;
211 211
 int m;
212 212
 int previousInterrutLevel;
213 213
 		
214  
-	//ASSERT(length);
  214
+	// ASSERT(length);
215 215
 
216 216
 	if (! gCdcacm_attached || gDiscard || (length <= 0))
217 217
 	{
16  hardware/pic32/cores/pic32/HardwareSerial_usb.c
@@ -338,11 +338,16 @@ static byte configuration[CONFIGURATION_DESCRIPTOR_SIZE];
338 338
 	
339 339
 	assert(! usb_in_isr);
340 340
 	assert((usb_in_isr	=	true) ? true : true);
  341
+    assert((usb_in_ticks = ticks) ? true : true);
341 342
 	
342 343
 #ifdef _USE_USB_IRQ_
  344
+#if defined(__PIC32MX2XX__)
  345
+    /// TODO: Plib replacement function should go here
  346
+    IFS1CLR	=	0x00000008; // USBIF
  347
+#else
343 348
 	IFS1CLR	=	0x02000000; // USBIF
344 349
 #endif
345  
-	
  350
+#endif	
346 351
 	// *** device ***
347 352
 	
348 353
 	// if we just transferred a token...
@@ -359,7 +364,7 @@ static byte configuration[CONFIGURATION_DESCRIPTOR_SIZE];
359 364
 		int endpoint2;
360 365
 		short length;
361 366
 		short value;
362  
-		struct bdt *bdt;
  367
+		volatile struct bdt *bdt;
363 368
 		struct setup *setup;
364 369
 		
365 370
 		// we just completed a packet transfer
@@ -751,10 +756,17 @@ void	usb_initialize(void)
751 756
 
752 757
 	// enable int
753 758
 #ifdef _USE_USB_IRQ_
  759
+#if defined(__PIC32MX2XX__)
  760
+    /// TODO: Plib replacement function should go here
  761
+	IEC1bits.USBIE = 1;
  762
+    IPC7bits.USBIP = 6;
  763
+    IPC7bits.USBIS = 0;
  764
+#else
754 765
 	IEC1bits.USBIE = 1;
755 766
 	IPC11bits.USBIP = 6;
756 767
 	IPC11bits.USBIS = 0;
757 768
 #endif
  769
+#endif
758 770
 
759 771
 	MCF_USB_OTG_SOF_THLD = 74;
760 772
 
8  hardware/pic32/cores/pic32/System_Defs.h
@@ -16,6 +16,8 @@
16 16
 /*																		*/
17 17
 /*	11/29/2011(GeneApperson): Created									*/
18 18
 /*	12/20/2011(GeneApperson): Added task manager declarations			*/
  19
+/*	07/26/2012(GeneApperson): Added PPS support for PIC32MX1xx/MX2xx	*/
  20
+/*		devices															*/
19 21
 /*																		*/
20 22
 /************************************************************************/
21 23
 //*	This library is free software; you can redistribute it and/or
@@ -114,9 +116,15 @@
114 116
 
115 117
 /* Core Timer
116 118
 */
  119
+#if defined(__PIC32MX1XX__) || defined(__PIC32MX2XX__)
  120
+#define	_CT_IPL_ISR		IPL7SOFT
  121
+#define	_CT_IPL_IPC		CT_INT_PRIOR_7
  122
+#define	_CT_SPL_IPC		0
  123
+#else
117 124
 #define	_CT_IPL_ISR		IPL7SRS
118 125
 #define	_CT_IPL_IPC		CT_INT_PRIOR_7
119 126
 #define	_CT_SPL_IPC		0
  127
+#endif
120 128
 
121 129
 /* Core Software Interrupts
122 130
 */
2  hardware/pic32/cores/pic32/Tone.cpp
@@ -60,8 +60,8 @@
60 60
 
61 61
 #define	OPT_SYSTEM_INTERNAL
62 62
 #define OPT_BOARD_INTERNAL	//pull in internal symbol definitons
63  
-#include "p32_defs.h"
64 63
 #include "pins_arduino.h"
  64
+#include "p32_defs.h"
65 65
 
66 66
 //	timerx_toggle_count:
67 67
 //	> 0 - duration specified
22  hardware/pic32/cores/pic32/WInterrupts.c
@@ -31,6 +31,7 @@
31 31
 //* Aug  8, 2011	<GeneApperson> completely rewritten (issue #75)
32 32
 //* Aug 30, 2011    <GeneApperson> clear interrupt flag after return from
33 33
 //*                     user interrupt function (issue #109)
  34
+//*	Jul 26, 2012	<GeneApperson> Added PPS support for PIC32MX1xx/MX2xx devices
34 35
 //************************************************************************
35 36
 
36 37
 #include <plib.h>
@@ -41,8 +42,8 @@
41 42
 
42 43
 #define	OPT_SYSTEM_INTERNAL
43 44
 #define OPT_BOARD_INTERNAL	//pull in internal symbol definitons
44  
-#include "p32_defs.h"
45 45
 #include "pins_arduino.h"
  46
+#include "p32_defs.h"
46 47
 
47 48
 #include "WConstants.h"
48 49
 #include "wiring_private.h"
@@ -62,6 +63,25 @@ void attachInterrupt(uint8_t interruptNum, void (*userFunc)(void), int mode)
62 63
 	{
63 64
 	    intFunc[interruptNum]	=	userFunc;
64 65
 
  66
+#if defined(__PIC32MX1XX__) || defined(__PIC32MX2XX__)
  67
+		/* For devices with peripheral pin select (PPS), it is necessary to
  68
+		** map the input function to the pin. This is done by loading the
  69
+		** PPS input select register for the specific interrupt with the value
  70
+		** to select the pin that the interrupt is mapped to as defined by the
  71
+		** board variant file.
  72
+		*/
  73
+		volatile uint32_t *	pps;
  74
+		uint8_t		pin;
  75
+		uint8_t		sel;
  76
+
  77
+		if ((sel = externalIntToInputSelect(interruptNum)) != NOT_PPS_PIN)
  78
+		{
  79
+			pin = externalIntToDigitalPin(interruptNum);
  80
+			pps = ppsInputRegister(sel);
  81
+			*pps = ppsInputSelect(pin);
  82
+		}
  83
+#endif
  84
+
65 85
 		// The active edge is selected via the INTxEP bits in the INTCON register.
66 86
 		// A '0' bit selects falling edge, and a '1' bit select rising edge.
67 87
 		if (mode == FALLING)
165  hardware/pic32/cores/pic32/chipKIT-application-32MX120F032-nobootloader.ld
... ...
@@ -0,0 +1,165 @@
  1
+/* Default linker script, for normal executables */
  2
+OUTPUT_FORMAT("elf32-tradlittlemips")
  3
+OUTPUT_ARCH(pic32mx)
  4
+ENTRY(_reset)
  5
+/*
  6
+ * Provide for a minimum stack and heap size
  7
+ * - _min_stack_size - represents the minimum space that must be made
  8
+ *                     available for the stack.  Can be overridden from
  9
+ *                     the command line using the linker's --defsym option.
  10
+ * - _min_heap_size  - represents the minimum space that must be made
  11
+ *                     available for the heap.  Can be overridden from
  12
+ *                     the command line using the linker's --defsym option.
  13
+ */
  14
+EXTERN (_min_stack_size _min_heap_size)
  15
+PROVIDE(_min_stack_size = 0x800) ;
  16
+PROVIDE(_min_heap_size = 0x800) ;
  17
+
  18
+/*************************************************************************
  19
+ * Processor-specific object file.  Contains SFR definitions.
  20
+ *************************************************************************/
  21
+INPUT("processor.o")
  22
+
  23
+/*************************************************************************
  24
+ * Memory Regions
  25
+ *
  26
+ * Memory regions without attributes cannot be used for orphaned sections.
  27
+ * Only sections specifically assigned to these regions can be allocated
  28
+ * into these regions.
  29
+ *************************************************************************/
  30
+MEMORY
  31
+{
  32
+  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000
  33
+  kseg0_program_mem    (rx)  : ORIGIN = 0x9D001000, LENGTH = 0x6000
  34
+  kseg0_eeprom_mem           : ORIGIN = 0x9D006000, LENGTH = 0x1000
  35
+  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0
  36
+  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0x490 
  37
+  debug_exec_mem             : ORIGIN = 0xBFC00490, LENGTH = 0x760
  38
+  config3                    : ORIGIN = 0xBFC00BF0, LENGTH = 0x4
  39
+  config2                    : ORIGIN = 0xBFC00BF4, LENGTH = 0x4
  40
+  config1                    : ORIGIN = 0xBFC00BF8, LENGTH = 0x4
  41
+  config0                    : ORIGIN = 0xBFC00BFC, LENGTH = 0x4
  42
+  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x2000
  43
+  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000
  44
+  configsfrs                 : ORIGIN = 0xBFC00BF0, LENGTH = 0x10
  45
+}
  46
+
  47
+/*************************************************************************
  48
+ * Memory Address Equates
  49
+ *************************************************************************/
  50
+_ebase_address  	    = ORIGIN(exception_mem);
  51
+_IMAGE_PTR_TABLE       	= _ebase_address + 0x0F8;
  52
+_IMAGE_HEADER_ADDR      = _ebase_address + 0x0FC;
  53
+_GEN_EXCPT_ADDR         = _ebase_address + 0x180;
  54
+_RESET_ADDR             = ORIGIN(kseg1_boot_mem );
  55
+_EEPROM_ADDR            = ORIGIN(kseg0_eeprom_mem);
  56
+_BEV_EXCPT_ADDR         = 0xBFC00380;
  57
+_DBG_EXCPT_ADDR         = 0xBFC00480;
  58
+_DBG_CODE_ADDR          = ORIGIN(debug_exec_mem);
  59
+
  60
+/*************************************************************************
  61
+ *  Bootloader program directives.
  62
+ *  
  63
+ * _IMAGE_TYPE
  64
+ *
  65
+ *  image type:
  66
+ */
  67
+     
  68
+_imageReserved                      = 0x00000000 ;
  69
+_imageMPIDE                         = 0x00000001 ;  /* This is a normal MPIDE sketch                                                                                                    */
  70
+_imageBootFlashBootloader           = 0x00000002 ;  /* This is a boot flash bootloader                                                                                                  */
  71
+_imageProgramFlashBootloader        = 0x00000004 ;  /* This is a program flash bootloader                                                                                               */
  72
+_imageSplitFlashBootloader          = 0x00000008 ;  /* This has bootloader code in both boot and program flash                                                                          */
  73
+
  74
+ /*
  75
+ *  Instructions for the bootloader
  76
+ */
  77
+                                                                       
  78
+_imageFullFlashEraseLess4KEEProm    = 0x00010000 ;  /* The original bootloader method of erasing all of program flash except the last 4K reserved for eeprom                            */
  79
+_imageJustInTimeFlashErase          = 0x00020000 ;  /* Only flash pages written too needed by the sketch is erased                                                                      */
  80
+_imageLinkerSpecifiedFlashErase     = 0x00040000 ;  /* The linker defines the flash range to erase                                                                                      */
  81
+_imageFullFlashErase                = 0x00080000 ;  /* All of flash is erased                                                                                                           */
  82
+_imageExecutionJumpAddress          = 0x01000000 ;  /* the bootloader will jump to the execution jump address immediately after programming                                             */
  83
+_imageExecutionJumpToFirstInFlash   = 0x02000000 ;  /* the bootloader will jump to the first sketch loaded in flash ignoring the execution jump address immediately after programming   */
  84
+ 
  85
+/*  
  86
+ * _IMAGE_FLASH_SIZE 
  87
+ *
  88
+ *      Typically _imageJustInTimeFlashErase is selected to just erase the pages
  89
+ *      of flash that code is written too; thus leaving all other flash pages untouched.
  90
+ *  
  91
+ *      If _imageLinkerSpecifiedFlashErase set, then the range
  92
+ *      starting from _ebase_address for _IMAGE_FLASH_SIZE bytes are erased.
  93
+ *
  94
+ *      If _imageFullFlashErase is specified, than the whole flash
  95
+ *      as known by the bootloader will be erased. This will erase eeprom as well
  96
+ *
  97
+ *      if _imageFullFlashEraseLess4KEEProm is set, all of flash less the last 4K is
  98
+ *      erased, this is the old default. This bit could be set to make a program flash bootloader
  99
+ *      erasing everything but the old flash. If NOTHING is set, this will be the default as this is the old behavior.
  100
+ *  
  101
+ *  _JUMP_ADDR
  102
+ *  
  103
+ *      This is the address that the bootloader will jump to start execution
  104
+ *      of the sketch. This is almost always _RESET_ADDR.
  105
+ *
  106
+ *      However, you can specify an alternate entry execution point for example
  107
+ *      if you have alternate starup code that, say, shared
  108
+ *      the runtime with other sketches or needed some kind of specific handling
  109
+ *
  110
+ *      Immediately after programming (avrdude upload) the bootloader will typically
  111
+ *      jump to the just loaded sketch, no matter where it was loaded in flash.
  112
+ *      _imageExecutionJumpToFirstInFlash will tell the bootloader to jump to the first
  113
+ *      sketch in flash even if the just loaded one is not at the beginning of flash.
  114
+ *      This is useful when programming sketches in slots of flash and then always
  115
+ *      jumping to the program-flash loader (vector sketch) as if the board was just reset.
  116
+ *      This bit does not effect jumping to a sketch already in flash after reset.
  117
+ *      As of today, after reset, the first program in flash will always be jumped to.
  118
+ *
  119
+ *************************************************************************/
  120
+ _IMAGE_TYPE            = _imageMPIDE | _imageJustInTimeFlashErase | _imageExecutionJumpAddress;
  121
+ _IMAGE_FLASH_SIZE      = LENGTH(exception_mem) + LENGTH(kseg0_program_mem);
  122
+_JUMP_ADDR              = _RESET_ADDR;
  123
+
  124
+SECTIONS
  125
+{
  126
+  .config_BFC00BF0 : {
  127
+    LONG(0xCFFFFFFF)
  128
+  } > config3
  129
+  .config_BFC00BF4 : {
  130
+    LONG(0xFFF9FFD9)
  131
+  } > config2
  132
+  .config_BFC00BF8 : {
  133
+    LONG(0xFF6ACDDB)
  134
+  } > config1
  135
+  .config_BFC00BFC : {
  136
+    LONG(0x7FFFFFFB)
  137
+  } > config0
  138
+}
  139
+
  140
+SECTIONS
  141
+{
  142
+  .bev_excpt _BEV_EXCPT_ADDR :
  143
+  {
  144
+    KEEP(*(.bev_handler))
  145
+  } > kseg1_boot_mem
  146
+
  147
+  .dbg_excpt _DBG_EXCPT_ADDR (NOLOAD) :
  148
+  {
  149
+    . += (DEFINED (_DEBUGGER) ? 0x8 : 0x0);
  150
+  } > kseg1_boot_mem
  151
+
  152
+  .dbg_code _DBG_CODE_ADDR (NOLOAD) :
  153
+  {
  154
+    . += (DEFINED (_DEBUGGER) ? LENGTH(debug_exec_mem) : 0x0);
  155
+  } > debug_exec_mem
  156
+
  157
+  /* Boot Sections */
  158
+  .reset _RESET_ADDR :
  159
+  {
  160
+    KEEP(*(.reset))
  161
+  } > kseg1_boot_mem
  162
+}
  163
+
  164
+/* From here out every linker script is the same, so just include it */
  165
+/*INCLUDE "chipKIT-application-COMMON.ld"*/
268  hardware/pic32/cores/pic32/chipKIT-application-32MX120F032.ld 100755 → 100644
... ...
@@ -1,134 +1,134 @@
1  
-/* Default linker script, for normal executables */
2  
-OUTPUT_FORMAT("elf32-tradlittlemips")
3  
-OUTPUT_ARCH(pic32mx)
4  
-ENTRY(_reset)
5  
-/*
6  
- * Provide for a minimum stack and heap size
7  
- * - _min_stack_size - represents the minimum space that must be made
8  
- *                     available for the stack.  Can be overridden from
9  
- *                     the command line using the linker's --defsym option.
10  
- * - _min_heap_size  - represents the minimum space that must be made
11  
- *                     available for the heap.  Can be overridden from
12  
- *                     the command line using the linker's --defsym option.
13  
- */
14  
-EXTERN (_min_stack_size _min_heap_size)
15  
-PROVIDE(_min_stack_size = 0x800) ;
16  
-PROVIDE(_min_heap_size = 0x800) ;
17  
-
18  
-/*************************************************************************
19  
- * Processor-specific object file.  Contains SFR definitions.
20  
- *************************************************************************/
21  
-INPUT("processor.o")
22  
-
23  
-/*************************************************************************
24  
- * Memory Regions
25  
- *
26  
- * Memory regions without attributes cannot be used for orphaned sections.
27  
- * Only sections specifically assigned to these regions can be allocated
28  
- * into these regions.
29  
- *************************************************************************/
30  
-MEMORY
31  
-{
32  
-  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000
33  
-  kseg0_program_mem    (rx)  : ORIGIN = 0x9D001000, LENGTH = 0x6000
34  
-  kseg0_eeprom_mem           : ORIGIN = 0x9D006000, LENGTH = 0x1000
35  
-  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0
36  
-  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0 
37  
-  debug_exec_mem             : ORIGIN = 0xBFC00490, LENGTH = 0
38  
-  config3                    : ORIGIN = 0xBFC00BF0, LENGTH = 0x4
39  
-  config2                    : ORIGIN = 0xBFC00BF4, LENGTH = 0x4
40  
-  config1                    : ORIGIN = 0xBFC00BF8, LENGTH = 0x4
41  
-  config0                    : ORIGIN = 0xBFC00BFC, LENGTH = 0x4
42  
-  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x2000
43  
-  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000
44  
-  configsfrs                 : ORIGIN = 0xBFC00BF0, LENGTH = 0x10
45  
-}
46  
-
47  
-/*************************************************************************
48  
- * Memory Address Equates
49  
- *************************************************************************/
50  
-_ebase_address  	    = ORIGIN(exception_mem);
51  
-_IMAGE_PTR_TABLE       	= _ebase_address + 0x0F8;
52  
-_IMAGE_HEADER_ADDR      = _ebase_address + 0x0FC;
53  
-_GEN_EXCPT_ADDR         = _ebase_address + 0x180;
54  
-_RESET_ADDR             = ORIGIN(kseg0_program_mem);
55  
-_EEPROM_ADDR            = ORIGIN(kseg0_eeprom_mem);
56  
-_BEV_EXCPT_ADDR         = 0xBFC00380;
57  
-_DBG_EXCPT_ADDR         = 0xBFC00480;
58  
-_DBG_CODE_ADDR          = ORIGIN(debug_exec_mem);
59  
-
60  
-/*************************************************************************
61  
- *  Bootloader program directives.
62  
- *  
63  
- * _IMAGE_TYPE
64  
- *
65  
- *  image type:
66  
- */
67  
-     
68  
-_imageReserved                      = 0x00000000 ;
69  
-_imageMPIDE                         = 0x00000001 ;  /* This is a normal MPIDE sketch                                                                                                    */
70  
-_imageBootFlashBootloader           = 0x00000002 ;  /* This is a boot flash bootloader                                                                                                  */
71  
-_imageProgramFlashBootloader        = 0x00000004 ;  /* This is a program flash bootloader                                                                                               */
72  
-_imageSplitFlashBootloader          = 0x00000008 ;  /* This has bootloader code in both boot and program flash                                                                          */
73  
-
74  
- /*
75  
- *  Instructions for the bootloader
76  
- */
77  
-                                                                       
78  
-_imageFullFlashEraseLess4KEEProm    = 0x00010000 ;  /* The original bootloader method of erasing all of program flash except the last 4K reserved for eeprom                            */
79  
-_imageJustInTimeFlashErase          = 0x00020000 ;  /* Only flash pages written too needed by the sketch is erased                                                                      */
80  
-_imageLinkerSpecifiedFlashErase     = 0x00040000 ;  /* The linker defines the flash range to erase                                                                                      */
81  
-_imageFullFlashErase                = 0x00080000 ;  /* All of flash is erased                                                                                                           */
82  
-_imageExecutionJumpAddress          = 0x01000000 ;  /* the bootloader will jump to the execution jump address immediately after programming                                             */
83  
-_imageExecutionJumpToFirstInFlash   = 0x02000000 ;  /* the bootloader will jump to the first sketch loaded in flash ignoring the execution jump address immediately after programming   */
84  
- 
85  
-/*  
86  
- * _IMAGE_FLASH_SIZE 
87  
- *
88  
- *      Typically _imageJustInTimeFlashErase is selected to just erase the pages
89  
- *      of flash that code is written too; thus leaving all other flash pages untouched.
90  
- *  
91  
- *      If _imageLinkerSpecifiedFlashErase set, then the range
92  
- *      starting from _ebase_address for _IMAGE_FLASH_SIZE bytes are erased.
93  
- *
94  
- *      If _imageFullFlashErase is specified, than the whole flash
95  
- *      as known by the bootloader will be erased. This will erase eeprom as well
96  
- *
97  
- *      if _imageFullFlashEraseLess4KEEProm is set, all of flash less the last 4K is
98  
- *      erased, this is the old default. This bit could be set to make a program flash bootloader
99  
- *      erasing everything but the old flash. If NOTHING is set, this will be the default as this is the old behavior.
100  
- *  
101  
- *  _JUMP_ADDR
102  
- *  
103  
- *      This is the address that the bootloader will jump to start execution
104  
- *      of the sketch. This is almost always _RESET_ADDR.
105  
- *
106  
- *      However, you can specify an alternate entry execution point for example
107  
- *      if you have alternate starup code that, say, shared
108  
- *      the runtime with other sketches or needed some kind of specific handling
109  
- *
110  
- *      Immediately after programming (avrdude upload) the bootloader will typically
111  
- *      jump to the just loaded sketch, no matter where it was loaded in flash.
112  
- *      _imageExecutionJumpToFirstInFlash will tell the bootloader to jump to the first
113  
- *      sketch in flash even if the just loaded one is not at the beginning of flash.
114  
- *      This is useful when programming sketches in slots of flash and then always
115  
- *      jumping to the program-flash loader (vector sketch) as if the board was just reset.
116  
- *      This bit does not effect jumping to a sketch already in flash after reset.
117  
- *      As of today, after reset, the first program in flash will always be jumped to.
118  
- *
119  
- *************************************************************************/
120  
- _IMAGE_TYPE            = _imageMPIDE | _imageJustInTimeFlashErase | _imageExecutionJumpAddress;
121  
- _IMAGE_FLASH_SIZE      = LENGTH(exception_mem) + LENGTH(kseg0_program_mem);
122  
-_JUMP_ADDR              = _RESET_ADDR;
123  
-
124  
-SECTIONS
125  
-{
126  
-  /* Boot Sections */
127  
-  .reset _RESET_ADDR :
128  
-  {
129  
-    KEEP(*(.reset))
130  
-  } > kseg0_program_mem
131  
-}
132  
-
133  
-/* From here out every linker script is the same, so just include it */
134  
-/*INCLUDE "chipKIT-application-COMMON.ld"*/
  1
+/* Default linker script, for normal executables */
  2
+OUTPUT_FORMAT("elf32-tradlittlemips")
  3
+OUTPUT_ARCH(pic32mx)
  4
+ENTRY(_reset)
  5
+/*
  6
+ * Provide for a minimum stack and heap size
  7
+ * - _min_stack_size - represents the minimum space that must be made
  8
+ *                     available for the stack.  Can be overridden from
  9
+ *                     the command line using the linker's --defsym option.
  10
+ * - _min_heap_size  - represents the minimum space that must be made
  11
+ *                     available for the heap.  Can be overridden from
  12
+ *                     the command line using the linker's --defsym option.
  13
+ */
  14
+EXTERN (_min_stack_size _min_heap_size)