{"payload":{"header_redesign_enabled":false,"results":[{"id":"226946481","archived":false,"color":"#e4cc98","followers":38,"has_funding_file":false,"hl_name":"chipsalliance/Cores-SweRV_fpga","hl_trunc_description":null,"language":"Tcl","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":226946481,"name":"Cores-SweRV_fpga","owner_id":46612642,"owner_login":"chipsalliance","updated_at":"2020-02-07T10:20:38.565Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":57,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Achipsalliance%252FCores-SweRV_fpga%2B%2Blanguage%253ATcl","metadata":null,"csrf_tokens":{"/chipsalliance/Cores-SweRV_fpga/star":{"post":"rbJM9tEedNKxKfiLyVCyB6agNncGa6bQHz-1DupUjQ9SOnj30Rxjel3HIB5AF2zuqCe0S8JASsw5S24O6dlwpw"},"/chipsalliance/Cores-SweRV_fpga/unstar":{"post":"KKjgX3fQphNVBJOpcAsLM-1F7C3fmXGf7mh9ZeucDxRq_L30i5VxoqOLbzk48XB8-yPf9poz1b4unYQ-V6FNEg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"NWhUFkscsUjTaTVOLZC5JW5Q6ZSLEQMiyavm0-LltFlMUNMCXA6xhxtavMh73BtFTWF4VoVfhlbFDz0WdjEg6g"}}},"title":"Repository search results"}