From 1b890bf0fbae085e6ae934b3e04697d24827f30c Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Fri, 12 Jan 2024 14:35:23 -0800 Subject: [PATCH] file level param binding --- include/Surelog/DesignCompile/UhdmWriter.h | 1 + src/DesignCompile/UhdmWriter.cpp | 16 +- tests/ConstCapital/ConstCapital.log | 16 - tests/FileLocalParam/FileLocalParam.log | 274 ++++++++++++++++++ tests/FileLocalParam/FileLocalParam.sl | 1 + tests/FileLocalParam/dut.sv | 11 + .../tests/CoresSweRVMP/CoresSweRVMP.log | 4 +- third_party/tests/Scr1/Scr1.log | 2 +- third_party/tests/Scr1SvTests/Scr1SvTests.log | 2 +- 9 files changed, 306 insertions(+), 21 deletions(-) create mode 100644 tests/FileLocalParam/FileLocalParam.log create mode 100644 tests/FileLocalParam/FileLocalParam.sl create mode 100644 tests/FileLocalParam/dut.sv diff --git a/include/Surelog/DesignCompile/UhdmWriter.h b/include/Surelog/DesignCompile/UhdmWriter.h index 6f761b317d..3618aec017 100644 --- a/include/Surelog/DesignCompile/UhdmWriter.h +++ b/include/Surelog/DesignCompile/UhdmWriter.h @@ -131,6 +131,7 @@ class UhdmWriter final { CompileDesign* const m_compileDesign; Design* const m_design; + UHDM::design* m_uhdmDesign; ComponentMap m_componentMap; CompileHelper m_helper; }; diff --git a/src/DesignCompile/UhdmWriter.cpp b/src/DesignCompile/UhdmWriter.cpp index 5e2a333a38..e9cd4b0141 100644 --- a/src/DesignCompile/UhdmWriter.cpp +++ b/src/DesignCompile/UhdmWriter.cpp @@ -165,7 +165,7 @@ std::string UhdmWriter::builtinGateName(VObjectType type) { } UhdmWriter::UhdmWriter(CompileDesign* compiler, Design* design) - : m_compileDesign(compiler), m_design(design) { + : m_compileDesign(compiler), m_design(design), m_uhdmDesign(nullptr) { m_helper.seterrorReporting( m_compileDesign->getCompiler()->getErrorContainer(), m_compileDesign->getCompiler()->getSymbolTable()); @@ -3723,6 +3723,19 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) { if (ref->Actual_group()) break; } } + + if (!ref->Actual_group()) { + design* d = m_uhdmDesign; + if (auto params = d->Parameters()) { + for (auto decl : *params) { + if (decl->VpiName() == name) { + ref->Actual_group(decl); + break; + } + } + } + } + if (!ref->Actual_group()) { if (mod) { if (auto elem = mod->getDesignElement()) { @@ -4696,6 +4709,7 @@ vpiHandle UhdmWriter::write(PathId uhdmFileId) { design* d = nullptr; if (m_design) { d = s.MakeDesign(); + m_uhdmDesign = d; designHandle = reinterpret_cast(new uhdm_handle(uhdmdesign, d)); std::string designName = "unnamed"; auto topLevelModules = m_design->getTopLevelModuleInstances(); diff --git a/tests/ConstCapital/ConstCapital.log b/tests/ConstCapital/ConstCapital.log index 5e7f0438e6..ebf8b9266c 100644 --- a/tests/ConstCapital/ConstCapital.log +++ b/tests/ConstCapital/ConstCapital.log @@ -131,7 +131,6 @@ gen_if 2 gen_scope 4 gen_scope_array 4 int_typespec 7 -logic_net 2 module_inst 7 operation 4 param_assign 4 @@ -149,7 +148,6 @@ gen_if 2 gen_scope 6 gen_scope_array 6 int_typespec 7 -logic_net 2 module_inst 9 operation 4 param_assign 4 @@ -178,20 +176,6 @@ design: (work@test) \_design: (work@test) |vpiFullName:work@test |vpiDefName:work@test - |vpiNet: - \_logic_net: (work@test.foo), line:10:5, endln:10:8 - |vpiParent: - \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:8:1, endln:19:10 - |vpiName:foo - |vpiFullName:work@test.foo - |vpiNetType:1 - |vpiNet: - \_logic_net: (work@test.foo2), line:15:5, endln:15:9 - |vpiParent: - \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/ConstCapital/dut.sv, line:8:1, endln:19:10 - |vpiName:foo2 - |vpiFullName:work@test.foo2 - |vpiNetType:1 |vpiGenStmt: \_gen_if: , line:10:1, endln:10:3 |vpiParent: diff --git a/tests/FileLocalParam/FileLocalParam.log b/tests/FileLocalParam/FileLocalParam.log new file mode 100644 index 0000000000..34d6a36066 --- /dev/null +++ b/tests/FileLocalParam/FileLocalParam.log @@ -0,0 +1,274 @@ +[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/FileLocalParam/slpp_all/surelog.log". +AST_DEBUG_BEGIN +LIB: work +FILE: ${SURELOG_DIR}/tests/FileLocalParam/dut.sv +n<> u<0> t<_INVALID_> f<0> l<0:0> +n<> u<1> t p<69> s<68> l<1:1> el<1:0> +n<> u<2> t p<12> s<11> l<1:25> el<1:25> +n u<3> t p<10> s<9> l<1:25> el<1:31> +n<16> u<4> t p<5> l<1:56> el<1:58> +n<> u<5> t p<6> c<4> l<1:56> el<1:58> +n<> u<6> t p<7> c<5> l<1:56> el<1:58> +n<> u<7> t p<8> c<6> l<1:56> el<1:58> +n<> u<8> t p<9> c<7> l<1:56> el<1:58> +n<> u<9> t p<10> c<8> l<1:56> el<1:58> +n<> u<10> t p<11> c<3> l<1:25> el<1:58> +n<> u<11> t p<12> c<10> l<1:25> el<1:58> +n<> u<12> t p<13> c<2> l<1:1> el<1:58> +n<> u<13> t p<14> c<12> l<1:1> el<1:60> +n<> u<14> t p<15> c<13> l<1:1> el<1:60> +n<> u<15> t p<68> c<14> s<42> l<1:1> el<1:60> +n u<16> t p<17> l<3:13> el<3:19> +n<> u<17> t p<18> c<16> l<3:13> el<3:19> +n<> u<18> t p<19> c<17> l<3:13> el<3:19> +n<> u<19> t p<24> c<18> s<23> l<3:13> el<3:19> +n<0> u<20> t p<21> l<3:20> el<3:21> +n<> u<21> t p<22> c<20> l<3:20> el<3:21> +n<> u<22> t p<23> c<21> l<3:20> el<3:21> +n<> u<23> t p<24> c<22> l<3:20> el<3:21> +n<> u<24> t p<25> c<19> l<3:13> el<3:21> +n<> u<25> t p<26> c<24> l<3:12> el<3:22> +n<> u<26> t p<39> c<25> s<38> l<3:12> el<3:22> +n u<27> t p<37> s<36> l<3:23> el<3:26> +n u<28> t p<29> l<4:3> el<4:9> +n<> u<29> t p<30> c<28> l<4:3> el<4:9> +n<> u<30> t p<31> c<29> l<4:3> el<4:9> +n<> u<31> t p<32> c<30> l<4:3> el<4:9> +n<> u<32> t p<33> c<31> l<3:33> el<5:48> +n<> u<33> t p<34> c<32> l<3:33> el<5:48> +n<> u<34> t p<35> c<33> l<3:33> el<5:48> +n<> u<35> t p<36> c<34> l<3:33> el<5:48> +n<> u<36> t p<37> c<35> l<3:33> el<5:48> +n<> u<37> t p<38> c<27> l<3:23> el<5:48> +n<> u<38> t p<39> c<37> l<3:23> el<5:48> +n<> u<39> t p<40> c<26> l<3:1> el<5:48> +n<> u<40> t p<41> c<39> l<3:1> el<5:49> +n<> u<41> t p<42> c<40> l<3:1> el<5:49> +n<> u<42> t p<68> c<41> s<67> l<3:1> el<5:49> +n u<43> t p<47> s<44> l<7:1> el<7:7> +n u<44> t p<47> s<46> l<7:8> el<7:11> +n<> u<45> t p<46> l<7:12> el<7:12> +n<> u<46> t p<47> c<45> l<7:11> el<7:13> +n<> u<47> t p<66> c<43> s<64> l<7:1> el<7:14> +n<> u<48> t p<58> s<57> l<9:13> el<9:13> +n u<49> t p<56> s<55> l<9:13> el<9:14> +n u<50> t p<51> l<9:16> el<9:19> +n<> u<51> t p<52> c<50> l<9:16> el<9:19> +n<> u<52> t p<53> c<51> l<9:16> el<9:19> +n<> u<53> t p<54> c<52> l<9:16> el<9:19> +n<> u<54> t p<55> c<53> l<9:16> el<9:19> +n<> u<55> t p<56> c<54> l<9:16> el<9:19> +n<> u<56> t p<57> c<49> l<9:13> el<9:19> +n<> u<57> t p<58> c<56> l<9:13> el<9:19> +n<> u<58> t p<59> c<48> l<9:3> el<9:19> +n<> u<59> t p<60> c<58> l<9:3> el<9:20> +n<> u<60> t p<61> c<59> l<9:3> el<9:20> +n<> u<61> t p<62> c<60> l<9:3> el<9:20> +n<> u<62> t p<63> c<61> l<9:3> el<9:20> +n<> u<63> t p<64> c<62> l<9:3> el<9:20> +n<> u<64> t p<66> c<63> s<65> l<9:3> el<9:20> +n<> u<65> t p<66> l<11:1> el<11:10> +n<> u<66> t p<67> c<47> l<7:1> el<11:10> +n<> u<67> t p<68> c<66> l<7:1> el<11:10> +n<> u<68> t p<69> c<15> l<1:1> el<11:10> +n<> u<69> t c<1> l<1:1> el<11:10> +AST_DEBUG_END +[WRN:PA0205] ${SURELOG_DIR}/tests/FileLocalParam/dut.sv:7:1: No timescale set for "top". +[INF:CP0300] Compilation... +[INF:CP0303] ${SURELOG_DIR}/tests/FileLocalParam/dut.sv:7:1: Compile module "work@top". +[INF:EL0526] Design Elaboration... +[NTE:EL0503] ${SURELOG_DIR}/tests/FileLocalParam/dut.sv:7:1: Top level module "work@top". +[NTE:EL0508] Nb Top level modules: 1. +[NTE:EL0509] Max instance depth: 1. +[NTE:EL0510] Nb instances: 1. +[NTE:EL0511] Nb leaf instances: 1. +[INF:UH0706] Creating UHDM Model... +=== UHDM Object Stats Begin (Non-Elaborated Model) === +constant 7 +design 1 +int_typespec 5 +module_inst 5 +operation 3 +param_assign 6 +parameter 6 +range 2 +ref_obj 6 +ref_typespec 8 +=== UHDM Object Stats End === +[INF:UH0707] Elaborating UHDM... +=== UHDM Object Stats Begin (Elaborated Model) === +constant 7 +design 1 +int_typespec 5 +module_inst 5 +operation 3 +param_assign 6 +parameter 6 +range 2 +ref_obj 6 +ref_typespec 8 +=== UHDM Object Stats End === +[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/FileLocalParam/slpp_all/surelog.uhdm ... +[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/FileLocalParam/slpp_all/checker/surelog.chk.html ... +[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/FileLocalParam/slpp_all/surelog.uhdm ... +[INF:UH0711] Decompiling UHDM... +====== UHDM ======= +design: (work@top) +|vpiElaborated:1 +|vpiName:work@top +|uhdmallModules: +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10 + |vpiParent: + \_design: (work@top) + |vpiFullName:work@top + |vpiParameter: + \_parameter: (work@top.D), line:9:13, endln:9:14 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10 + |vpiName:D + |vpiFullName:work@top.D + |vpiParamAssign: + \_param_assign: , line:9:13, endln:9:19 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10 + |vpiRhs: + \_ref_obj: (work@top.MAP), line:9:16, endln:9:19 + |vpiParent: + \_param_assign: , line:9:13, endln:9:19 + |vpiName:MAP + |vpiFullName:work@top.MAP + |vpiActual: + \_parameter: (MAP), line:3:23, endln:3:26 + |vpiLhs: + \_parameter: (work@top.D), line:9:13, endln:9:14 + |vpiDefName:work@top +|vpiParameter: +\_parameter: (AWIDTH), line:1:25, endln:1:31 + |vpiParent: + \_design: (work@top) + |UINT:16 + |vpiTypespec: + \_ref_typespec: (AWIDTH) + |vpiParent: + \_parameter: (AWIDTH), line:1:25, endln:1:31 + |vpiFullName:AWIDTH + |vpiActual: + \_int_typespec: , line:1:1, endln:1:58 + |vpiLocalParam:1 + |vpiName:AWIDTH +|vpiParameter: +\_parameter: (MAP), line:3:23, endln:3:26 + |vpiParent: + \_design: (work@top) + |vpiTypespec: + \_ref_typespec: (MAP) + |vpiParent: + \_parameter: (MAP), line:3:23, endln:3:26 + |vpiFullName:MAP + |vpiActual: + \_int_typespec: , line:3:12, endln:3:22 + |vpiLocalParam:1 + |vpiName:MAP +|vpiParamAssign: +\_param_assign: , line:1:25, endln:1:58 + |vpiParent: + \_design: (work@top) + |vpiRhs: + \_constant: , line:1:56, endln:1:58 + |vpiParent: + \_param_assign: , line:1:25, endln:1:58 + |vpiDecompile:16 + |vpiSize:32 + |UINT:16 + |vpiTypespec: + \_ref_typespec: + |vpiParent: + \_constant: , line:1:56, endln:1:58 + |vpiActual: + \_int_typespec: , line:1:1, endln:1:58 + |vpiConstType:9 + |vpiLhs: + \_parameter: (AWIDTH), line:1:25, endln:1:31 +|vpiParamAssign: +\_param_assign: , line:3:23, endln:5:48 + |vpiParent: + \_design: (work@top) + |vpiRhs: + \_operation: , line:3:33, endln:5:48 + |vpiParent: + \_param_assign: , line:3:23, endln:5:48 + |vpiOpType:33 + |vpiOperand: + \_ref_obj: (AWIDTH), line:4:3, endln:4:9 + |vpiParent: + \_operation: , line:3:33, endln:5:48 + |vpiName:AWIDTH + |vpiLhs: + \_parameter: (MAP), line:3:23, endln:3:26 +|uhdmtopModules: +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10 + |vpiName:work@top + |vpiParameter: + \_parameter: (work@top.D), line:9:13, endln:9:14 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10 + |vpiName:D + |vpiFullName:work@top.D + |vpiParamAssign: + \_param_assign: , line:9:13, endln:9:19 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/FileLocalParam/dut.sv, line:7:1, endln:11:10 + |vpiRhs: + \_ref_obj: (work@top.MAP), line:9:16, endln:9:19 + |vpiParent: + \_param_assign: , line:9:13, endln:9:19 + |vpiName:MAP + |vpiFullName:work@top.MAP + |vpiActual: + \_parameter: (MAP), line:3:23, endln:3:26 + |vpiLhs: + \_parameter: (work@top.D), line:9:13, endln:9:14 + |vpiDefName:work@top + |vpiTop:1 + |vpiTopModule:1 +\_weaklyReferenced: +\_int_typespec: , line:1:1, endln:1:58 +\_int_typespec: , line:3:12, endln:3:22 + |vpiParent: + \_parameter: (MAP), line:3:23, endln:3:26 + |vpiRange: + \_range: , line:3:12, endln:3:22 + |vpiParent: + \_int_typespec: , line:3:12, endln:3:22 + |vpiLeftRange: + \_constant: , line:3:13, endln:3:19 + |vpiParent: + \_range: , line:3:12, endln:3:22 + |vpiDecompile:16 + |vpiSize:32 + |UINT:16 + |vpiTypespec: + \_ref_typespec: (MAP) + |vpiParent: + \_constant: , line:3:13, endln:3:19 + |vpiFullName:MAP + |vpiActual: + \_int_typespec: , line:1:1, endln:1:58 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:3:20, endln:3:21 + |vpiParent: + \_range: , line:3:12, endln:3:22 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_int_typespec: , line:1:1, endln:1:58 + |vpiParent: + \_ref_typespec: (MAP) +=================== +[ FATAL] : 0 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 1 +[ NOTE] : 5 diff --git a/tests/FileLocalParam/FileLocalParam.sl b/tests/FileLocalParam/FileLocalParam.sl new file mode 100644 index 0000000000..b461620aca --- /dev/null +++ b/tests/FileLocalParam/FileLocalParam.sl @@ -0,0 +1 @@ +-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin diff --git a/tests/FileLocalParam/dut.sv b/tests/FileLocalParam/dut.sv new file mode 100644 index 0000000000..6294d1db21 --- /dev/null +++ b/tests/FileLocalParam/dut.sv @@ -0,0 +1,11 @@ +localparam AWIDTH = 16 ; + +localparam [AWIDTH:0] MAP ={ + AWIDTH + }; + +module top(); + + parameter D =MAP; + +endmodule \ No newline at end of file diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index 324c64fb23..a764175951 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -73,8 +73,8 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; [ 43%] Generating 16_dec_decode_ctl.sv [ 50%] Generating 1_lsu_stbuf.sv [ 56%] Generating 2_ahb_to_axi4.sv -[ 62%] Generating 3_rvjtag_tap.sv -[ 68%] Generating 4_dec_tlu_ctl.sv +[ 62%] Generating 4_dec_tlu_ctl.sv +[ 68%] Generating 3_rvjtag_tap.sv [ 75%] Generating 5_lsu_bus_buffer.sv [ 81%] Generating 6_dbg.sv [ 87%] Generating 7_axi4_to_ahb.sv diff --git a/third_party/tests/Scr1/Scr1.log b/third_party/tests/Scr1/Scr1.log index f73dcef66b..7c27ff8e66 100644 --- a/third_party/tests/Scr1/Scr1.log +++ b/third_party/tests/Scr1/Scr1.log @@ -259,7 +259,7 @@ int_var 40 integer_typespec 59 integer_var 3 io_decl 27 -logic_net 2690 +logic_net 2621 logic_typespec 4195 logic_var 828 method_func_call 5 diff --git a/third_party/tests/Scr1SvTests/Scr1SvTests.log b/third_party/tests/Scr1SvTests/Scr1SvTests.log index 7098d5b012..5dd1495956 100644 --- a/third_party/tests/Scr1SvTests/Scr1SvTests.log +++ b/third_party/tests/Scr1SvTests/Scr1SvTests.log @@ -191,7 +191,7 @@ int_var 32 integer_typespec 74 integer_var 3 io_decl 27 -logic_net 2961 +logic_net 2894 logic_typespec 4682 logic_var 1058 method_func_call 4