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Pull requests: chipsalliance/caliptra-rtl

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Pull requests list

[TB] Buffer uC print statements for sim.log
#1120 opened Nov 12, 2025 by clayton8 Loading…
[RTL] Add dynamic/static CG modules
#1111 opened Nov 5, 2025 by clayton8 Loading…
Add IP cell count data to integration spec
#1094 opened Oct 23, 2025 by ravithakurAMD Loading…
1
Caliptra RTL rdc constraints update
#1092 opened Oct 22, 2025 by pjangid30 Loading…
1
[DOC] do not reset caliptra separately from the host controller
#1087 opened Oct 16, 2025 by rob-tetrel Loading…
1
[DOC] Remove 'definition of done' from integration requirements
#1061 opened Sep 29, 2025 by calebofearth Loading…
@ericeilertson
1
[DOC] RDL: list all python requirements
#939 opened Aug 1, 2025 by marnovandermaas Loading…
Brought out reset signals at the interface for necessary reset handline
#922 opened Jul 15, 2025 by jchanga Loading…
2
[VAL] Add DMA tests for missing coverage
#918 opened Jul 7, 2025 by anjpar Loading…
[UVM] Add AXI sub sequences to soc_ifc environment
#831 opened Mar 18, 2025 by upadhyayulakiran Loading…
3
Auto-generation of regression yaml files for Calitpra_top regression runs.
#755 opened Feb 25, 2025 by anjpar Loading…
DCLS integration Future
#737 opened Feb 18, 2025 by kgugala Loading…
1
Add coverage report
#587 opened Sep 10, 2024 by kiryk Loading…
2
Add test for JTAG during uC reset
#554 opened Jul 4, 2024 by robertszczepanski Loading…
Patch 1.0 RTL with Lint Fixes enhancement New feature or request
#518 opened May 17, 2024 by calebofearth Loading…
@calebofearth
9
Fix PC setup after waking from clock gating in Verilator Future
#380 opened Jan 16, 2024 by robertszczepanski Loading…
12
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