From 9a64ac32a249dbbb8371dcacf59d940ebc1c95e9 Mon Sep 17 00:00:00 2001 From: Daniel Resnick Date: Wed, 30 Aug 2023 15:19:19 -0600 Subject: [PATCH] Aggregate literals now materialize const wires (#3515) --- core/src/main/scala/chisel3/Data.scala | 6 ++---- src/test/scala/chiselTests/BundleLiteralSpec.scala | 8 ++++++++ src/test/scala/chiselTests/VecLiteralSpec.scala | 8 ++++++++ 3 files changed, 18 insertions(+), 4 deletions(-) diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala index fd0111a43ef..e996f388ed9 100644 --- a/core/src/main/scala/chisel3/Data.scala +++ b/core/src/main/scala/chisel3/Data.scala @@ -634,14 +634,12 @@ abstract class Data extends BaseType with SourceInfoDoc { case Some(BundleLitBinding(litMap)) => litMap.get(this) match { case Some(litArg) => litArg - // TODO make a Const once const is supported in firtool - case _ => materializeWire() // FIXME FIRRTL doesn't have Bundle literal expressions + case _ => materializeWire(true) // FIXME FIRRTL doesn't have Bundle literal expressions } case Some(VecLitBinding(litMap)) => litMap.get(this) match { case Some(litArg) => litArg - // TODO make a Const once const is supported in firtool - case _ => materializeWire() // FIXME FIRRTL doesn't have Vec literal expressions + case _ => materializeWire(true) // FIXME FIRRTL doesn't have Vec literal expressions } case Some(DontCareBinding()) => materializeWire() // FIXME FIRRTL doesn't have a DontCare expression so materialize a Wire diff --git a/src/test/scala/chiselTests/BundleLiteralSpec.scala b/src/test/scala/chiselTests/BundleLiteralSpec.scala index fa97346be21..dc849cce406 100644 --- a/src/test/scala/chiselTests/BundleLiteralSpec.scala +++ b/src/test/scala/chiselTests/BundleLiteralSpec.scala @@ -352,4 +352,12 @@ class BundleLiteralSpec extends ChiselFlatSpec with Utils { } } } + + "bundle literals" should "materialize const wires" in { + val chirrtl = ChiselStage.emitCHIRRTL(new Module { + val r = RegInit((new MyBundle).Lit(_.a -> 42.U, _.b -> true.B, _.c -> MyEnum.sB)) + }) + val wire = """wire.*: const \{ a : UInt<8>, b : UInt<1>, c : UInt<1>\}""".r + (chirrtl should include).regex(wire) + } } diff --git a/src/test/scala/chiselTests/VecLiteralSpec.scala b/src/test/scala/chiselTests/VecLiteralSpec.scala index 9e06c3527e2..466c4ab3689 100644 --- a/src/test/scala/chiselTests/VecLiteralSpec.scala +++ b/src/test/scala/chiselTests/VecLiteralSpec.scala @@ -507,4 +507,12 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils { vec.getWidth should be(16 * 2) vec.litValue should be(BigInt("bbbb000a", 16)) } + + "vec literals should materialize const wires" in { + val chirrtl = ChiselStage.emitCHIRRTL(new Module { + val r = RegInit(Vec(2, UInt(4.W)).Lit(0 -> 1.U, 1 -> 2.U)) + }) + val wire = """wire.*: const UInt<4>\[2\]""".r + (chirrtl should include).regex(wire) + } }