From d2ddda4bfe8e6e238398dfd848a578a0740d06a6 Mon Sep 17 00:00:00 2001 From: Jared Barocsi Date: Thu, 15 Jun 2023 14:54:17 -0700 Subject: [PATCH 1/8] Add filesystem path option to SRAM API --- src/main/scala/chisel3/util/SRAM.scala | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/src/main/scala/chisel3/util/SRAM.scala b/src/main/scala/chisel3/util/SRAM.scala index c5e90623dc5..69d5643219e 100644 --- a/src/main/scala/chisel3/util/SRAM.scala +++ b/src/main/scala/chisel3/util/SRAM.scala @@ -5,6 +5,7 @@ import chisel3._ import chisel3.internal.Builder import chisel3.experimental.SourceInfo import chisel3.internal.sourceinfo.{MemTransform, SourceInfoTransform} +import chisel3.util.experimental.loadMemoryFromFileInline import scala.language.reflectiveCalls import scala.language.experimental.macros @@ -116,6 +117,7 @@ object SRAM { * @param numReadPorts The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0 * @param numWritePorts The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0 * @param numReadwritePorts The number of desired read/write ports >= 0, and the above two conditions must hold + * @param contents A filesystem path to a binary file to preload this SRAM's contents with * * @return A new `SRAMInterface` wire containing the control signals for each instantiated port * @note This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle @@ -126,11 +128,12 @@ object SRAM { tpe: T, numReadPorts: Int, numWritePorts: Int, - numReadwritePorts: Int + numReadwritePorts: Int, + contents: Option[String] = None )( implicit sourceInfo: SourceInfo ): SRAMInterface[T] = - memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock) + memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, contents) /** Generates a [[SyncReadMem]] within the current module, connected to an explicit number * of read, write, and read/write ports, with masking capability on all write and read/write ports. @@ -142,6 +145,7 @@ object SRAM { * @param numReadPorts The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0 * @param numWritePorts The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0 * @param numReadwritePorts The number of desired read/write ports >= 0, and the above two conditions must hold + * @param contents A filesystem path to a binary file to preload this SRAM's contents with * * @return A new `SRAMInterface` wire containing the control signals for each instantiated port * @note This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle @@ -152,12 +156,13 @@ object SRAM { tpe: T, numReadPorts: Int, numWritePorts: Int, - numReadwritePorts: Int + numReadwritePorts: Int, + contents: Option[String] = None )( implicit evidence: T <:< Vec[_], sourceInfo: SourceInfo ): SRAMInterface[T] = - masked_memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock) + masked_memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, contents) private def memInterface_impl[T <: Data]( size: BigInt, @@ -165,7 +170,8 @@ object SRAM { )(numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, - clock: Clock + clock: Clock, + contents: Option[String] )( implicit sourceInfo: SourceInfo ): SRAMInterface[T] = { @@ -205,6 +211,8 @@ object SRAM { ) } + contents.map { path: String => loadMemoryFromFileInline(mem, path) } + _out } @@ -214,7 +222,8 @@ object SRAM { )(numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, - clock: Clock + clock: Clock, + contents: Option[String] )( implicit sourceInfo: SourceInfo, evidence: T <:< Vec[_] @@ -261,6 +270,8 @@ object SRAM { ) } + contents.map { path: String => loadMemoryFromFileInline(mem, path) } + _out } From df73594a9fcce159240d23c7a148f1c412c48ae1 Mon Sep 17 00:00:00 2001 From: Jared Barocsi Date: Wed, 21 Jun 2023 13:40:50 -0700 Subject: [PATCH 2/8] Maintain binary compatibility --- src/main/scala/chisel3/util/SRAM.scala | 53 ++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/src/main/scala/chisel3/util/SRAM.scala b/src/main/scala/chisel3/util/SRAM.scala index 69d5643219e..52f8e0c0ced 100644 --- a/src/main/scala/chisel3/util/SRAM.scala +++ b/src/main/scala/chisel3/util/SRAM.scala @@ -135,6 +135,59 @@ object SRAM { ): SRAMInterface[T] = memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, contents) + /** Generates a [[SyncReadMem]] within the current module, connected to an explicit number + * of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, + * it contains at least one read accessor (a read-only or read-write port), and at least one write accessor + * (a write-only or read-write port). + * + * @param size The desired size of the inner `SyncReadMem` + * @tparam T The data type of the memory element + * @param numReadPorts The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0 + * @param numWritePorts The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0 + * @param numReadwritePorts The number of desired read/write ports >= 0, and the above two conditions must hold + * + * @return A new `SRAMInterface` wire containing the control signals for each instantiated port + * @note This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle + * @note Read-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared. + */ + def apply[T <: Data]( + size: BigInt, + tpe: T, + numReadPorts: Int, + numWritePorts: Int, + numReadwritePorts: Int + )( + implicit sourceInfo: SourceInfo + ): SRAMInterface[T] = + memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, None) + + /** Generates a [[SyncReadMem]] within the current module, connected to an explicit number + * of read, write, and read/write ports, with masking capability on all write and read/write ports. + * This SRAM abstraction has both read and write capabilities: that is, it contains at least one read + * accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port). + * + * @param size The desired size of the inner `SyncReadMem` + * @tparam T The data type of the memory element + * @param numReadPorts The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0 + * @param numWritePorts The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0 + * @param numReadwritePorts The number of desired read/write ports >= 0, and the above two conditions must hold + * + * @return A new `SRAMInterface` wire containing the control signals for each instantiated port + * @note This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle + * @note Read-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared. + */ + def masked[T <: Data]( + size: BigInt, + tpe: T, + numReadPorts: Int, + numWritePorts: Int, + numReadwritePorts: Int + )( + implicit evidence: T <:< Vec[_], + sourceInfo: SourceInfo + ): SRAMInterface[T] = + masked_memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, None) + /** Generates a [[SyncReadMem]] within the current module, connected to an explicit number * of read, write, and read/write ports, with masking capability on all write and read/write ports. * This SRAM abstraction has both read and write capabilities: that is, it contains at least one read From 3f32a1c79c1f1c9400a799cb83b42c7768bb09c2 Mon Sep 17 00:00:00 2001 From: Jared Barocsi Date: Wed, 21 Jun 2023 16:57:46 -0700 Subject: [PATCH 3/8] Omit default parameters in API --- src/main/scala/chisel3/util/SRAM.scala | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/main/scala/chisel3/util/SRAM.scala b/src/main/scala/chisel3/util/SRAM.scala index 52f8e0c0ced..fffcd93f963 100644 --- a/src/main/scala/chisel3/util/SRAM.scala +++ b/src/main/scala/chisel3/util/SRAM.scala @@ -117,7 +117,6 @@ object SRAM { * @param numReadPorts The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0 * @param numWritePorts The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0 * @param numReadwritePorts The number of desired read/write ports >= 0, and the above two conditions must hold - * @param contents A filesystem path to a binary file to preload this SRAM's contents with * * @return A new `SRAMInterface` wire containing the control signals for each instantiated port * @note This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle @@ -128,12 +127,11 @@ object SRAM { tpe: T, numReadPorts: Int, numWritePorts: Int, - numReadwritePorts: Int, - contents: Option[String] = None + numReadwritePorts: Int )( implicit sourceInfo: SourceInfo ): SRAMInterface[T] = - memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, contents) + memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, None) /** Generates a [[SyncReadMem]] within the current module, connected to an explicit number * of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, @@ -145,6 +143,7 @@ object SRAM { * @param numReadPorts The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0 * @param numWritePorts The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0 * @param numReadwritePorts The number of desired read/write ports >= 0, and the above two conditions must hold + * @param contents A filesystem path to a binary file to preload this SRAM's contents with * * @return A new `SRAMInterface` wire containing the control signals for each instantiated port * @note This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle @@ -155,11 +154,12 @@ object SRAM { tpe: T, numReadPorts: Int, numWritePorts: Int, - numReadwritePorts: Int + numReadwritePorts: Int, + loadMemoryFile: String )( implicit sourceInfo: SourceInfo ): SRAMInterface[T] = - memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, None) + memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, Some(loadMemoryFile)) /** Generates a [[SyncReadMem]] within the current module, connected to an explicit number * of read, write, and read/write ports, with masking capability on all write and read/write ports. @@ -198,7 +198,7 @@ object SRAM { * @param numReadPorts The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0 * @param numWritePorts The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0 * @param numReadwritePorts The number of desired read/write ports >= 0, and the above two conditions must hold - * @param contents A filesystem path to a binary file to preload this SRAM's contents with + * @param loadMemoryFile A filesystem path to a binary file to preload this SRAM's contents with * * @return A new `SRAMInterface` wire containing the control signals for each instantiated port * @note This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle @@ -210,12 +210,12 @@ object SRAM { numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, - contents: Option[String] = None + loadMemoryFile: String )( implicit evidence: T <:< Vec[_], sourceInfo: SourceInfo ): SRAMInterface[T] = - masked_memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, contents) + masked_memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, Some(loadMemoryFile)) private def memInterface_impl[T <: Data]( size: BigInt, @@ -224,7 +224,7 @@ object SRAM { numWritePorts: Int, numReadwritePorts: Int, clock: Clock, - contents: Option[String] + memoryFile: Option[String] )( implicit sourceInfo: SourceInfo ): SRAMInterface[T] = { @@ -264,7 +264,7 @@ object SRAM { ) } - contents.map { path: String => loadMemoryFromFileInline(mem, path) } + memoryFile.map { path: String => loadMemoryFromFileInline(mem, path) } _out } @@ -276,7 +276,7 @@ object SRAM { numWritePorts: Int, numReadwritePorts: Int, clock: Clock, - contents: Option[String] + memoryFile: Option[String] )( implicit sourceInfo: SourceInfo, evidence: T <:< Vec[_] @@ -323,7 +323,7 @@ object SRAM { ) } - contents.map { path: String => loadMemoryFromFileInline(mem, path) } + memoryFile.map { path: String => loadMemoryFromFileInline(mem, path) } _out } From c05a7ca58f2b11a641ed402fb30b6b83135f33e1 Mon Sep 17 00:00:00 2001 From: Jared Barocsi Date: Wed, 21 Jun 2023 17:16:28 -0700 Subject: [PATCH 4/8] Use concrete memory file object instead of path, to encode file type information --- src/main/scala/chisel3/util/SRAM.scala | 39 ++++++++++++++++++++------ 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/src/main/scala/chisel3/util/SRAM.scala b/src/main/scala/chisel3/util/SRAM.scala index fffcd93f963..5bb8b24b3c0 100644 --- a/src/main/scala/chisel3/util/SRAM.scala +++ b/src/main/scala/chisel3/util/SRAM.scala @@ -6,6 +6,7 @@ import chisel3.internal.Builder import chisel3.experimental.SourceInfo import chisel3.internal.sourceinfo.{MemTransform, SourceInfoTransform} import chisel3.util.experimental.loadMemoryFromFileInline +import firrtl.annotations.MemoryLoadFileType import scala.language.reflectiveCalls import scala.language.experimental.macros @@ -105,6 +106,24 @@ class SRAMInterface[T <: Data]( Vec(numReadwritePorts, new MemoryReadWritePort(tpe, addrWidth, masked)) } +private[chisel3] abstract class MemoryFile(private[chisel3] val fileType: MemoryLoadFileType) { + val path: String +} + +/** A binary memory file to preload an [[SRAM]] with, represented by a filesystem path. This will annotate + * the inner [[SyncReadMem]] with `loadMemoryFromFile` using `MemoryLoadFileType.Binary` as the file type. + * + * @param path The path to the binary file + */ +case class BinaryMemoryFile(path: String) extends MemoryFile(MemoryLoadFileType.Binary) + +/** A hex memory file to preload an [[SRAM]] with, represented by a filesystem path. This will annotate + * the inner [[SyncReadMem]] with `loadMemoryFromFile` using `MemoryLoadFileType.Hex` as the file type. + * + * @param path The path to the hex file + */ +case class HexMemoryFile(path: String) extends MemoryFile(MemoryLoadFileType.Hex) + object SRAM { /** Generates a [[SyncReadMem]] within the current module, connected to an explicit number @@ -155,11 +174,11 @@ object SRAM { numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, - loadMemoryFile: String + memoryFile: MemoryFile )( implicit sourceInfo: SourceInfo ): SRAMInterface[T] = - memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, Some(loadMemoryFile)) + memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, Some(memoryFile)) /** Generates a [[SyncReadMem]] within the current module, connected to an explicit number * of read, write, and read/write ports, with masking capability on all write and read/write ports. @@ -198,7 +217,7 @@ object SRAM { * @param numReadPorts The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0 * @param numWritePorts The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0 * @param numReadwritePorts The number of desired read/write ports >= 0, and the above two conditions must hold - * @param loadMemoryFile A filesystem path to a binary file to preload this SRAM's contents with + * @param memoryFile A `MemoryFile` object, containing the filesystem path to the data to preload this SRAM with * * @return A new `SRAMInterface` wire containing the control signals for each instantiated port * @note This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle @@ -210,12 +229,12 @@ object SRAM { numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, - loadMemoryFile: String + memoryFile: MemoryFile )( implicit evidence: T <:< Vec[_], sourceInfo: SourceInfo ): SRAMInterface[T] = - masked_memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, Some(loadMemoryFile)) + masked_memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, Some(memoryFile)) private def memInterface_impl[T <: Data]( size: BigInt, @@ -224,7 +243,7 @@ object SRAM { numWritePorts: Int, numReadwritePorts: Int, clock: Clock, - memoryFile: Option[String] + memoryFile: Option[MemoryFile] )( implicit sourceInfo: SourceInfo ): SRAMInterface[T] = { @@ -264,7 +283,8 @@ object SRAM { ) } - memoryFile.map { path: String => loadMemoryFromFileInline(mem, path) } + // Emit Verilog for preloading the memory from a file if requested + memoryFile.map { file: MemoryFile => loadMemoryFromFileInline(mem, file.path, file.fileType) } _out } @@ -276,7 +296,7 @@ object SRAM { numWritePorts: Int, numReadwritePorts: Int, clock: Clock, - memoryFile: Option[String] + memoryFile: Option[MemoryFile] )( implicit sourceInfo: SourceInfo, evidence: T <:< Vec[_] @@ -323,7 +343,8 @@ object SRAM { ) } - memoryFile.map { path: String => loadMemoryFromFileInline(mem, path) } + // Emit Verilog for preloading the memory from a file if requested + memoryFile.map { file: MemoryFile => loadMemoryFromFileInline(mem, file.path, file.fileType) } _out } From 77301a5ada6885ede1de2e3ffc57f2bcfee8631f Mon Sep 17 00:00:00 2001 From: Jared Barocsi Date: Wed, 21 Jun 2023 17:20:37 -0700 Subject: [PATCH 5/8] Docs updates --- src/main/scala/chisel3/util/SRAM.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/chisel3/util/SRAM.scala b/src/main/scala/chisel3/util/SRAM.scala index 5bb8b24b3c0..d8024decb01 100644 --- a/src/main/scala/chisel3/util/SRAM.scala +++ b/src/main/scala/chisel3/util/SRAM.scala @@ -162,7 +162,7 @@ object SRAM { * @param numReadPorts The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0 * @param numWritePorts The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0 * @param numReadwritePorts The number of desired read/write ports >= 0, and the above two conditions must hold - * @param contents A filesystem path to a binary file to preload this SRAM's contents with + * @param memoryFile A memory file whose path is emitted as Verilog directives to initialize the inner `SyncReadMem` * * @return A new `SRAMInterface` wire containing the control signals for each instantiated port * @note This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle @@ -217,7 +217,7 @@ object SRAM { * @param numReadPorts The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0 * @param numWritePorts The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0 * @param numReadwritePorts The number of desired read/write ports >= 0, and the above two conditions must hold - * @param memoryFile A `MemoryFile` object, containing the filesystem path to the data to preload this SRAM with + * @param memoryFile A memory file whose path is emitted as Verilog directives to initialize the inner `SyncReadMem` * * @return A new `SRAMInterface` wire containing the control signals for each instantiated port * @note This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle From 3d7e5bd6e530e197426fae2f90482fa674413d9b Mon Sep 17 00:00:00 2001 From: Jared Barocsi Date: Wed, 21 Jun 2023 17:21:22 -0700 Subject: [PATCH 6/8] Scalafmt --- src/main/scala/chisel3/util/SRAM.scala | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/main/scala/chisel3/util/SRAM.scala b/src/main/scala/chisel3/util/SRAM.scala index d8024decb01..bc75997659e 100644 --- a/src/main/scala/chisel3/util/SRAM.scala +++ b/src/main/scala/chisel3/util/SRAM.scala @@ -234,7 +234,13 @@ object SRAM { implicit evidence: T <:< Vec[_], sourceInfo: SourceInfo ): SRAMInterface[T] = - masked_memInterface_impl(size, tpe)(numReadPorts, numWritePorts, numReadwritePorts, Builder.forcedClock, Some(memoryFile)) + masked_memInterface_impl(size, tpe)( + numReadPorts, + numWritePorts, + numReadwritePorts, + Builder.forcedClock, + Some(memoryFile) + ) private def memInterface_impl[T <: Data]( size: BigInt, From 997498124f298aaa3d5830d0c5111953afdcf64b Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Thu, 22 Jun 2023 13:41:31 -0700 Subject: [PATCH 7/8] Apply suggestions from code review --- src/main/scala/chisel3/util/SRAM.scala | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/main/scala/chisel3/util/SRAM.scala b/src/main/scala/chisel3/util/SRAM.scala index bc75997659e..17ee6b73170 100644 --- a/src/main/scala/chisel3/util/SRAM.scala +++ b/src/main/scala/chisel3/util/SRAM.scala @@ -106,7 +106,12 @@ class SRAMInterface[T <: Data]( Vec(numReadwritePorts, new MemoryReadWritePort(tpe, addrWidth, masked)) } -private[chisel3] abstract class MemoryFile(private[chisel3] val fileType: MemoryLoadFileType) { +/** A memory file with which to preload an [[SRAM]] + * + * See concrete subclasses [[BinaryMemoryFile]] and [[HexMemoryFile]] + */ +sealed abstract class MemoryFile(private[chisel3] val fileType: MemoryLoadFileType) { + /** The path to the memory contents file */ val path: String } @@ -290,7 +295,7 @@ object SRAM { } // Emit Verilog for preloading the memory from a file if requested - memoryFile.map { file: MemoryFile => loadMemoryFromFileInline(mem, file.path, file.fileType) } + memoryFile.foreach { file: MemoryFile => loadMemoryFromFileInline(mem, file.path, file.fileType) } _out } @@ -350,7 +355,7 @@ object SRAM { } // Emit Verilog for preloading the memory from a file if requested - memoryFile.map { file: MemoryFile => loadMemoryFromFileInline(mem, file.path, file.fileType) } + memoryFile.foreach { file: MemoryFile => loadMemoryFromFileInline(mem, file.path, file.fileType) } _out } From d1cb9bf33cd0e453e65627135466478184ab945a Mon Sep 17 00:00:00 2001 From: Jared Barocsi Date: Thu, 22 Jun 2023 15:00:25 -0700 Subject: [PATCH 8/8] Scalafmt --- src/main/scala/chisel3/util/SRAM.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/chisel3/util/SRAM.scala b/src/main/scala/chisel3/util/SRAM.scala index 17ee6b73170..5aebaf8780f 100644 --- a/src/main/scala/chisel3/util/SRAM.scala +++ b/src/main/scala/chisel3/util/SRAM.scala @@ -111,6 +111,7 @@ class SRAMInterface[T <: Data]( * See concrete subclasses [[BinaryMemoryFile]] and [[HexMemoryFile]] */ sealed abstract class MemoryFile(private[chisel3] val fileType: MemoryLoadFileType) { + /** The path to the memory contents file */ val path: String }