From d713a5c471a2a105569799d96be96d6e784d3d91 Mon Sep 17 00:00:00 2001 From: Deborah Soung Date: Wed, 25 Oct 2023 16:07:16 -0700 Subject: [PATCH 1/4] removing clock and cond from force/release --- .../main/scala/chisel3/probe/package.scala | 8 +++-- src/test/scala/chiselTests/ProbeSpec.scala | 29 ++++++++++--------- .../interface/TappedInterfaceSpec.scala | 2 +- 3 files changed, 22 insertions(+), 17 deletions(-) diff --git a/core/src/main/scala/chisel3/probe/package.scala b/core/src/main/scala/chisel3/probe/package.scala index a000d012cbd..b13f24495b1 100644 --- a/core/src/main/scala/chisel3/probe/package.scala +++ b/core/src/main/scala/chisel3/probe/package.scala @@ -101,14 +101,18 @@ package object probe extends SourceInfoDoc { } /** Override existing driver of a writable probe. */ - def force(clock: Clock, cond: Bool, probe: Data, value: Data)(implicit sourceInfo: SourceInfo): Unit = { + def force(probe: Data, value: Data)(implicit sourceInfo: SourceInfo): Unit = { requireHasWritableProbeTypeModifier(probe, "Cannot force a non-writable Probe.") + val clock = Builder.forcedClock + val cond = Module.disableOption.map(!_.value).getOrElse(true.B) pushCommand(ProbeForce(sourceInfo, clock.ref, cond.ref, probe.ref, padDataToProbeWidth(value, probe).ref)) } /** Release driver on a probe. */ - def release(clock: Clock, cond: Bool, probe: Data)(implicit sourceInfo: SourceInfo): Unit = { + def release(probe: Data)(implicit sourceInfo: SourceInfo): Unit = { requireHasWritableProbeTypeModifier(probe, "Cannot release a non-writable Probe.") + val clock = Builder.forcedClock + val cond = Module.disableOption.map(!_.value).getOrElse(true.B) pushCommand(ProbeRelease(sourceInfo, clock.ref, cond.ref, probe.ref)) } diff --git a/src/test/scala/chiselTests/ProbeSpec.scala b/src/test/scala/chiselTests/ProbeSpec.scala index 382c66b5bc4..3bd65b12a19 100644 --- a/src/test/scala/chiselTests/ProbeSpec.scala +++ b/src/test/scala/chiselTests/ProbeSpec.scala @@ -58,12 +58,11 @@ class ProbeSpec extends ChiselFlatSpec with Utils { releaseInitial(u1.io.out) - force(clock, io.x, u2.io.out, u1.io.out) - release(clock, io.y, u2.io.out) + when(io.x) { force(u2.io.out, u1.io.out) } + when(io.y) { release(u2.io.out) } }, Array("--full-stacktrace") ) - (processChirrtl(chirrtl) should contain).allOf( "output io : { flip in : RWProbe>, out : RWProbe>}", "define u1.io.in = rwprobe(io.x)", @@ -71,8 +70,8 @@ class ProbeSpec extends ChiselFlatSpec with Utils { "connect io.y, read(u2.io.out)", "force_initial(u1.io.out, UInt<1>(0h0))", "release_initial(u1.io.out)", - "force(clock, io.x, u2.io.out, u1.io.out)", - "release(clock, io.y, u2.io.out)" + "force(clock, _T, u2.io.out, u1.io.out)", + "release(clock, _T_1, u2.io.out)" ) } @@ -468,7 +467,7 @@ class ProbeSpec extends ChiselFlatSpec with Utils { new Module { val in = IO(Input(Bool())) val out = IO(Output(Probe(Bool()))) - force(clock, in, out, in) + force(out, in) }, Array("--throw-on-first-error") ) @@ -504,7 +503,7 @@ class ProbeSpec extends ChiselFlatSpec with Utils { val in = IO(Input(UInt(4.W))) val p = IO(Output(RWProbe(UInt(16.W)))) forceInitial(p, 123.U) - force(clock, reset.asBool, p, in) + force(p, in) }, Array("--full-stacktrace") ) @@ -535,7 +534,7 @@ class ProbeSpec extends ChiselFlatSpec with Utils { new Module { val in = IO(Input(UInt())) val p = IO(Output(RWProbe(UInt(16.W)))) - force(clock, reset.asBool, p, in) + force(p, in) }, Array("--throw-on-first-error") ) @@ -549,7 +548,7 @@ class ProbeSpec extends ChiselFlatSpec with Utils { new Module { val in = IO(Input(UInt(16.W))) val p = IO(Output(RWProbe(UInt()))) - force(clock, reset.asBool, p, in) + force(p, in) }, Array("--throw-on-first-error") ) @@ -597,23 +596,25 @@ class ProbeSpec extends ChiselFlatSpec with Utils { forceInitial(dut.b.refs.reg, cycle) // Additionally, 'initial force ...' doesn't seem to work here (?). // So do this on cycle zero explicitly for compatibility. - force(clock, cycle === 0.U, dut.b.refs.reg, cycle) + when(cycle === 0.U) { force(dut.b.refs.reg, cycle) } when(0.U < cycle && cycle <= 10.U) { // Force cycle and check we observe it on output a cycle later. chisel3.assert(dut.out === cycle - 1.U) - force(clock, true.B, dut.b.refs.reg, cycle) + force(dut.b.refs.reg, cycle) }.elsewhen(cycle === 11.U) { // Check last value, release. chisel3.assert(dut.out === 10.U) - release(clock, true.B, dut.b.refs.reg) + release(dut.b.refs.reg) }.elsewhen(cycle === 12.U) { // Check original value is restored. chisel3.assert(dut.out === 42.U) } // Force the register and the output port. - force(clock, cycle >= 13.U, dut.b.refs.reg, cycle) - force(clock, cycle >= 13.U, dut.b.refs.out, 123.U) + when(cycle >= 13.U) { + force(dut.b.refs.reg, cycle) + force(dut.b.refs.out, 123.U) + } when(cycle > 13.U) { // Register reads the value forced to it. chisel3.assert(read(dut.b.refs.reg) === cycle) diff --git a/src/test/scala/chiselTests/interface/TappedInterfaceSpec.scala b/src/test/scala/chiselTests/interface/TappedInterfaceSpec.scala index 0ca19adc11b..bd0ac266bc4 100644 --- a/src/test/scala/chiselTests/interface/TappedInterfaceSpec.scala +++ b/src/test/scala/chiselTests/interface/TappedInterfaceSpec.scala @@ -110,7 +110,7 @@ class TappedInterfaceSpec extends AnyFunSpec with Matchers { b := baz.io.b forceInitial(baz.io.c, true.B) - force(clock, reset.asBool, baz.io.d, false.B) + force(baz.io.d, false.B) } } From a0c8525512317a5f1b95d3b4eb0d95fae655d242 Mon Sep 17 00:00:00 2001 From: Deborah Soung Date: Wed, 25 Oct 2023 16:44:46 -0700 Subject: [PATCH 2/4] more scaladoc details --- .../main/scala/chisel3/probe/package.scala | 33 +++++++++++++++---- 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/core/src/main/scala/chisel3/probe/package.scala b/core/src/main/scala/chisel3/probe/package.scala index b13f24495b1..72344b4d7f6 100644 --- a/core/src/main/scala/chisel3/probe/package.scala +++ b/core/src/main/scala/chisel3/probe/package.scala @@ -25,7 +25,11 @@ package object probe extends SourceInfoDoc { } } - /** Initialize a probe with a provided probe value. */ + /** Initialize a probe with a provided probe value. + * + * @param sink probe to initialize + * @param probeExpr value to initialize the sink to + */ def define[T <: Data](sink: T, probeExpr: T)(implicit sourceInfo: SourceInfo): Unit = { if (!checkTypeEquivalence(sink, probeExpr)) { Builder.error("Cannot define a probe on a non-equivalent type.") @@ -41,7 +45,10 @@ package object probe extends SourceInfoDoc { pushCommand(ProbeDefine(sourceInfo, sink.ref, probeExpr.ref)) } - /** Access the value of a probe. */ + /** Access the value of a probe. + * + * @param source probe whose value is getting accessed + */ def read[T <: Data](source: T): T = macro chisel3.internal.sourceinfo.ProbeTransform.sourceRead[T] /** @group SourceInfoTransformMacro */ @@ -88,19 +95,30 @@ package object probe extends SourceInfoDoc { } } - /** Override existing driver of a writable probe on initialization. */ + /** Override existing driver of a writable probe on initialization. + * + * @param probe writable Probe to force + * @value value to force onto the probe + */ def forceInitial(probe: Data, value: Data)(implicit sourceInfo: SourceInfo): Unit = { requireHasWritableProbeTypeModifier(probe, "Cannot forceInitial a non-writable Probe.") pushCommand(ProbeForceInitial(sourceInfo, probe.ref, padDataToProbeWidth(value, probe).ref)) } - /** Release initial driver on a probe. */ + /** Release initial driver on a probe. + * + * @param probe writable Probe to release + */ def releaseInitial(probe: Data)(implicit sourceInfo: SourceInfo): Unit = { requireHasWritableProbeTypeModifier(probe, "Cannot releaseInitial a non-writable Probe.") pushCommand(ProbeReleaseInitial(sourceInfo, probe.ref)) } - /** Override existing driver of a writable probe. */ + /** Override existing driver of a writable probe. + * + * @param probe writable Probe to force + * @value value to force onto the probe + */ def force(probe: Data, value: Data)(implicit sourceInfo: SourceInfo): Unit = { requireHasWritableProbeTypeModifier(probe, "Cannot force a non-writable Probe.") val clock = Builder.forcedClock @@ -108,7 +126,10 @@ package object probe extends SourceInfoDoc { pushCommand(ProbeForce(sourceInfo, clock.ref, cond.ref, probe.ref, padDataToProbeWidth(value, probe).ref)) } - /** Release driver on a probe. */ + /** Release driver on a probe. + * + * @param probe writable Probe to release + */ def release(probe: Data)(implicit sourceInfo: SourceInfo): Unit = { requireHasWritableProbeTypeModifier(probe, "Cannot release a non-writable Probe.") val clock = Builder.forcedClock From a5747dc87f023ace8d871c6835d614b7b9c6a025 Mon Sep 17 00:00:00 2001 From: Deborah Soung Date: Thu, 26 Oct 2023 09:12:40 -0700 Subject: [PATCH 3/4] fix mdoc tags --- core/src/main/scala/chisel3/probe/package.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/core/src/main/scala/chisel3/probe/package.scala b/core/src/main/scala/chisel3/probe/package.scala index 72344b4d7f6..e74d086c63c 100644 --- a/core/src/main/scala/chisel3/probe/package.scala +++ b/core/src/main/scala/chisel3/probe/package.scala @@ -98,7 +98,7 @@ package object probe extends SourceInfoDoc { /** Override existing driver of a writable probe on initialization. * * @param probe writable Probe to force - * @value value to force onto the probe + * @param value to force onto the probe */ def forceInitial(probe: Data, value: Data)(implicit sourceInfo: SourceInfo): Unit = { requireHasWritableProbeTypeModifier(probe, "Cannot forceInitial a non-writable Probe.") @@ -117,7 +117,7 @@ package object probe extends SourceInfoDoc { /** Override existing driver of a writable probe. * * @param probe writable Probe to force - * @value value to force onto the probe + * @param value to force onto the probe */ def force(probe: Data, value: Data)(implicit sourceInfo: SourceInfo): Unit = { requireHasWritableProbeTypeModifier(probe, "Cannot force a non-writable Probe.") From 4c9dad3ebad7688bd5e3b068071431ec9b299e3e Mon Sep 17 00:00:00 2001 From: Deborah Soung Date: Thu, 26 Oct 2023 09:30:46 -0700 Subject: [PATCH 4/4] when details in scaladoc --- core/src/main/scala/chisel3/probe/package.scala | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/core/src/main/scala/chisel3/probe/package.scala b/core/src/main/scala/chisel3/probe/package.scala index e74d086c63c..6c0f5d0a531 100644 --- a/core/src/main/scala/chisel3/probe/package.scala +++ b/core/src/main/scala/chisel3/probe/package.scala @@ -114,7 +114,12 @@ package object probe extends SourceInfoDoc { pushCommand(ProbeReleaseInitial(sourceInfo, probe.ref)) } - /** Override existing driver of a writable probe. + /** Override existing driver of a writable probe. If called within the scope + * of a [[when]] block, the force will only occur on cycles that the when + * condition is true. + * + * Fires only when reset has been asserted and then deasserted through the + * [[Disable]] API. * * @param probe writable Probe to force * @param value to force onto the probe @@ -126,7 +131,12 @@ package object probe extends SourceInfoDoc { pushCommand(ProbeForce(sourceInfo, clock.ref, cond.ref, probe.ref, padDataToProbeWidth(value, probe).ref)) } - /** Release driver on a probe. + /** Release driver on a probe. If called within the scope of a [[when]] + * block, the release will only occur on cycles that the when condition + * is true. + * + * Fires only when reset has been asserted and then deasserted through the + * [[Disable]] API. * * @param probe writable Probe to release */