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OmniXtend cache coherence protocol
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OmniXtend version 1.0.3 released!

OmniXtend is a fully open networking protocol for exchanging coherence messages directly with processor caches, memory controllers and various accelerators.

OmniXtend is the most efficient way of attaching new accelerators, storage and memory devices to RISC-V SoCs.

OmniXtend can be used to create multi-socket RISC-V systems.

OmniXtend uses Ethernet L2 for framing, and so can be switched with off-the-shelf Ethernet switches. Programmable-dataplane Ethernet switches, such as Barefoot Tofino, enable greatly improved performance and protocol/architectural innovation.

See the current specification document for details of the protocol. OmniXtend 1.0.3 is based on TileLink version 1.8.0. This document can help with the creation of state machines for caches, accelerators and memory controllers.

This short video shows how to set up the demo system.


OmniXtend is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

The protocol specification is provided under Apache 2.0 license.

The reference hardware implementations include a linux distribution provided under the GPL v2 license.

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