Zk(Zbk, Zkn, Zks)/Zb: Scalar Cryptography/Bitmanip Extension (#2950)

Co-authored-by: phthinh <hung3@e.ntu.edu.sg>
Co-authored-by: Yangyu Chen <cyy@cyyself.name>
Co-authored-by: Jerry Zhao <jerryz123@berkeley.edu>

Author: 4 people

.github/workflows/mill-ci.yml

@@ -65,7 +65,7 @@ jobs:
     runs-on: [self-hosted, linux]
     strategy:
       matrix:
-        config: ["DefaultRV32Config,32,RV32IMACZicsr_Zifencei", "DefaultConfig,64,RV64IMACZicsr_Zifencei"]
+        config: ["DefaultRV32Config,32,RV32IMACZicsr_Zifencei", "DefaultConfig,64,RV64IMACZicsr_Zifencei", "BitManipCryptoConfig,64,RV64IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh", "BitManipCrypto32Config,32,RV32IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"]
     steps:
       - uses: actions/checkout@v2
         with:

build.sc

@@ -62,6 +62,8 @@ object emulator extends mill.Cross[Emulator](
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.TinyConfig"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCryptoConfig"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCrypto32Config"),
   // Misc
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultSmallConfig"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DualBankConfig"),
@@ -337,6 +339,9 @@ object `runnable-arch-test` extends mill.Cross[ArchTest](
   // For CI within reasonable time
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultConfig", "64", "RV64IMACZicsr_Zifencei"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config", "32", "RV32IMACZicsr_Zifencei"),
+
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCryptoConfig", "64", "RV64IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCrypto32Config", "32", "RV32IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"),
 )
 class ArchTest(top: String, config: String, xlen: String, isa: String) extends Module {
   def ispecString = T {

scripts/arch-test/emulator/riscof_emulator.py

@@ -107,6 +107,30 @@ def build(self, isa_yaml, platform_yaml):
           self.isa += 'd'
       if "C" in ispec["ISA"]:
           self.isa += 'c'
+      if "Zba" in ispec["ISA"]:
+          self.isa += '_Zba'
+      if "Zbb" in ispec["ISA"]:
+          self.isa += '_Zbb'
+      if "Zbc" in ispec["ISA"]:
+          self.isa += '_Zbc'
+      if "Zbkb" in ispec["ISA"]:
+          self.isa += '_Zbkb'
+      if "Zbkc" in ispec["ISA"]:
+          self.isa += '_Zbkc'
+      if "Zbkx" in ispec["ISA"]:
+          self.isa += '_Zbkx'
+      if "Zbs" in ispec["ISA"]:
+          self.isa += '_Zbs'
+      if "Zknd" in ispec["ISA"]:
+          self.isa += '_Zknd'
+      if "Zkne" in ispec["ISA"]:
+          self.isa += '_Zkne'
+      if "Zknh" in ispec["ISA"]:
+          self.isa += '_Zknh'
+      if "Zksed" in ispec["ISA"]:
+          self.isa += '_Zksed'
+      if "Zksh" in ispec["ISA"]:
+          self.isa += '_Zksh'
 
       #TODO: The following assumes you are using the riscv-gcc toolchain. If
       #      not please change appropriately
@@ -153,7 +177,7 @@ def runTests(self, testList):
 
           # substitute all variables in the compile command that we created in the initialize
           # function
-          cmd = self.compile_cmd.format(testentry['isa'].lower(), test, elf, compile_macros)
+          cmd = self.compile_cmd.format(self.isa.lower(), test, elf, compile_macros)
 
 	  # if the user wants to disable running the tests and only compile the tests, then
 	  # the "else" clause is executed below assigning the sim command to simple no action

scripts/arch-test/spike/riscof_spike.py

@@ -107,6 +107,30 @@ def build(self, isa_yaml, platform_yaml):
           self.isa += 'd'
       if "C" in ispec["ISA"]:
           self.isa += 'c'
+      if "Zba" in ispec["ISA"]:
+          self.isa += '_Zba'
+      if "Zbb" in ispec["ISA"]:
+          self.isa += '_Zbb'
+      if "Zbc" in ispec["ISA"]:
+          self.isa += '_Zbc'
+      if "Zbkb" in ispec["ISA"]:
+          self.isa += '_Zbkb'
+      if "Zbkc" in ispec["ISA"]:
+          self.isa += '_Zbkc'
+      if "Zbkx" in ispec["ISA"]:
+          self.isa += '_Zbkx'
+      if "Zbs" in ispec["ISA"]:
+          self.isa += '_Zbs'
+      if "Zknd" in ispec["ISA"]:
+          self.isa += '_Zknd'
+      if "Zkne" in ispec["ISA"]:
+          self.isa += '_Zkne'
+      if "Zknh" in ispec["ISA"]:
+          self.isa += '_Zknh'
+      if "Zksed" in ispec["ISA"]:
+          self.isa += '_Zksed'
+      if "Zksh" in ispec["ISA"]:
+          self.isa += '_Zksh'
 
       #TODO: The following assumes you are using the riscv-gcc toolchain. If
       #      not please change appropriately
@@ -153,7 +177,7 @@ def runTests(self, testList):
 
           # substitute all variables in the compile command that we created in the initialize
           # function
-          cmd = self.compile_cmd.format(testentry['isa'].lower(), test, elf, compile_macros)
+          cmd = self.compile_cmd.format(self.isa.lower(), test, elf, compile_macros)
 
 	  # if the user wants to disable running the tests and only compile the tests, then
 	  # the "else" clause is executed below assigning the sim command to simple no action