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doubts about L1 cache configuration #1352

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clx7913 opened this issue Apr 16, 2018 · 9 comments
Closed

doubts about L1 cache configuration #1352

clx7913 opened this issue Apr 16, 2018 · 9 comments

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@clx7913
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@clx7913 clx7913 commented Apr 16, 2018

For example,my L1 cache has the configuration:"NSets=64,NWays=4".How many bytes or bits each way has?Which parameter should I refer to in /coreplex/Configs.scala,the RowBits or the CacheBlockBytes?

@hcook
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@hcook hcook commented Apr 16, 2018

CacheBlockBytes controls the size of each cache block (of which there are ways*sets).

RowBits controls the dimensions of the data SRAM.

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@clx7913
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@clx7913 clx7913 commented Apr 16, 2018

You mean each way has CacheBlockBytes bytes?

If the default value of CacheBlockBytes is 64,so the size of the L1 cache is sets*ways*CacheBlockBytes=64*4*64.Am I right?

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@hcook
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@hcook hcook commented Apr 17, 2018

It depends what you mean by "each way". Each way of a set is CacheBlockBytes of data. Each way of a cache is therefore CacheBlockBytes*sets. The default cache size is 16Kb.

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@clx7913
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@clx7913 clx7913 commented Apr 18, 2018

Thank you so much!That's really detailed.

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@clx7913 clx7913 closed this Apr 18, 2018
@cabingh
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@cabingh cabingh commented Sep 8, 2018

Hello I am still learning the source code structures. where I can find this default CacheBlockBytes setting? I don't see /coreplex/Configs.scala in current src/main/scala. Thanks in advance.

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@aignacio
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@aignacio aignacio commented Nov 15, 2018

@cabingh I'm not sure about that but check this line where it's defined as 64 bytes. As an example, the configuration of L1 for TinyCore (If I'm right) it's:
D$ cache size = 256 nSets * 1 nWays * 64 CacheBlockbytes = 16384 Bytes = 16 KiB
I$ cache size = 64 nSets * 1 nWays * 64 CacheBlockbytes = 4096 Bytes = 4 KiB
...using the image below (different cfg) we can say that by default we have block size equals to 512-bit (64*8) instead of 32-bit like image.
screenshot from 2018-11-15 14-30-45
is this right @aswaterman ?

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@aswaterman
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@aswaterman aswaterman commented Nov 15, 2018

@aignacio that sounds correct to me.

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@jerryhethatday
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@jerryhethatday jerryhethatday commented Nov 8, 2020

CacheBlockBytes controls the size of each cache block (of which there are ways*sets).

RowBits controls the dimensions of the data SRAM.

can you further explain the rowbits field, I have no idea what's that for? what does dimensions of the data SRAM mean?

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@aswaterman
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@aswaterman aswaterman commented Nov 8, 2020

How wide the data SRAM physically is. For example, if RowBits is 128 and CacheBlockBytes is 64 (=512 bits), then each cache line spans 4 rows.

It's essentially a physical-design tuning parameter.

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