From 0f1936362a2e1dcb8a434821397cf3fcfcb1f301 Mon Sep 17 00:00:00 2001 From: John Ingalls Date: Mon, 20 Mar 2023 09:59:40 -0700 Subject: [PATCH] Hypervisor: encodeVirtualAddress extra MSB to canonicalize VS-disabled --- src/main/scala/rocket/RocketCore.scala | 7 ++++--- src/main/scala/tile/BaseTile.scala | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala index a654eafdf6c..fcbc46a604b 100644 --- a/src/main/scala/rocket/RocketCore.scala +++ b/src/main/scala/rocket/RocketCore.scala @@ -1092,9 +1092,10 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else { // efficient means to compress 64-bit VA into vaddrBits+1 bits // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) - val a = a0.asSInt >> vaddrBits - val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1)) - Cat(msb, ea(vaddrBits-1,0)) + val b = vaddrBitsExtended-1 + val a = (a0 >> b).asSInt + val msb = Mux(a === 0.S || a === -1.S, ea(b), !ea(b-1)) + Cat(msb, ea(b-1, 0)) } class Scoreboard(n: Int, zero: Boolean = false) diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index d9fbc861922..3456e1e1143 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -190,7 +190,7 @@ trait HasTileParameters extends HasNonDiplomaticTileParameters { } def vpnBits: Int = vaddrBits - pgIdxBits def ppnBits: Int = paddrBits - pgIdxBits - def vpnBitsExtended: Int = vpnBits + (vaddrBits < xLen).toInt + def vpnBitsExtended: Int = vpnBits + (if (vaddrBits < xLen) 1 + usingHypervisor.toInt else 0) def vaddrBitsExtended: Int = vpnBitsExtended + pgIdxBits }