diff --git a/frontends/systemverilog/uhdm_common_frontend.cc b/frontends/systemverilog/uhdm_common_frontend.cc index d242a7d48..73d9eefb0 100644 --- a/frontends/systemverilog/uhdm_common_frontend.cc +++ b/frontends/systemverilog/uhdm_common_frontend.cc @@ -151,8 +151,29 @@ void UhdmCommonFrontend::execute(std::istream *&f, std::string filename, std::ve AST::AstNode *current_ast = parse(filename); if (current_ast) { - AST::process(design, current_ast, dump_ast1, dump_ast2, no_dump_ptr, dump_vlog1, dump_vlog2, dump_rtlil, false, false, false, false, false, - false, false, false, false, false, dont_redefine, false, defer, default_nettype_wire); + AST::process(design, current_ast, + false, // nodisplay (came with Yosys 0.37) + dump_ast1, // + dump_ast2, // + no_dump_ptr, // + dump_vlog1, // + dump_vlog2, // + dump_rtlil, // + false, // nolatches + false, // nomeminit + false, // nomem2reg + false, // mem2reg + false, // noblackbox + false, // lib + false, // nowb + false, // noopt + false, // icells + false, // pwires + dont_redefine, // nooverwrite + false, // overwrite + defer, // defer + default_nettype_wire // autowire + ); delete current_ast; } } diff --git a/third_party/yosys b/third_party/yosys index ea7818d31..80511ced7 160000 --- a/third_party/yosys +++ b/third_party/yosys @@ -1 +1 @@ -Subproject commit ea7818d31bb2533d4ecceb2ed1bcf4a22b850453 +Subproject commit 80511ced71b657e77a5389d54c6aa045c047ccaf