diff --git a/uhdm-tests/opentitan/0001-Add-opentitan-patch-for-uhdm.patch b/uhdm-tests/opentitan/0001-Add-opentitan-patch-for-uhdm.patch index 5b4e33da4..276eaef27 100644 --- a/uhdm-tests/opentitan/0001-Add-opentitan-patch-for-uhdm.patch +++ b/uhdm-tests/opentitan/0001-Add-opentitan-patch-for-uhdm.patch @@ -824,6 +824,380 @@ index 77c3cdff9..4765d63ba 100644 // to internal hardware .qe (), +diff --git a/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv b/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv +index f6dbddef4..a7b890133 100644 +--- a/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv ++++ b/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv +@@ -13,11 +13,14 @@ module alert_handler_reg_wrap import alert_pkg::*; ( + // interrupt + output logic [N_CLASSES-1:0] irq_o, + // State information for HW crashdump +- output alert_crashdump_t crashdump_o, ++ //output alert_crashdump_t crashdump_o, ++ output wire [212:0] crashdump_o, + // hw2reg +- input hw2reg_wrap_t hw2reg_wrap, ++ //input hw2reg_wrap_t hw2reg_wrap, ++ input wire [220:0] hw2reg_wrap, + // reg2hw +- output reg2hw_wrap_t reg2hw_wrap ++ //output reg2hw_wrap_t reg2hw_wrap ++ output wire [811:0] reg2hw_wrap + ); + + +@@ -26,8 +29,10 @@ module alert_handler_reg_wrap import alert_pkg::*; ( + ////////////////// + + logic [N_CLASSES-1:0] class_autolock_en; +- alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw; +- alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg; ++ //alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw; ++ //alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg; ++ wire [844:0] reg2hw; ++ wire [237:0] hw2reg; + + alert_handler_reg_top u_reg ( + .clk_i, +@@ -43,57 +48,46 @@ module alert_handler_reg_wrap import alert_pkg::*; ( + // interrupts // + //////////////// + +- prim_intr_hw #( +- .Width(1) +- ) i_irq_classa ( +- .event_intr_i ( hw2reg_wrap.class_trig[0] ), +- .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classa.q ), +- .reg2hw_intr_test_q_i ( reg2hw.intr_test.classa.q ), +- .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classa.qe ), +- .reg2hw_intr_state_q_i ( reg2hw.intr_state.classa.q ), +- .hw2reg_intr_state_de_o ( hw2reg.intr_state.classa.de ), +- .hw2reg_intr_state_d_o ( hw2reg.intr_state.classa.d ), +- .intr_o ( irq_o[0] ) +- ); +- +- prim_intr_hw #( +- .Width(1) +- ) i_irq_classb ( +- .event_intr_i ( hw2reg_wrap.class_trig[1] ), +- .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classb.q ), +- .reg2hw_intr_test_q_i ( reg2hw.intr_test.classb.q ), +- .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classb.qe ), +- .reg2hw_intr_state_q_i ( reg2hw.intr_state.classb.q ), +- .hw2reg_intr_state_de_o ( hw2reg.intr_state.classb.de ), +- .hw2reg_intr_state_d_o ( hw2reg.intr_state.classb.d ), +- .intr_o ( irq_o[1] ) +- ); +- +- prim_intr_hw #( +- .Width(1) +- ) i_irq_classc ( +- .event_intr_i ( hw2reg_wrap.class_trig[2] ), +- .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classc.q ), +- .reg2hw_intr_test_q_i ( reg2hw.intr_test.classc.q ), +- .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classc.qe ), +- .reg2hw_intr_state_q_i ( reg2hw.intr_state.classc.q ), +- .hw2reg_intr_state_de_o ( hw2reg.intr_state.classc.de ), +- .hw2reg_intr_state_d_o ( hw2reg.intr_state.classc.d ), +- .intr_o ( irq_o[2] ) +- ); +- +- prim_intr_hw #( +- .Width(1) +- ) i_irq_classd ( +- .event_intr_i ( hw2reg_wrap.class_trig[3] ), +- .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classd.q ), +- .reg2hw_intr_test_q_i ( reg2hw.intr_test.classd.q ), +- .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classd.qe ), +- .reg2hw_intr_state_q_i ( reg2hw.intr_state.classd.q ), +- .hw2reg_intr_state_de_o ( hw2reg.intr_state.classd.de ), +- .hw2reg_intr_state_d_o ( hw2reg.intr_state.classd.d ), +- .intr_o ( irq_o[3] ) +- ); ++ prim_intr_hw #(.Width(1)) i_irq_classa( ++ .event_intr_i(hw2reg_wrap[208]), ++ .reg2hw_intr_enable_q_i(reg2hw[840]), ++ .reg2hw_intr_test_q_i(reg2hw[836]), ++ .reg2hw_intr_test_qe_i(reg2hw[835]), ++ .reg2hw_intr_state_q_i(reg2hw[844]), ++ .hw2reg_intr_state_de_o(hw2reg[236]), ++ .hw2reg_intr_state_d_o(hw2reg[237]), ++ .intr_o(irq_o[0]) ++ ); ++ prim_intr_hw #(.Width(1)) i_irq_classb( ++ .event_intr_i(hw2reg_wrap[209]), ++ .reg2hw_intr_enable_q_i(reg2hw[839]), ++ .reg2hw_intr_test_q_i(reg2hw[834]), ++ .reg2hw_intr_test_qe_i(reg2hw[833]), ++ .reg2hw_intr_state_q_i(reg2hw[843]), ++ .hw2reg_intr_state_de_o(hw2reg[234]), ++ .hw2reg_intr_state_d_o(hw2reg[235]), ++ .intr_o(irq_o[1]) ++ ); ++ prim_intr_hw #(.Width(1)) i_irq_classc( ++ .event_intr_i(hw2reg_wrap[210]), ++ .reg2hw_intr_enable_q_i(reg2hw[838]), ++ .reg2hw_intr_test_q_i(reg2hw[832]), ++ .reg2hw_intr_test_qe_i(reg2hw[831]), ++ .reg2hw_intr_state_q_i(reg2hw[842]), ++ .hw2reg_intr_state_de_o(hw2reg[232]), ++ .hw2reg_intr_state_d_o(hw2reg[233]), ++ .intr_o(irq_o[2]) ++ ); ++ prim_intr_hw #(.Width(1)) i_irq_classd( ++ .event_intr_i(hw2reg_wrap[211]), ++ .reg2hw_intr_enable_q_i(reg2hw[837]), ++ .reg2hw_intr_test_q_i(reg2hw[830]), ++ .reg2hw_intr_test_qe_i(reg2hw[829]), ++ .reg2hw_intr_state_q_i(reg2hw[841]), ++ .hw2reg_intr_state_de_o(hw2reg[230]), ++ .hw2reg_intr_state_d_o(hw2reg[231]), ++ .intr_o(irq_o[3]) ++ ); + + ///////////////////// + // hw2reg mappings // +@@ -102,185 +96,62 @@ module alert_handler_reg_wrap import alert_pkg::*; ( + // if an alert is enabled and it fires, + // we have to set the corresponding cause bit + for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_cause +- assign hw2reg.alert_cause[k].d = 1'b1; +- assign hw2reg.alert_cause[k].de = reg2hw.alert_cause[k].q | +- hw2reg_wrap.alert_cause[k]; ++ assign hw2reg[220 + ((k * 2) + 1)] = 1'b1; ++ assign hw2reg[220 + (k * 2)] = reg2hw[784 + k] | hw2reg_wrap[216 + k]; + end + + // if a local alert is enabled and it fires, + // we have to set the corresponding cause bit + for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_cause +- assign hw2reg.loc_alert_cause[k].d = 1'b1; +- assign hw2reg.loc_alert_cause[k].de = reg2hw.loc_alert_cause[k].q | +- hw2reg_wrap.loc_alert_cause[k]; ++ assign hw2reg[212 + ((k * 2) + 1)] = 1'b1; ++ assign hw2reg[212 + (k * 2)] = reg2hw[768 + k] | hw2reg_wrap[212 + k]; + end + + // ping timeout in cycles + // autolock can clear these regs automatically upon entering escalation + // note: the class must be activated for this to occur +- assign { hw2reg.classd_clren.d, +- hw2reg.classc_clren.d, +- hw2reg.classb_clren.d, +- hw2reg.classa_clren.d } = '0; +- +- assign { hw2reg.classd_clren.de, +- hw2reg.classc_clren.de, +- hw2reg.classb_clren.de, +- hw2reg.classa_clren.de } = hw2reg_wrap.class_esc_trig & +- class_autolock_en & +- reg2hw_wrap.class_en; +- +- // current accumulator counts +- assign { hw2reg.classd_accum_cnt.d, +- hw2reg.classc_accum_cnt.d, +- hw2reg.classb_accum_cnt.d, +- hw2reg.classa_accum_cnt.d } = hw2reg_wrap.class_accum_cnt; +- +- // current accumulator counts +- assign { hw2reg.classd_esc_cnt.d, +- hw2reg.classc_esc_cnt.d, +- hw2reg.classb_esc_cnt.d, +- hw2reg.classa_esc_cnt.d } = hw2reg_wrap.class_esc_cnt; +- +- // current accumulator counts +- assign { hw2reg.classd_state.d, +- hw2reg.classc_state.d, +- hw2reg.classb_state.d, +- hw2reg.classa_state.d } = hw2reg_wrap.class_esc_state; +- ++ assign {hw2reg[52], hw2reg[105], hw2reg[158], hw2reg[211]} = {4 {1'b0}}; ++ assign {hw2reg[51], hw2reg[104], hw2reg[157], hw2reg[210]} = (hw2reg_wrap[207-:4] & class_autolock_en) & reg2hw_wrap[759-:4]; ++ assign hw2reg[209-:16] = hw2reg_wrap[203-:16]; ++ assign hw2reg[156-:16] = hw2reg_wrap[187-:16]; ++ assign hw2reg[103-:16] = hw2reg_wrap[171-:16]; ++ assign hw2reg[50-:16] = hw2reg_wrap[155-:16]; ++ assign hw2reg[193-:32] = hw2reg_wrap[139-:32]; ++ assign hw2reg[140-:32] = hw2reg_wrap[107-:32]; ++ assign hw2reg[87-:32] = hw2reg_wrap[75-:32]; ++ assign hw2reg[34-:32] = hw2reg_wrap[43-:32]; ++ assign hw2reg[161-:3] = hw2reg_wrap[11-:3]; ++ assign hw2reg[108-:3] = hw2reg_wrap[8-:3]; ++ assign hw2reg[55-:3] = hw2reg_wrap[5-:3]; ++ assign hw2reg[2-:3] = hw2reg_wrap[2-:3]; + ///////////////////// + // reg2hw mappings // + ///////////////////// + + // config register lock +- assign reg2hw_wrap.config_locked = ~reg2hw.regen.q; ++ assign reg2hw_wrap[811] = ~reg2hw[828]; + + // alert enable and class assignments + for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_en_class +- assign reg2hw_wrap.alert_en[k] = reg2hw.alert_en[k].q; +- assign reg2hw_wrap.alert_class[k] = reg2hw.alert_class[k].q; ++ assign reg2hw_wrap[770 + k] = reg2hw[799 + k]; ++ assign reg2hw_wrap[760 + (k * CLASS_DW)+:CLASS_DW] = reg2hw[789 + ((k * 2) + 1)-:2]; + end + + // local alert enable and class assignments + for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_en_class +- assign reg2hw_wrap.loc_alert_en[k] = reg2hw.loc_alert_en[k].q; +- assign reg2hw_wrap.loc_alert_class[k] = reg2hw.loc_alert_class[k].q; ++ assign reg2hw_wrap[783 + k] = reg2hw[780 + k]; ++ assign reg2hw_wrap[775 + (k * CLASS_DW)+:CLASS_DW] = reg2hw[772 + ((k * 2) + 1)-:2]; + end + +- assign reg2hw_wrap.ping_timeout_cyc = reg2hw.ping_timeout_cyc.q; +- +- // class enable +- // we require that at least one of the enable signals is +- // set for a class to be enabled +- assign reg2hw_wrap.class_en = { reg2hw.classd_ctrl.en & ( reg2hw.classd_ctrl.en_e3 | +- reg2hw.classd_ctrl.en_e2 | +- reg2hw.classd_ctrl.en_e1 | +- reg2hw.classd_ctrl.en_e0 ), +- // +- reg2hw.classc_ctrl.en & ( reg2hw.classc_ctrl.en_e3 | +- reg2hw.classc_ctrl.en_e2 | +- reg2hw.classc_ctrl.en_e1 | +- reg2hw.classc_ctrl.en_e0 ), +- // +- reg2hw.classb_ctrl.en & ( reg2hw.classb_ctrl.en_e3 | +- reg2hw.classb_ctrl.en_e2 | +- reg2hw.classb_ctrl.en_e1 | +- reg2hw.classb_ctrl.en_e0 ), +- // +- reg2hw.classa_ctrl.en & ( reg2hw.classa_ctrl.en_e3 | +- reg2hw.classa_ctrl.en_e2 | +- reg2hw.classa_ctrl.en_e1 | +- reg2hw.classa_ctrl.en_e0 ) }; +- +- +- // autolock enable +- assign class_autolock_en = { reg2hw.classd_ctrl.lock, +- reg2hw.classc_ctrl.lock, +- reg2hw.classb_ctrl.lock, +- reg2hw.classa_ctrl.lock }; +- +- // escalation signal enable +- assign reg2hw_wrap.class_esc_en = { reg2hw.classd_ctrl.en_e3, +- reg2hw.classd_ctrl.en_e2, +- reg2hw.classd_ctrl.en_e1, +- reg2hw.classd_ctrl.en_e0, +- // +- reg2hw.classc_ctrl.en_e3, +- reg2hw.classc_ctrl.en_e2, +- reg2hw.classc_ctrl.en_e1, +- reg2hw.classc_ctrl.en_e0, +- // +- reg2hw.classb_ctrl.en_e3, +- reg2hw.classb_ctrl.en_e2, +- reg2hw.classb_ctrl.en_e1, +- reg2hw.classb_ctrl.en_e0, +- // +- reg2hw.classa_ctrl.en_e3, +- reg2hw.classa_ctrl.en_e2, +- reg2hw.classa_ctrl.en_e1, +- reg2hw.classa_ctrl.en_e0 }; +- +- +- // escalation phase to escalation signal mapping +- assign reg2hw_wrap.class_esc_map = { reg2hw.classd_ctrl.map_e3, +- reg2hw.classd_ctrl.map_e2, +- reg2hw.classd_ctrl.map_e1, +- reg2hw.classd_ctrl.map_e0, +- // +- reg2hw.classc_ctrl.map_e3, +- reg2hw.classc_ctrl.map_e2, +- reg2hw.classc_ctrl.map_e1, +- reg2hw.classc_ctrl.map_e0, +- // +- reg2hw.classb_ctrl.map_e3, +- reg2hw.classb_ctrl.map_e2, +- reg2hw.classb_ctrl.map_e1, +- reg2hw.classb_ctrl.map_e0, +- // +- reg2hw.classa_ctrl.map_e3, +- reg2hw.classa_ctrl.map_e2, +- reg2hw.classa_ctrl.map_e1, +- reg2hw.classa_ctrl.map_e0 }; +- +- // TODO: check whether this is correctly locked inside the regfile +- // writing 1b1 to a class clr register clears the accumulator and +- // escalation state if autolock is not asserted +- assign reg2hw_wrap.class_clr = { reg2hw.classd_clr.q & reg2hw.classd_clr.qe, +- reg2hw.classc_clr.q & reg2hw.classc_clr.qe, +- reg2hw.classb_clr.q & reg2hw.classb_clr.qe, +- reg2hw.classa_clr.q & reg2hw.classa_clr.qe }; +- +- // accumulator thresholds +- assign reg2hw_wrap.class_accum_thresh = { reg2hw.classd_accum_thresh.q, +- reg2hw.classc_accum_thresh.q, +- reg2hw.classb_accum_thresh.q, +- reg2hw.classa_accum_thresh.q }; +- +- // interrupt timeout lengths +- assign reg2hw_wrap.class_timeout_cyc = { reg2hw.classd_timeout_cyc.q, +- reg2hw.classc_timeout_cyc.q, +- reg2hw.classb_timeout_cyc.q, +- reg2hw.classa_timeout_cyc.q }; +- // escalation phase lengths +- assign reg2hw_wrap.class_phase_cyc = { reg2hw.classd_phase3_cyc.q, +- reg2hw.classd_phase2_cyc.q, +- reg2hw.classd_phase1_cyc.q, +- reg2hw.classd_phase0_cyc.q, +- // +- reg2hw.classc_phase3_cyc.q, +- reg2hw.classc_phase2_cyc.q, +- reg2hw.classc_phase1_cyc.q, +- reg2hw.classc_phase0_cyc.q, +- // +- reg2hw.classb_phase3_cyc.q, +- reg2hw.classb_phase2_cyc.q, +- reg2hw.classb_phase1_cyc.q, +- reg2hw.classb_phase0_cyc.q, +- // +- reg2hw.classa_phase3_cyc.q, +- reg2hw.classa_phase2_cyc.q, +- reg2hw.classa_phase1_cyc.q, +- reg2hw.classa_phase0_cyc.q}; ++ assign reg2hw_wrap[810-:24] = reg2hw[827-:24]; ++ assign reg2hw_wrap[759-:4] = {reg2hw[191] & (((reg2hw[186] | reg2hw[187]) | reg2hw[188]) | reg2hw[189]), reg2hw[383] & (((reg2hw[378] | reg2hw[379]) | reg2hw[380]) | reg2hw[381]), reg2hw[575] & (((reg2hw[570] | reg2hw[571]) | reg2hw[572]) | reg2hw[573]), reg2hw[767] & (((reg2hw[762] | reg2hw[763]) | reg2hw[764]) | reg2hw[765])}; ++ assign class_autolock_en = {reg2hw[190], reg2hw[382], reg2hw[574], reg2hw[766]}; ++ assign reg2hw_wrap[47-:16] = {reg2hw[186], reg2hw[187], reg2hw[188], reg2hw[189], reg2hw[378], reg2hw[379], reg2hw[380], reg2hw[381], reg2hw[570], reg2hw[571], reg2hw[572], reg2hw[573], reg2hw[762], reg2hw[763], reg2hw[764], reg2hw[765]}; ++ assign reg2hw_wrap[31-:32] = {reg2hw[179-:2], reg2hw[181-:2], reg2hw[183-:2], reg2hw[185-:2], reg2hw[371-:2], reg2hw[373-:2], reg2hw[375-:2], reg2hw[377-:2], reg2hw[563-:2], reg2hw[565-:2], reg2hw[567-:2], reg2hw[569-:2], reg2hw[755-:2], reg2hw[757-:2], reg2hw[759-:2], reg2hw[761-:2]}; ++ assign reg2hw_wrap[755-:4] = {reg2hw[177] & reg2hw[176], reg2hw[369] & reg2hw[368], reg2hw[561] & reg2hw[560], reg2hw[753] & reg2hw[752]}; ++ assign reg2hw_wrap[751-:64] = {reg2hw[175-:16], reg2hw[367-:16], reg2hw[559-:16], reg2hw[751-:16]}; ++ assign reg2hw_wrap[687-:128] = {reg2hw[159-:32], reg2hw[351-:32], reg2hw[543-:32], reg2hw[735-:32]}; ++ assign reg2hw_wrap[559-:512] = {reg2hw[31-:32], reg2hw[63-:32], reg2hw[95-:32], reg2hw[127-:32], reg2hw[223-:32], reg2hw[255-:32], reg2hw[287-:32], reg2hw[319-:32], reg2hw[415-:32], reg2hw[447-:32], reg2hw[479-:32], reg2hw[511-:32], reg2hw[607-:32], reg2hw[639-:32], reg2hw[671-:32], reg2hw[703-:32]}; + + ////////////////////// + // crashdump output // +@@ -288,17 +159,17 @@ module alert_handler_reg_wrap import alert_pkg::*; ( + + // alert cause output + for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_cause_dump +- assign crashdump_o.alert_cause[k] = reg2hw.alert_cause[k].q; ++ assign crashdump_o[208 + k] = reg2hw[784 + k]; + end + + // local alert cause register output + for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_cause_dump +- assign crashdump_o.loc_alert_cause[k] = reg2hw.loc_alert_cause[k].q; ++ assign crashdump_o[204 + k] = reg2hw[768 + k]; + end + +- assign crashdump_o.class_accum_cnt = hw2reg_wrap.class_accum_cnt; +- assign crashdump_o.class_esc_cnt = hw2reg_wrap.class_esc_cnt; +- assign crashdump_o.class_esc_state = hw2reg_wrap.class_esc_state; ++ assign crashdump_o[203-:64] = hw2reg_wrap[203-:64]; ++ assign crashdump_o[139-:128] = hw2reg_wrap[139-:128]; ++ assign crashdump_o[11-:12] = hw2reg_wrap[11-:12]; + + endmodule : alert_handler_reg_wrap + diff --git a/hw/ip/alert_handler/rtl/alert_pkg.sv b/hw/ip/alert_handler/rtl/alert_pkg.sv index 5324b4978..fb9e8de6c 100644 --- a/hw/ip/alert_handler/rtl/alert_pkg.sv @@ -12270,6 +12644,4986 @@ index 4cff2c116..9e70b7672 100644 end endcase end +diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv +index e6d74c618..084f67c94 100644 +--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv ++++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv +@@ -14,8 +14,10 @@ module alert_handler_reg_top ( + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW +- output alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw, // Write +- input alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg, // Read ++ //output alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw, // Write ++ //input alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg, // Read ++ output wire [844:0] reg2hw, ++ input wire [237:0] hw2reg, + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +@@ -427,3169 +429,1803 @@ module alert_handler_reg_top ( + logic [2:0] classd_state_qs; + logic classd_state_re; + +- // Register instances +- // R[intr_state]: V(False) +- +- // F[classa]: 0:0 +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h0) +- ) u_intr_state_classa ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (intr_state_classa_we), +- .wd (intr_state_classa_wd), +- +- // from internal hardware +- .de (hw2reg.intr_state.classa.de), +- .d (hw2reg.intr_state.classa.d ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.intr_state.classa.q ), +- +- // to register interface (read) +- .qs (intr_state_classa_qs) +- ); +- +- +- // F[classb]: 1:1 +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h0) +- ) u_intr_state_classb ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (intr_state_classb_we), +- .wd (intr_state_classb_wd), +- +- // from internal hardware +- .de (hw2reg.intr_state.classb.de), +- .d (hw2reg.intr_state.classb.d ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.intr_state.classb.q ), +- +- // to register interface (read) +- .qs (intr_state_classb_qs) +- ); +- +- +- // F[classc]: 2:2 +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h0) +- ) u_intr_state_classc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (intr_state_classc_we), +- .wd (intr_state_classc_wd), +- +- // from internal hardware +- .de (hw2reg.intr_state.classc.de), +- .d (hw2reg.intr_state.classc.d ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.intr_state.classc.q ), +- +- // to register interface (read) +- .qs (intr_state_classc_qs) +- ); +- +- +- // F[classd]: 3:3 +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h0) +- ) u_intr_state_classd ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (intr_state_classd_we), +- .wd (intr_state_classd_wd), +- +- // from internal hardware +- .de (hw2reg.intr_state.classd.de), +- .d (hw2reg.intr_state.classd.d ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.intr_state.classd.q ), +- +- // to register interface (read) +- .qs (intr_state_classd_qs) +- ); +- +- +- // R[intr_enable]: V(False) +- +- // F[classa]: 0:0 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_intr_enable_classa ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (intr_enable_classa_we), +- .wd (intr_enable_classa_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.intr_enable.classa.q ), +- +- // to register interface (read) +- .qs (intr_enable_classa_qs) +- ); +- +- +- // F[classb]: 1:1 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_intr_enable_classb ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (intr_enable_classb_we), +- .wd (intr_enable_classb_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.intr_enable.classb.q ), +- +- // to register interface (read) +- .qs (intr_enable_classb_qs) +- ); +- +- +- // F[classc]: 2:2 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_intr_enable_classc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (intr_enable_classc_we), +- .wd (intr_enable_classc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.intr_enable.classc.q ), +- +- // to register interface (read) +- .qs (intr_enable_classc_qs) +- ); +- +- +- // F[classd]: 3:3 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_intr_enable_classd ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (intr_enable_classd_we), +- .wd (intr_enable_classd_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.intr_enable.classd.q ), +- +- // to register interface (read) +- .qs (intr_enable_classd_qs) +- ); +- +- +- // R[intr_test]: V(True) +- +- // F[classa]: 0:0 +- prim_subreg_ext #( +- .DW (1) +- ) u_intr_test_classa ( +- .re (1'b0), +- .we (intr_test_classa_we), +- .wd (intr_test_classa_wd), +- .d ('0), +- .qre (), +- .qe (reg2hw.intr_test.classa.qe), +- .q (reg2hw.intr_test.classa.q ), +- .qs () +- ); +- +- +- // F[classb]: 1:1 +- prim_subreg_ext #( +- .DW (1) +- ) u_intr_test_classb ( +- .re (1'b0), +- .we (intr_test_classb_we), +- .wd (intr_test_classb_wd), +- .d ('0), +- .qre (), +- .qe (reg2hw.intr_test.classb.qe), +- .q (reg2hw.intr_test.classb.q ), +- .qs () +- ); +- +- +- // F[classc]: 2:2 +- prim_subreg_ext #( +- .DW (1) +- ) u_intr_test_classc ( +- .re (1'b0), +- .we (intr_test_classc_we), +- .wd (intr_test_classc_wd), +- .d ('0), +- .qre (), +- .qe (reg2hw.intr_test.classc.qe), +- .q (reg2hw.intr_test.classc.q ), +- .qs () +- ); +- +- +- // F[classd]: 3:3 +- prim_subreg_ext #( +- .DW (1) +- ) u_intr_test_classd ( +- .re (1'b0), +- .we (intr_test_classd_we), +- .wd (intr_test_classd_wd), +- .d ('0), +- .qre (), +- .qe (reg2hw.intr_test.classd.qe), +- .q (reg2hw.intr_test.classd.q ), +- .qs () +- ); +- +- +- // R[regen]: V(False) +- +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h1) +- ) u_regen ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (regen_we), +- .wd (regen_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.regen.q ), +- +- // to register interface (read) +- .qs (regen_qs) +- ); +- +- +- // R[ping_timeout_cyc]: V(False) +- +- prim_subreg #( +- .DW (24), +- .SWACCESS("RW"), +- .RESVAL (24'h20) +- ) u_ping_timeout_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (ping_timeout_cyc_we & regen_qs), +- .wd (ping_timeout_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.ping_timeout_cyc.q ), +- +- // to register interface (read) +- .qs (ping_timeout_cyc_qs) +- ); +- +- +- +- // Subregister 0 of Multireg alert_en +- // R[alert_en]: V(False) +- +- // F[en_a0]: 0:0 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_alert_en_en_a0 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (alert_en_en_a0_we & regen_qs), +- .wd (alert_en_en_a0_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.alert_en[0].q ), +- +- // to register interface (read) +- .qs (alert_en_en_a0_qs) +- ); +- +- +- // F[en_a1]: 1:1 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_alert_en_en_a1 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (alert_en_en_a1_we & regen_qs), +- .wd (alert_en_en_a1_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.alert_en[1].q ), +- +- // to register interface (read) +- .qs (alert_en_en_a1_qs) +- ); +- +- +- // F[en_a2]: 2:2 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_alert_en_en_a2 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (alert_en_en_a2_we & regen_qs), +- .wd (alert_en_en_a2_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.alert_en[2].q ), +- +- // to register interface (read) +- .qs (alert_en_en_a2_qs) +- ); +- +- +- // F[en_a3]: 3:3 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_alert_en_en_a3 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (alert_en_en_a3_we & regen_qs), +- .wd (alert_en_en_a3_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.alert_en[3].q ), +- +- // to register interface (read) +- .qs (alert_en_en_a3_qs) +- ); +- +- +- // F[en_a4]: 4:4 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_alert_en_en_a4 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (alert_en_en_a4_we & regen_qs), +- .wd (alert_en_en_a4_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.alert_en[4].q ), +- +- // to register interface (read) +- .qs (alert_en_en_a4_qs) +- ); +- +- +- +- +- // Subregister 0 of Multireg alert_class +- // R[alert_class]: V(False) +- +- // F[class_a0]: 1:0 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h0) +- ) u_alert_class_class_a0 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (alert_class_class_a0_we & regen_qs), +- .wd (alert_class_class_a0_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.alert_class[0].q ), +- +- // to register interface (read) +- .qs (alert_class_class_a0_qs) +- ); +- +- +- // F[class_a1]: 3:2 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h0) +- ) u_alert_class_class_a1 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (alert_class_class_a1_we & regen_qs), +- .wd (alert_class_class_a1_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.alert_class[1].q ), +- +- // to register interface (read) +- .qs (alert_class_class_a1_qs) +- ); +- +- +- // F[class_a2]: 5:4 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h0) +- ) u_alert_class_class_a2 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (alert_class_class_a2_we & regen_qs), +- .wd (alert_class_class_a2_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.alert_class[2].q ), +- +- // to register interface (read) +- .qs (alert_class_class_a2_qs) +- ); +- +- +- // F[class_a3]: 7:6 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h0) +- ) u_alert_class_class_a3 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (alert_class_class_a3_we & regen_qs), +- .wd (alert_class_class_a3_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.alert_class[3].q ), +- +- // to register interface (read) +- .qs (alert_class_class_a3_qs) +- ); +- +- +- // F[class_a4]: 9:8 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h0) +- ) u_alert_class_class_a4 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (alert_class_class_a4_we & regen_qs), +- .wd (alert_class_class_a4_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.alert_class[4].q ), +- +- // to register interface (read) +- .qs (alert_class_class_a4_qs) +- ); +- +- +- +- +- // Subregister 0 of Multireg alert_cause +- // R[alert_cause]: V(False) +- +- // F[a0]: 0:0 +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h0) +- ) u_alert_cause_a0 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (alert_cause_a0_we), +- .wd (alert_cause_a0_wd), +- +- // from internal hardware +- .de (hw2reg.alert_cause[0].de), +- .d (hw2reg.alert_cause[0].d ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.alert_cause[0].q ), +- +- // to register interface (read) +- .qs (alert_cause_a0_qs) +- ); +- +- +- // F[a1]: 1:1 +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h0) +- ) u_alert_cause_a1 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (alert_cause_a1_we), +- .wd (alert_cause_a1_wd), +- +- // from internal hardware +- .de (hw2reg.alert_cause[1].de), +- .d (hw2reg.alert_cause[1].d ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.alert_cause[1].q ), +- +- // to register interface (read) +- .qs (alert_cause_a1_qs) +- ); +- +- +- // F[a2]: 2:2 +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h0) +- ) u_alert_cause_a2 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (alert_cause_a2_we), +- .wd (alert_cause_a2_wd), +- +- // from internal hardware +- .de (hw2reg.alert_cause[2].de), +- .d (hw2reg.alert_cause[2].d ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.alert_cause[2].q ), +- +- // to register interface (read) +- .qs (alert_cause_a2_qs) +- ); +- +- +- // F[a3]: 3:3 +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h0) +- ) u_alert_cause_a3 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (alert_cause_a3_we), +- .wd (alert_cause_a3_wd), +- +- // from internal hardware +- .de (hw2reg.alert_cause[3].de), +- .d (hw2reg.alert_cause[3].d ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.alert_cause[3].q ), +- +- // to register interface (read) +- .qs (alert_cause_a3_qs) +- ); +- +- +- // F[a4]: 4:4 +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h0) +- ) u_alert_cause_a4 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (alert_cause_a4_we), +- .wd (alert_cause_a4_wd), +- +- // from internal hardware +- .de (hw2reg.alert_cause[4].de), +- .d (hw2reg.alert_cause[4].d ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.alert_cause[4].q ), +- +- // to register interface (read) +- .qs (alert_cause_a4_qs) +- ); +- +- +- +- +- // Subregister 0 of Multireg loc_alert_en +- // R[loc_alert_en]: V(False) +- +- // F[en_la0]: 0:0 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_loc_alert_en_en_la0 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (loc_alert_en_en_la0_we & regen_qs), +- .wd (loc_alert_en_en_la0_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.loc_alert_en[0].q ), +- +- // to register interface (read) +- .qs (loc_alert_en_en_la0_qs) +- ); +- +- +- // F[en_la1]: 1:1 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_loc_alert_en_en_la1 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (loc_alert_en_en_la1_we & regen_qs), +- .wd (loc_alert_en_en_la1_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.loc_alert_en[1].q ), +- +- // to register interface (read) +- .qs (loc_alert_en_en_la1_qs) +- ); +- +- +- // F[en_la2]: 2:2 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_loc_alert_en_en_la2 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (loc_alert_en_en_la2_we & regen_qs), +- .wd (loc_alert_en_en_la2_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.loc_alert_en[2].q ), +- +- // to register interface (read) +- .qs (loc_alert_en_en_la2_qs) +- ); +- +- +- // F[en_la3]: 3:3 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_loc_alert_en_en_la3 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (loc_alert_en_en_la3_we & regen_qs), +- .wd (loc_alert_en_en_la3_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.loc_alert_en[3].q ), +- +- // to register interface (read) +- .qs (loc_alert_en_en_la3_qs) +- ); +- +- +- +- +- // Subregister 0 of Multireg loc_alert_class +- // R[loc_alert_class]: V(False) +- +- // F[class_la0]: 1:0 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h0) +- ) u_loc_alert_class_class_la0 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (loc_alert_class_class_la0_we & regen_qs), +- .wd (loc_alert_class_class_la0_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.loc_alert_class[0].q ), +- +- // to register interface (read) +- .qs (loc_alert_class_class_la0_qs) +- ); +- +- +- // F[class_la1]: 3:2 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h0) +- ) u_loc_alert_class_class_la1 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (loc_alert_class_class_la1_we & regen_qs), +- .wd (loc_alert_class_class_la1_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.loc_alert_class[1].q ), +- +- // to register interface (read) +- .qs (loc_alert_class_class_la1_qs) +- ); +- +- +- // F[class_la2]: 5:4 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h0) +- ) u_loc_alert_class_class_la2 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (loc_alert_class_class_la2_we & regen_qs), +- .wd (loc_alert_class_class_la2_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.loc_alert_class[2].q ), +- +- // to register interface (read) +- .qs (loc_alert_class_class_la2_qs) +- ); +- +- +- // F[class_la3]: 7:6 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h0) +- ) u_loc_alert_class_class_la3 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (loc_alert_class_class_la3_we & regen_qs), +- .wd (loc_alert_class_class_la3_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.loc_alert_class[3].q ), +- +- // to register interface (read) +- .qs (loc_alert_class_class_la3_qs) +- ); +- +- +- +- +- // Subregister 0 of Multireg loc_alert_cause +- // R[loc_alert_cause]: V(False) +- +- // F[la0]: 0:0 +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h0) +- ) u_loc_alert_cause_la0 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (loc_alert_cause_la0_we), +- .wd (loc_alert_cause_la0_wd), +- +- // from internal hardware +- .de (hw2reg.loc_alert_cause[0].de), +- .d (hw2reg.loc_alert_cause[0].d ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.loc_alert_cause[0].q ), +- +- // to register interface (read) +- .qs (loc_alert_cause_la0_qs) +- ); +- +- +- // F[la1]: 1:1 +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h0) +- ) u_loc_alert_cause_la1 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (loc_alert_cause_la1_we), +- .wd (loc_alert_cause_la1_wd), +- +- // from internal hardware +- .de (hw2reg.loc_alert_cause[1].de), +- .d (hw2reg.loc_alert_cause[1].d ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.loc_alert_cause[1].q ), +- +- // to register interface (read) +- .qs (loc_alert_cause_la1_qs) +- ); +- +- +- // F[la2]: 2:2 +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h0) +- ) u_loc_alert_cause_la2 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (loc_alert_cause_la2_we), +- .wd (loc_alert_cause_la2_wd), +- +- // from internal hardware +- .de (hw2reg.loc_alert_cause[2].de), +- .d (hw2reg.loc_alert_cause[2].d ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.loc_alert_cause[2].q ), +- +- // to register interface (read) +- .qs (loc_alert_cause_la2_qs) +- ); +- +- +- // F[la3]: 3:3 +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h0) +- ) u_loc_alert_cause_la3 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (loc_alert_cause_la3_we), +- .wd (loc_alert_cause_la3_wd), +- +- // from internal hardware +- .de (hw2reg.loc_alert_cause[3].de), +- .d (hw2reg.loc_alert_cause[3].d ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.loc_alert_cause[3].q ), +- +- // to register interface (read) +- .qs (loc_alert_cause_la3_qs) +- ); +- +- +- +- // R[classa_ctrl]: V(False) +- +- // F[en]: 0:0 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_classa_ctrl_en ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_ctrl_en_we & regen_qs), +- .wd (classa_ctrl_en_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_ctrl.en.q ), +- +- // to register interface (read) +- .qs (classa_ctrl_en_qs) +- ); +- +- +- // F[lock]: 1:1 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_classa_ctrl_lock ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_ctrl_lock_we & regen_qs), +- .wd (classa_ctrl_lock_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_ctrl.lock.q ), +- +- // to register interface (read) +- .qs (classa_ctrl_lock_qs) +- ); +- +- +- // F[en_e0]: 2:2 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classa_ctrl_en_e0 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_ctrl_en_e0_we & regen_qs), +- .wd (classa_ctrl_en_e0_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_ctrl.en_e0.q ), +- +- // to register interface (read) +- .qs (classa_ctrl_en_e0_qs) +- ); +- +- +- // F[en_e1]: 3:3 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classa_ctrl_en_e1 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_ctrl_en_e1_we & regen_qs), +- .wd (classa_ctrl_en_e1_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_ctrl.en_e1.q ), +- +- // to register interface (read) +- .qs (classa_ctrl_en_e1_qs) +- ); +- +- +- // F[en_e2]: 4:4 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classa_ctrl_en_e2 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_ctrl_en_e2_we & regen_qs), +- .wd (classa_ctrl_en_e2_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_ctrl.en_e2.q ), +- +- // to register interface (read) +- .qs (classa_ctrl_en_e2_qs) +- ); +- +- +- // F[en_e3]: 5:5 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classa_ctrl_en_e3 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_ctrl_en_e3_we & regen_qs), +- .wd (classa_ctrl_en_e3_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_ctrl.en_e3.q ), +- +- // to register interface (read) +- .qs (classa_ctrl_en_e3_qs) +- ); +- +- +- // F[map_e0]: 7:6 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h0) +- ) u_classa_ctrl_map_e0 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_ctrl_map_e0_we & regen_qs), +- .wd (classa_ctrl_map_e0_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_ctrl.map_e0.q ), +- +- // to register interface (read) +- .qs (classa_ctrl_map_e0_qs) +- ); +- +- +- // F[map_e1]: 9:8 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h1) +- ) u_classa_ctrl_map_e1 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_ctrl_map_e1_we & regen_qs), +- .wd (classa_ctrl_map_e1_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_ctrl.map_e1.q ), +- +- // to register interface (read) +- .qs (classa_ctrl_map_e1_qs) +- ); +- +- +- // F[map_e2]: 11:10 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h2) +- ) u_classa_ctrl_map_e2 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_ctrl_map_e2_we & regen_qs), +- .wd (classa_ctrl_map_e2_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_ctrl.map_e2.q ), +- +- // to register interface (read) +- .qs (classa_ctrl_map_e2_qs) +- ); +- +- +- // F[map_e3]: 13:12 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h3) +- ) u_classa_ctrl_map_e3 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_ctrl_map_e3_we & regen_qs), +- .wd (classa_ctrl_map_e3_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_ctrl.map_e3.q ), +- +- // to register interface (read) +- .qs (classa_ctrl_map_e3_qs) +- ); +- +- +- // R[classa_clren]: V(False) +- +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h1) +- ) u_classa_clren ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (classa_clren_we), +- .wd (classa_clren_wd), +- +- // from internal hardware +- .de (hw2reg.classa_clren.de), +- .d (hw2reg.classa_clren.d ), +- +- // to internal hardware +- .qe (), +- .q (), +- +- // to register interface (read) +- .qs (classa_clren_qs) +- ); +- +- +- // R[classa_clr]: V(False) +- +- prim_subreg #( +- .DW (1), +- .SWACCESS("WO"), +- .RESVAL (1'h0) +- ) u_classa_clr ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_clr_we & classa_clren_qs), +- .wd (classa_clr_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (reg2hw.classa_clr.qe), +- .q (reg2hw.classa_clr.q ), +- +- .qs () +- ); +- +- +- // R[classa_accum_cnt]: V(True) +- +- prim_subreg_ext #( +- .DW (16) +- ) u_classa_accum_cnt ( +- .re (classa_accum_cnt_re), +- .we (1'b0), +- .wd ('0), +- .d (hw2reg.classa_accum_cnt.d), +- .qre (), +- .qe (), +- .q (), +- .qs (classa_accum_cnt_qs) +- ); +- +- +- // R[classa_accum_thresh]: V(False) +- +- prim_subreg #( +- .DW (16), +- .SWACCESS("RW"), +- .RESVAL (16'h0) +- ) u_classa_accum_thresh ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_accum_thresh_we & regen_qs), +- .wd (classa_accum_thresh_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_accum_thresh.q ), +- +- // to register interface (read) +- .qs (classa_accum_thresh_qs) +- ); +- +- +- // R[classa_timeout_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classa_timeout_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_timeout_cyc_we & regen_qs), +- .wd (classa_timeout_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_timeout_cyc.q ), +- +- // to register interface (read) +- .qs (classa_timeout_cyc_qs) +- ); +- +- +- // R[classa_phase0_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classa_phase0_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_phase0_cyc_we & regen_qs), +- .wd (classa_phase0_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_phase0_cyc.q ), +- +- // to register interface (read) +- .qs (classa_phase0_cyc_qs) +- ); +- +- +- // R[classa_phase1_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classa_phase1_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_phase1_cyc_we & regen_qs), +- .wd (classa_phase1_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_phase1_cyc.q ), +- +- // to register interface (read) +- .qs (classa_phase1_cyc_qs) +- ); +- +- +- // R[classa_phase2_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classa_phase2_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_phase2_cyc_we & regen_qs), +- .wd (classa_phase2_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_phase2_cyc.q ), +- +- // to register interface (read) +- .qs (classa_phase2_cyc_qs) +- ); +- +- +- // R[classa_phase3_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classa_phase3_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classa_phase3_cyc_we & regen_qs), +- .wd (classa_phase3_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classa_phase3_cyc.q ), +- +- // to register interface (read) +- .qs (classa_phase3_cyc_qs) +- ); +- +- +- // R[classa_esc_cnt]: V(True) +- +- prim_subreg_ext #( +- .DW (32) +- ) u_classa_esc_cnt ( +- .re (classa_esc_cnt_re), +- .we (1'b0), +- .wd ('0), +- .d (hw2reg.classa_esc_cnt.d), +- .qre (), +- .qe (), +- .q (), +- .qs (classa_esc_cnt_qs) +- ); +- +- +- // R[classa_state]: V(True) +- +- prim_subreg_ext #( +- .DW (3) +- ) u_classa_state ( +- .re (classa_state_re), +- .we (1'b0), +- .wd ('0), +- .d (hw2reg.classa_state.d), +- .qre (), +- .qe (), +- .q (), +- .qs (classa_state_qs) +- ); +- +- +- // R[classb_ctrl]: V(False) +- +- // F[en]: 0:0 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_classb_ctrl_en ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_ctrl_en_we & regen_qs), +- .wd (classb_ctrl_en_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_ctrl.en.q ), +- +- // to register interface (read) +- .qs (classb_ctrl_en_qs) +- ); +- +- +- // F[lock]: 1:1 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_classb_ctrl_lock ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_ctrl_lock_we & regen_qs), +- .wd (classb_ctrl_lock_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_ctrl.lock.q ), +- +- // to register interface (read) +- .qs (classb_ctrl_lock_qs) +- ); +- +- +- // F[en_e0]: 2:2 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classb_ctrl_en_e0 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_ctrl_en_e0_we & regen_qs), +- .wd (classb_ctrl_en_e0_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_ctrl.en_e0.q ), +- +- // to register interface (read) +- .qs (classb_ctrl_en_e0_qs) +- ); +- +- +- // F[en_e1]: 3:3 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classb_ctrl_en_e1 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_ctrl_en_e1_we & regen_qs), +- .wd (classb_ctrl_en_e1_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_ctrl.en_e1.q ), +- +- // to register interface (read) +- .qs (classb_ctrl_en_e1_qs) +- ); +- +- +- // F[en_e2]: 4:4 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classb_ctrl_en_e2 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_ctrl_en_e2_we & regen_qs), +- .wd (classb_ctrl_en_e2_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_ctrl.en_e2.q ), +- +- // to register interface (read) +- .qs (classb_ctrl_en_e2_qs) +- ); +- +- +- // F[en_e3]: 5:5 + prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classb_ctrl_en_e3 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_ctrl_en_e3_we & regen_qs), +- .wd (classb_ctrl_en_e3_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_ctrl.en_e3.q ), +- +- // to register interface (read) +- .qs (classb_ctrl_en_e3_qs) ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h0) ++ ) u_intr_state_classa( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(intr_state_classa_we), ++ .wd(intr_state_classa_wd), ++ .de(hw2reg[236]), ++ .d(hw2reg[237]), ++ .qe(), ++ .q(reg2hw[844]), ++ .qs(intr_state_classa_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h0) ++ ) u_intr_state_classb( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(intr_state_classb_we), ++ .wd(intr_state_classb_wd), ++ .de(hw2reg[234]), ++ .d(hw2reg[235]), ++ .qe(), ++ .q(reg2hw[843]), ++ .qs(intr_state_classb_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h0) ++ ) u_intr_state_classc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(intr_state_classc_we), ++ .wd(intr_state_classc_wd), ++ .de(hw2reg[232]), ++ .d(hw2reg[233]), ++ .qe(), ++ .q(reg2hw[842]), ++ .qs(intr_state_classc_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h0) ++ ) u_intr_state_classd( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(intr_state_classd_we), ++ .wd(intr_state_classd_wd), ++ .de(hw2reg[230]), ++ .d(hw2reg[231]), ++ .qe(), ++ .q(reg2hw[841]), ++ .qs(intr_state_classd_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_intr_enable_classa( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(intr_enable_classa_we), ++ .wd(intr_enable_classa_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[840]), ++ .qs(intr_enable_classa_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_intr_enable_classb( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(intr_enable_classb_we), ++ .wd(intr_enable_classb_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[839]), ++ .qs(intr_enable_classb_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_intr_enable_classc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(intr_enable_classc_we), ++ .wd(intr_enable_classc_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[838]), ++ .qs(intr_enable_classc_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_intr_enable_classd( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(intr_enable_classd_we), ++ .wd(intr_enable_classd_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[837]), ++ .qs(intr_enable_classd_qs) ++ ); ++ prim_subreg_ext #(.DW(1)) u_intr_test_classa( ++ .re(1'b0), ++ .we(intr_test_classa_we), ++ .wd(intr_test_classa_wd), ++ .d(1'b0), ++ .qre(), ++ .qe(reg2hw[835]), ++ .q(reg2hw[836]), ++ .qs() ++ ); ++ prim_subreg_ext #(.DW(1)) u_intr_test_classb( ++ .re(1'b0), ++ .we(intr_test_classb_we), ++ .wd(intr_test_classb_wd), ++ .d(1'b0), ++ .qre(), ++ .qe(reg2hw[833]), ++ .q(reg2hw[834]), ++ .qs() ++ ); ++ prim_subreg_ext #(.DW(1)) u_intr_test_classc( ++ .re(1'b0), ++ .we(intr_test_classc_we), ++ .wd(intr_test_classc_wd), ++ .d(1'b0), ++ .qre(), ++ .qe(reg2hw[831]), ++ .q(reg2hw[832]), ++ .qs() ++ ); ++ prim_subreg_ext #(.DW(1)) u_intr_test_classd( ++ .re(1'b0), ++ .we(intr_test_classd_we), ++ .wd(intr_test_classd_wd), ++ .d(1'b0), ++ .qre(), ++ .qe(reg2hw[829]), ++ .q(reg2hw[830]), ++ .qs() ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h1) ++ ) u_regen( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(regen_we), ++ .wd(regen_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[828]), ++ .qs(regen_qs) ++ ); ++ prim_subreg #( ++ .DW(24), ++ .SWACCESS("RW"), ++ .RESVAL(24'h000020) ++ ) u_ping_timeout_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(ping_timeout_cyc_we & regen_qs), ++ .wd(ping_timeout_cyc_wd), ++ .de(1'b0), ++ .d({24 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[827-:24]), ++ .qs(ping_timeout_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_alert_en_en_a0( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(alert_en_en_a0_we & regen_qs), ++ .wd(alert_en_en_a0_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[799]), ++ .qs(alert_en_en_a0_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_alert_en_en_a1( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(alert_en_en_a1_we & regen_qs), ++ .wd(alert_en_en_a1_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[800]), ++ .qs(alert_en_en_a1_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_alert_en_en_a2( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(alert_en_en_a2_we & regen_qs), ++ .wd(alert_en_en_a2_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[801]), ++ .qs(alert_en_en_a2_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_alert_en_en_a3( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(alert_en_en_a3_we & regen_qs), ++ .wd(alert_en_en_a3_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[802]), ++ .qs(alert_en_en_a3_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_alert_en_en_a4( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(alert_en_en_a4_we & regen_qs), ++ .wd(alert_en_en_a4_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[803]), ++ .qs(alert_en_en_a4_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h0) ++ ) u_alert_class_class_a0( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(alert_class_class_a0_we & regen_qs), ++ .wd(alert_class_class_a0_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[790-:2]), ++ .qs(alert_class_class_a0_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h0) ++ ) u_alert_class_class_a1( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(alert_class_class_a1_we & regen_qs), ++ .wd(alert_class_class_a1_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[792-:2]), ++ .qs(alert_class_class_a1_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h0) ++ ) u_alert_class_class_a2( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(alert_class_class_a2_we & regen_qs), ++ .wd(alert_class_class_a2_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[794-:2]), ++ .qs(alert_class_class_a2_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h0) ++ ) u_alert_class_class_a3( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(alert_class_class_a3_we & regen_qs), ++ .wd(alert_class_class_a3_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[796-:2]), ++ .qs(alert_class_class_a3_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h0) ++ ) u_alert_class_class_a4( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(alert_class_class_a4_we & regen_qs), ++ .wd(alert_class_class_a4_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[798-:2]), ++ .qs(alert_class_class_a4_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h0) ++ ) u_alert_cause_a0( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(alert_cause_a0_we), ++ .wd(alert_cause_a0_wd), ++ .de(hw2reg[220]), ++ .d(hw2reg[221]), ++ .qe(), ++ .q(reg2hw[784]), ++ .qs(alert_cause_a0_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h0) ++ ) u_alert_cause_a1( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(alert_cause_a1_we), ++ .wd(alert_cause_a1_wd), ++ .de(hw2reg[222]), ++ .d(hw2reg[223]), ++ .qe(), ++ .q(reg2hw[785]), ++ .qs(alert_cause_a1_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h0) ++ ) u_alert_cause_a2( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(alert_cause_a2_we), ++ .wd(alert_cause_a2_wd), ++ .de(hw2reg[224]), ++ .d(hw2reg[225]), ++ .qe(), ++ .q(reg2hw[786]), ++ .qs(alert_cause_a2_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h0) ++ ) u_alert_cause_a3( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(alert_cause_a3_we), ++ .wd(alert_cause_a3_wd), ++ .de(hw2reg[226]), ++ .d(hw2reg[227]), ++ .qe(), ++ .q(reg2hw[787]), ++ .qs(alert_cause_a3_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h0) ++ ) u_alert_cause_a4( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(alert_cause_a4_we), ++ .wd(alert_cause_a4_wd), ++ .de(hw2reg[228]), ++ .d(hw2reg[229]), ++ .qe(), ++ .q(reg2hw[788]), ++ .qs(alert_cause_a4_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_loc_alert_en_en_la0( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(loc_alert_en_en_la0_we & regen_qs), ++ .wd(loc_alert_en_en_la0_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[780]), ++ .qs(loc_alert_en_en_la0_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_loc_alert_en_en_la1( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(loc_alert_en_en_la1_we & regen_qs), ++ .wd(loc_alert_en_en_la1_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[781]), ++ .qs(loc_alert_en_en_la1_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_loc_alert_en_en_la2( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(loc_alert_en_en_la2_we & regen_qs), ++ .wd(loc_alert_en_en_la2_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[782]), ++ .qs(loc_alert_en_en_la2_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_loc_alert_en_en_la3( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(loc_alert_en_en_la3_we & regen_qs), ++ .wd(loc_alert_en_en_la3_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[783]), ++ .qs(loc_alert_en_en_la3_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h0) ++ ) u_loc_alert_class_class_la0( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(loc_alert_class_class_la0_we & regen_qs), ++ .wd(loc_alert_class_class_la0_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[773-:2]), ++ .qs(loc_alert_class_class_la0_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h0) ++ ) u_loc_alert_class_class_la1( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(loc_alert_class_class_la1_we & regen_qs), ++ .wd(loc_alert_class_class_la1_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[775-:2]), ++ .qs(loc_alert_class_class_la1_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h0) ++ ) u_loc_alert_class_class_la2( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(loc_alert_class_class_la2_we & regen_qs), ++ .wd(loc_alert_class_class_la2_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[777-:2]), ++ .qs(loc_alert_class_class_la2_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h0) ++ ) u_loc_alert_class_class_la3( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(loc_alert_class_class_la3_we & regen_qs), ++ .wd(loc_alert_class_class_la3_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[779-:2]), ++ .qs(loc_alert_class_class_la3_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h0) ++ ) u_loc_alert_cause_la0( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(loc_alert_cause_la0_we), ++ .wd(loc_alert_cause_la0_wd), ++ .de(hw2reg[212]), ++ .d(hw2reg[213]), ++ .qe(), ++ .q(reg2hw[768]), ++ .qs(loc_alert_cause_la0_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h0) ++ ) u_loc_alert_cause_la1( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(loc_alert_cause_la1_we), ++ .wd(loc_alert_cause_la1_wd), ++ .de(hw2reg[214]), ++ .d(hw2reg[215]), ++ .qe(), ++ .q(reg2hw[769]), ++ .qs(loc_alert_cause_la1_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h0) ++ ) u_loc_alert_cause_la2( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(loc_alert_cause_la2_we), ++ .wd(loc_alert_cause_la2_wd), ++ .de(hw2reg[216]), ++ .d(hw2reg[217]), ++ .qe(), ++ .q(reg2hw[770]), ++ .qs(loc_alert_cause_la2_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h0) ++ ) u_loc_alert_cause_la3( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(loc_alert_cause_la3_we), ++ .wd(loc_alert_cause_la3_wd), ++ .de(hw2reg[218]), ++ .d(hw2reg[219]), ++ .qe(), ++ .q(reg2hw[771]), ++ .qs(loc_alert_cause_la3_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_classa_ctrl_en( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_ctrl_en_we & regen_qs), ++ .wd(classa_ctrl_en_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[767]), ++ .qs(classa_ctrl_en_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_classa_ctrl_lock( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_ctrl_lock_we & regen_qs), ++ .wd(classa_ctrl_lock_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[766]), ++ .qs(classa_ctrl_lock_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classa_ctrl_en_e0( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_ctrl_en_e0_we & regen_qs), ++ .wd(classa_ctrl_en_e0_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[765]), ++ .qs(classa_ctrl_en_e0_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classa_ctrl_en_e1( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_ctrl_en_e1_we & regen_qs), ++ .wd(classa_ctrl_en_e1_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[764]), ++ .qs(classa_ctrl_en_e1_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classa_ctrl_en_e2( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_ctrl_en_e2_we & regen_qs), ++ .wd(classa_ctrl_en_e2_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[763]), ++ .qs(classa_ctrl_en_e2_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classa_ctrl_en_e3( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_ctrl_en_e3_we & regen_qs), ++ .wd(classa_ctrl_en_e3_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[762]), ++ .qs(classa_ctrl_en_e3_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h0) ++ ) u_classa_ctrl_map_e0( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_ctrl_map_e0_we & regen_qs), ++ .wd(classa_ctrl_map_e0_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[761-:2]), ++ .qs(classa_ctrl_map_e0_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h1) ++ ) u_classa_ctrl_map_e1( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_ctrl_map_e1_we & regen_qs), ++ .wd(classa_ctrl_map_e1_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[759-:2]), ++ .qs(classa_ctrl_map_e1_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h2) ++ ) u_classa_ctrl_map_e2( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_ctrl_map_e2_we & regen_qs), ++ .wd(classa_ctrl_map_e2_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[757-:2]), ++ .qs(classa_ctrl_map_e2_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h3) ++ ) u_classa_ctrl_map_e3( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_ctrl_map_e3_we & regen_qs), ++ .wd(classa_ctrl_map_e3_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[755-:2]), ++ .qs(classa_ctrl_map_e3_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h1) ++ ) u_classa_clren( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_clren_we), ++ .wd(classa_clren_wd), ++ .de(hw2reg[210]), ++ .d(hw2reg[211]), ++ .qe(), ++ .q(), ++ .qs(classa_clren_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("WO"), ++ .RESVAL(1'h0) ++ ) u_classa_clr( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_clr_we & classa_clren_qs), ++ .wd(classa_clr_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(reg2hw[752]), ++ .q(reg2hw[753]), ++ .qs() ++ ); ++ prim_subreg_ext #(.DW(16)) u_classa_accum_cnt( ++ .re(classa_accum_cnt_re), ++ .we(1'b0), ++ .wd({16 {1'sb0}}), ++ .d(hw2reg[209-:16]), ++ .qre(), ++ .qe(), ++ .q(), ++ .qs(classa_accum_cnt_qs) ++ ); ++ prim_subreg #( ++ .DW(16), ++ .SWACCESS("RW"), ++ .RESVAL(16'h0000) ++ ) u_classa_accum_thresh( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_accum_thresh_we & regen_qs), ++ .wd(classa_accum_thresh_wd), ++ .de(1'b0), ++ .d({16 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[751-:16]), ++ .qs(classa_accum_thresh_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classa_timeout_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_timeout_cyc_we & regen_qs), ++ .wd(classa_timeout_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[735-:32]), ++ .qs(classa_timeout_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classa_phase0_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_phase0_cyc_we & regen_qs), ++ .wd(classa_phase0_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[703-:32]), ++ .qs(classa_phase0_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classa_phase1_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_phase1_cyc_we & regen_qs), ++ .wd(classa_phase1_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[671-:32]), ++ .qs(classa_phase1_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classa_phase2_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_phase2_cyc_we & regen_qs), ++ .wd(classa_phase2_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[639-:32]), ++ .qs(classa_phase2_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classa_phase3_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classa_phase3_cyc_we & regen_qs), ++ .wd(classa_phase3_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[607-:32]), ++ .qs(classa_phase3_cyc_qs) ++ ); ++ prim_subreg_ext #(.DW(32)) u_classa_esc_cnt( ++ .re(classa_esc_cnt_re), ++ .we(1'b0), ++ .wd({32 {1'sb0}}), ++ .d(hw2reg[193-:32]), ++ .qre(), ++ .qe(), ++ .q(), ++ .qs(classa_esc_cnt_qs) ++ ); ++ prim_subreg_ext #(.DW(3)) u_classa_state( ++ .re(classa_state_re), ++ .we(1'b0), ++ .wd({3 {1'sb0}}), ++ .d(hw2reg[161-:3]), ++ .qre(), ++ .qe(), ++ .q(), ++ .qs(classa_state_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_classb_ctrl_en( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_ctrl_en_we & regen_qs), ++ .wd(classb_ctrl_en_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[575]), ++ .qs(classb_ctrl_en_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_classb_ctrl_lock( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_ctrl_lock_we & regen_qs), ++ .wd(classb_ctrl_lock_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[574]), ++ .qs(classb_ctrl_lock_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classb_ctrl_en_e0( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_ctrl_en_e0_we & regen_qs), ++ .wd(classb_ctrl_en_e0_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[573]), ++ .qs(classb_ctrl_en_e0_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classb_ctrl_en_e1( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_ctrl_en_e1_we & regen_qs), ++ .wd(classb_ctrl_en_e1_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[572]), ++ .qs(classb_ctrl_en_e1_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classb_ctrl_en_e2( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_ctrl_en_e2_we & regen_qs), ++ .wd(classb_ctrl_en_e2_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[571]), ++ .qs(classb_ctrl_en_e2_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classb_ctrl_en_e3( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_ctrl_en_e3_we & regen_qs), ++ .wd(classb_ctrl_en_e3_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[570]), ++ .qs(classb_ctrl_en_e3_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h0) ++ ) u_classb_ctrl_map_e0( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_ctrl_map_e0_we & regen_qs), ++ .wd(classb_ctrl_map_e0_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[569-:2]), ++ .qs(classb_ctrl_map_e0_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h1) ++ ) u_classb_ctrl_map_e1( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_ctrl_map_e1_we & regen_qs), ++ .wd(classb_ctrl_map_e1_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[567-:2]), ++ .qs(classb_ctrl_map_e1_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h2) ++ ) u_classb_ctrl_map_e2( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_ctrl_map_e2_we & regen_qs), ++ .wd(classb_ctrl_map_e2_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[565-:2]), ++ .qs(classb_ctrl_map_e2_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h3) ++ ) u_classb_ctrl_map_e3( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_ctrl_map_e3_we & regen_qs), ++ .wd(classb_ctrl_map_e3_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[563-:2]), ++ .qs(classb_ctrl_map_e3_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h1) ++ ) u_classb_clren( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_clren_we), ++ .wd(classb_clren_wd), ++ .de(hw2reg[157]), ++ .d(hw2reg[158]), ++ .qe(), ++ .q(), ++ .qs(classb_clren_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("WO"), ++ .RESVAL(1'h0) ++ ) u_classb_clr( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_clr_we & classb_clren_qs), ++ .wd(classb_clr_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(reg2hw[560]), ++ .q(reg2hw[561]), ++ .qs() ++ ); ++ prim_subreg_ext #(.DW(16)) u_classb_accum_cnt( ++ .re(classb_accum_cnt_re), ++ .we(1'b0), ++ .wd({16 {1'sb0}}), ++ .d(hw2reg[156-:16]), ++ .qre(), ++ .qe(), ++ .q(), ++ .qs(classb_accum_cnt_qs) ++ ); ++ prim_subreg #( ++ .DW(16), ++ .SWACCESS("RW"), ++ .RESVAL(16'h0000) ++ ) u_classb_accum_thresh( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_accum_thresh_we & regen_qs), ++ .wd(classb_accum_thresh_wd), ++ .de(1'b0), ++ .d({16 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[559-:16]), ++ .qs(classb_accum_thresh_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classb_timeout_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_timeout_cyc_we & regen_qs), ++ .wd(classb_timeout_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[543-:32]), ++ .qs(classb_timeout_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classb_phase0_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_phase0_cyc_we & regen_qs), ++ .wd(classb_phase0_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[511-:32]), ++ .qs(classb_phase0_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classb_phase1_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_phase1_cyc_we & regen_qs), ++ .wd(classb_phase1_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[479-:32]), ++ .qs(classb_phase1_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classb_phase2_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_phase2_cyc_we & regen_qs), ++ .wd(classb_phase2_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[447-:32]), ++ .qs(classb_phase2_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classb_phase3_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classb_phase3_cyc_we & regen_qs), ++ .wd(classb_phase3_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[415-:32]), ++ .qs(classb_phase3_cyc_qs) ++ ); ++ prim_subreg_ext #(.DW(32)) u_classb_esc_cnt( ++ .re(classb_esc_cnt_re), ++ .we(1'b0), ++ .wd({32 {1'sb0}}), ++ .d(hw2reg[140-:32]), ++ .qre(), ++ .qe(), ++ .q(), ++ .qs(classb_esc_cnt_qs) ++ ); ++ prim_subreg_ext #(.DW(3)) u_classb_state( ++ .re(classb_state_re), ++ .we(1'b0), ++ .wd({3 {1'sb0}}), ++ .d(hw2reg[108-:3]), ++ .qre(), ++ .qe(), ++ .q(), ++ .qs(classb_state_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_classc_ctrl_en( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_ctrl_en_we & regen_qs), ++ .wd(classc_ctrl_en_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[383]), ++ .qs(classc_ctrl_en_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_classc_ctrl_lock( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_ctrl_lock_we & regen_qs), ++ .wd(classc_ctrl_lock_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[382]), ++ .qs(classc_ctrl_lock_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classc_ctrl_en_e0( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_ctrl_en_e0_we & regen_qs), ++ .wd(classc_ctrl_en_e0_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[381]), ++ .qs(classc_ctrl_en_e0_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classc_ctrl_en_e1( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_ctrl_en_e1_we & regen_qs), ++ .wd(classc_ctrl_en_e1_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[380]), ++ .qs(classc_ctrl_en_e1_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classc_ctrl_en_e2( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_ctrl_en_e2_we & regen_qs), ++ .wd(classc_ctrl_en_e2_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[379]), ++ .qs(classc_ctrl_en_e2_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classc_ctrl_en_e3( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_ctrl_en_e3_we & regen_qs), ++ .wd(classc_ctrl_en_e3_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[378]), ++ .qs(classc_ctrl_en_e3_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h0) ++ ) u_classc_ctrl_map_e0( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_ctrl_map_e0_we & regen_qs), ++ .wd(classc_ctrl_map_e0_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[377-:2]), ++ .qs(classc_ctrl_map_e0_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h1) ++ ) u_classc_ctrl_map_e1( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_ctrl_map_e1_we & regen_qs), ++ .wd(classc_ctrl_map_e1_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[375-:2]), ++ .qs(classc_ctrl_map_e1_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h2) ++ ) u_classc_ctrl_map_e2( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_ctrl_map_e2_we & regen_qs), ++ .wd(classc_ctrl_map_e2_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[373-:2]), ++ .qs(classc_ctrl_map_e2_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h3) ++ ) u_classc_ctrl_map_e3( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_ctrl_map_e3_we & regen_qs), ++ .wd(classc_ctrl_map_e3_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[371-:2]), ++ .qs(classc_ctrl_map_e3_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h1) ++ ) u_classc_clren( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_clren_we), ++ .wd(classc_clren_wd), ++ .de(hw2reg[104]), ++ .d(hw2reg[105]), ++ .qe(), ++ .q(), ++ .qs(classc_clren_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("WO"), ++ .RESVAL(1'h0) ++ ) u_classc_clr( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_clr_we & classc_clren_qs), ++ .wd(classc_clr_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(reg2hw[368]), ++ .q(reg2hw[369]), ++ .qs() ++ ); ++ prim_subreg_ext #(.DW(16)) u_classc_accum_cnt( ++ .re(classc_accum_cnt_re), ++ .we(1'b0), ++ .wd({16 {1'sb0}}), ++ .d(hw2reg[103-:16]), ++ .qre(), ++ .qe(), ++ .q(), ++ .qs(classc_accum_cnt_qs) ++ ); ++ prim_subreg #( ++ .DW(16), ++ .SWACCESS("RW"), ++ .RESVAL(16'h0000) ++ ) u_classc_accum_thresh( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_accum_thresh_we & regen_qs), ++ .wd(classc_accum_thresh_wd), ++ .de(1'b0), ++ .d({16 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[367-:16]), ++ .qs(classc_accum_thresh_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classc_timeout_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_timeout_cyc_we & regen_qs), ++ .wd(classc_timeout_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[351-:32]), ++ .qs(classc_timeout_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classc_phase0_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_phase0_cyc_we & regen_qs), ++ .wd(classc_phase0_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[319-:32]), ++ .qs(classc_phase0_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classc_phase1_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_phase1_cyc_we & regen_qs), ++ .wd(classc_phase1_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[287-:32]), ++ .qs(classc_phase1_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classc_phase2_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_phase2_cyc_we & regen_qs), ++ .wd(classc_phase2_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[255-:32]), ++ .qs(classc_phase2_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classc_phase3_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classc_phase3_cyc_we & regen_qs), ++ .wd(classc_phase3_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[223-:32]), ++ .qs(classc_phase3_cyc_qs) ++ ); ++ prim_subreg_ext #(.DW(32)) u_classc_esc_cnt( ++ .re(classc_esc_cnt_re), ++ .we(1'b0), ++ .wd({32 {1'sb0}}), ++ .d(hw2reg[87-:32]), ++ .qre(), ++ .qe(), ++ .q(), ++ .qs(classc_esc_cnt_qs) ++ ); ++ prim_subreg_ext #(.DW(3)) u_classc_state( ++ .re(classc_state_re), ++ .we(1'b0), ++ .wd({3 {1'sb0}}), ++ .d(hw2reg[55-:3]), ++ .qre(), ++ .qe(), ++ .q(), ++ .qs(classc_state_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_classd_ctrl_en( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_ctrl_en_we & regen_qs), ++ .wd(classd_ctrl_en_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[191]), ++ .qs(classd_ctrl_en_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h0) ++ ) u_classd_ctrl_lock( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_ctrl_lock_we & regen_qs), ++ .wd(classd_ctrl_lock_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[190]), ++ .qs(classd_ctrl_lock_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classd_ctrl_en_e0( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_ctrl_en_e0_we & regen_qs), ++ .wd(classd_ctrl_en_e0_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[189]), ++ .qs(classd_ctrl_en_e0_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classd_ctrl_en_e1( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_ctrl_en_e1_we & regen_qs), ++ .wd(classd_ctrl_en_e1_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[188]), ++ .qs(classd_ctrl_en_e1_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classd_ctrl_en_e2( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_ctrl_en_e2_we & regen_qs), ++ .wd(classd_ctrl_en_e2_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[187]), ++ .qs(classd_ctrl_en_e2_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("RW"), ++ .RESVAL(1'h1) ++ ) u_classd_ctrl_en_e3( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_ctrl_en_e3_we & regen_qs), ++ .wd(classd_ctrl_en_e3_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(), ++ .q(reg2hw[186]), ++ .qs(classd_ctrl_en_e3_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h0) ++ ) u_classd_ctrl_map_e0( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_ctrl_map_e0_we & regen_qs), ++ .wd(classd_ctrl_map_e0_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[185-:2]), ++ .qs(classd_ctrl_map_e0_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h1) ++ ) u_classd_ctrl_map_e1( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_ctrl_map_e1_we & regen_qs), ++ .wd(classd_ctrl_map_e1_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[183-:2]), ++ .qs(classd_ctrl_map_e1_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h2) ++ ) u_classd_ctrl_map_e2( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_ctrl_map_e2_we & regen_qs), ++ .wd(classd_ctrl_map_e2_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[181-:2]), ++ .qs(classd_ctrl_map_e2_qs) ++ ); ++ prim_subreg #( ++ .DW(2), ++ .SWACCESS("RW"), ++ .RESVAL(2'h3) ++ ) u_classd_ctrl_map_e3( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_ctrl_map_e3_we & regen_qs), ++ .wd(classd_ctrl_map_e3_wd), ++ .de(1'b0), ++ .d({2 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[179-:2]), ++ .qs(classd_ctrl_map_e3_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("W1C"), ++ .RESVAL(1'h1) ++ ) u_classd_clren( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_clren_we), ++ .wd(classd_clren_wd), ++ .de(hw2reg[51]), ++ .d(hw2reg[52]), ++ .qe(), ++ .q(), ++ .qs(classd_clren_qs) ++ ); ++ prim_subreg #( ++ .DW(1), ++ .SWACCESS("WO"), ++ .RESVAL(1'h0) ++ ) u_classd_clr( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_clr_we & classd_clren_qs), ++ .wd(classd_clr_wd), ++ .de(1'b0), ++ .d(1'b0), ++ .qe(reg2hw[176]), ++ .q(reg2hw[177]), ++ .qs() ++ ); ++ prim_subreg_ext #(.DW(16)) u_classd_accum_cnt( ++ .re(classd_accum_cnt_re), ++ .we(1'b0), ++ .wd({16 {1'sb0}}), ++ .d(hw2reg[50-:16]), ++ .qre(), ++ .qe(), ++ .q(), ++ .qs(classd_accum_cnt_qs) ++ ); ++ prim_subreg #( ++ .DW(16), ++ .SWACCESS("RW"), ++ .RESVAL(16'h0000) ++ ) u_classd_accum_thresh( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_accum_thresh_we & regen_qs), ++ .wd(classd_accum_thresh_wd), ++ .de(1'b0), ++ .d({16 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[175-:16]), ++ .qs(classd_accum_thresh_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classd_timeout_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_timeout_cyc_we & regen_qs), ++ .wd(classd_timeout_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[159-:32]), ++ .qs(classd_timeout_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classd_phase0_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_phase0_cyc_we & regen_qs), ++ .wd(classd_phase0_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[127-:32]), ++ .qs(classd_phase0_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classd_phase1_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_phase1_cyc_we & regen_qs), ++ .wd(classd_phase1_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[95-:32]), ++ .qs(classd_phase1_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classd_phase2_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_phase2_cyc_we & regen_qs), ++ .wd(classd_phase2_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[63-:32]), ++ .qs(classd_phase2_cyc_qs) ++ ); ++ prim_subreg #( ++ .DW(32), ++ .SWACCESS("RW"), ++ .RESVAL(32'h00000000) ++ ) u_classd_phase3_cyc( ++ .clk_i(clk_i), ++ .rst_ni(rst_ni), ++ .we(classd_phase3_cyc_we & regen_qs), ++ .wd(classd_phase3_cyc_wd), ++ .de(1'b0), ++ .d({32 {1'sb0}}), ++ .qe(), ++ .q(reg2hw[31-:32]), ++ .qs(classd_phase3_cyc_qs) ++ ); ++ prim_subreg_ext #(.DW(32)) u_classd_esc_cnt( ++ .re(classd_esc_cnt_re), ++ .we(1'b0), ++ .wd({32 {1'sb0}}), ++ .d(hw2reg[34-:32]), ++ .qre(), ++ .qe(), ++ .q(), ++ .qs(classd_esc_cnt_qs) ++ ); ++ prim_subreg_ext #(.DW(3)) u_classd_state( ++ .re(classd_state_re), ++ .we(1'b0), ++ .wd({3 {1'sb0}}), ++ .d(hw2reg[2-:3]), ++ .qre(), ++ .qe(), ++ .q(), ++ .qs(classd_state_qs) + ); + + +- // F[map_e0]: 7:6 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h0) +- ) u_classb_ctrl_map_e0 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_ctrl_map_e0_we & regen_qs), +- .wd (classb_ctrl_map_e0_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_ctrl.map_e0.q ), +- +- // to register interface (read) +- .qs (classb_ctrl_map_e0_qs) +- ); +- +- +- // F[map_e1]: 9:8 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h1) +- ) u_classb_ctrl_map_e1 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_ctrl_map_e1_we & regen_qs), +- .wd (classb_ctrl_map_e1_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_ctrl.map_e1.q ), +- +- // to register interface (read) +- .qs (classb_ctrl_map_e1_qs) +- ); +- +- +- // F[map_e2]: 11:10 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h2) +- ) u_classb_ctrl_map_e2 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_ctrl_map_e2_we & regen_qs), +- .wd (classb_ctrl_map_e2_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_ctrl.map_e2.q ), +- +- // to register interface (read) +- .qs (classb_ctrl_map_e2_qs) +- ); +- +- +- // F[map_e3]: 13:12 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h3) +- ) u_classb_ctrl_map_e3 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_ctrl_map_e3_we & regen_qs), +- .wd (classb_ctrl_map_e3_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_ctrl.map_e3.q ), +- +- // to register interface (read) +- .qs (classb_ctrl_map_e3_qs) +- ); +- +- +- // R[classb_clren]: V(False) +- +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h1) +- ) u_classb_clren ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (classb_clren_we), +- .wd (classb_clren_wd), +- +- // from internal hardware +- .de (hw2reg.classb_clren.de), +- .d (hw2reg.classb_clren.d ), +- +- // to internal hardware +- .qe (), +- .q (), +- +- // to register interface (read) +- .qs (classb_clren_qs) +- ); +- +- +- // R[classb_clr]: V(False) +- +- prim_subreg #( +- .DW (1), +- .SWACCESS("WO"), +- .RESVAL (1'h0) +- ) u_classb_clr ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_clr_we & classb_clren_qs), +- .wd (classb_clr_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (reg2hw.classb_clr.qe), +- .q (reg2hw.classb_clr.q ), +- +- .qs () +- ); +- +- +- // R[classb_accum_cnt]: V(True) +- +- prim_subreg_ext #( +- .DW (16) +- ) u_classb_accum_cnt ( +- .re (classb_accum_cnt_re), +- .we (1'b0), +- .wd ('0), +- .d (hw2reg.classb_accum_cnt.d), +- .qre (), +- .qe (), +- .q (), +- .qs (classb_accum_cnt_qs) +- ); +- +- +- // R[classb_accum_thresh]: V(False) +- +- prim_subreg #( +- .DW (16), +- .SWACCESS("RW"), +- .RESVAL (16'h0) +- ) u_classb_accum_thresh ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_accum_thresh_we & regen_qs), +- .wd (classb_accum_thresh_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_accum_thresh.q ), +- +- // to register interface (read) +- .qs (classb_accum_thresh_qs) +- ); +- +- +- // R[classb_timeout_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classb_timeout_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_timeout_cyc_we & regen_qs), +- .wd (classb_timeout_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_timeout_cyc.q ), +- +- // to register interface (read) +- .qs (classb_timeout_cyc_qs) +- ); +- +- +- // R[classb_phase0_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classb_phase0_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_phase0_cyc_we & regen_qs), +- .wd (classb_phase0_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_phase0_cyc.q ), +- +- // to register interface (read) +- .qs (classb_phase0_cyc_qs) +- ); +- +- +- // R[classb_phase1_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classb_phase1_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_phase1_cyc_we & regen_qs), +- .wd (classb_phase1_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_phase1_cyc.q ), +- +- // to register interface (read) +- .qs (classb_phase1_cyc_qs) +- ); +- +- +- // R[classb_phase2_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classb_phase2_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_phase2_cyc_we & regen_qs), +- .wd (classb_phase2_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_phase2_cyc.q ), +- +- // to register interface (read) +- .qs (classb_phase2_cyc_qs) +- ); +- +- +- // R[classb_phase3_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classb_phase3_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classb_phase3_cyc_we & regen_qs), +- .wd (classb_phase3_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classb_phase3_cyc.q ), +- +- // to register interface (read) +- .qs (classb_phase3_cyc_qs) +- ); +- +- +- // R[classb_esc_cnt]: V(True) +- +- prim_subreg_ext #( +- .DW (32) +- ) u_classb_esc_cnt ( +- .re (classb_esc_cnt_re), +- .we (1'b0), +- .wd ('0), +- .d (hw2reg.classb_esc_cnt.d), +- .qre (), +- .qe (), +- .q (), +- .qs (classb_esc_cnt_qs) +- ); +- +- +- // R[classb_state]: V(True) +- +- prim_subreg_ext #( +- .DW (3) +- ) u_classb_state ( +- .re (classb_state_re), +- .we (1'b0), +- .wd ('0), +- .d (hw2reg.classb_state.d), +- .qre (), +- .qe (), +- .q (), +- .qs (classb_state_qs) +- ); +- +- +- // R[classc_ctrl]: V(False) +- +- // F[en]: 0:0 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_classc_ctrl_en ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_ctrl_en_we & regen_qs), +- .wd (classc_ctrl_en_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_ctrl.en.q ), +- +- // to register interface (read) +- .qs (classc_ctrl_en_qs) +- ); +- +- +- // F[lock]: 1:1 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_classc_ctrl_lock ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_ctrl_lock_we & regen_qs), +- .wd (classc_ctrl_lock_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_ctrl.lock.q ), +- +- // to register interface (read) +- .qs (classc_ctrl_lock_qs) +- ); +- +- +- // F[en_e0]: 2:2 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classc_ctrl_en_e0 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_ctrl_en_e0_we & regen_qs), +- .wd (classc_ctrl_en_e0_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_ctrl.en_e0.q ), +- +- // to register interface (read) +- .qs (classc_ctrl_en_e0_qs) +- ); +- +- +- // F[en_e1]: 3:3 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classc_ctrl_en_e1 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_ctrl_en_e1_we & regen_qs), +- .wd (classc_ctrl_en_e1_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_ctrl.en_e1.q ), +- +- // to register interface (read) +- .qs (classc_ctrl_en_e1_qs) +- ); +- +- +- // F[en_e2]: 4:4 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classc_ctrl_en_e2 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_ctrl_en_e2_we & regen_qs), +- .wd (classc_ctrl_en_e2_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_ctrl.en_e2.q ), +- +- // to register interface (read) +- .qs (classc_ctrl_en_e2_qs) +- ); +- +- +- // F[en_e3]: 5:5 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classc_ctrl_en_e3 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_ctrl_en_e3_we & regen_qs), +- .wd (classc_ctrl_en_e3_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_ctrl.en_e3.q ), +- +- // to register interface (read) +- .qs (classc_ctrl_en_e3_qs) +- ); +- +- +- // F[map_e0]: 7:6 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h0) +- ) u_classc_ctrl_map_e0 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_ctrl_map_e0_we & regen_qs), +- .wd (classc_ctrl_map_e0_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_ctrl.map_e0.q ), +- +- // to register interface (read) +- .qs (classc_ctrl_map_e0_qs) +- ); +- +- +- // F[map_e1]: 9:8 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h1) +- ) u_classc_ctrl_map_e1 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_ctrl_map_e1_we & regen_qs), +- .wd (classc_ctrl_map_e1_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_ctrl.map_e1.q ), +- +- // to register interface (read) +- .qs (classc_ctrl_map_e1_qs) +- ); +- +- +- // F[map_e2]: 11:10 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h2) +- ) u_classc_ctrl_map_e2 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_ctrl_map_e2_we & regen_qs), +- .wd (classc_ctrl_map_e2_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_ctrl.map_e2.q ), +- +- // to register interface (read) +- .qs (classc_ctrl_map_e2_qs) +- ); +- +- +- // F[map_e3]: 13:12 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h3) +- ) u_classc_ctrl_map_e3 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_ctrl_map_e3_we & regen_qs), +- .wd (classc_ctrl_map_e3_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_ctrl.map_e3.q ), +- +- // to register interface (read) +- .qs (classc_ctrl_map_e3_qs) +- ); +- +- +- // R[classc_clren]: V(False) +- +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h1) +- ) u_classc_clren ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (classc_clren_we), +- .wd (classc_clren_wd), +- +- // from internal hardware +- .de (hw2reg.classc_clren.de), +- .d (hw2reg.classc_clren.d ), +- +- // to internal hardware +- .qe (), +- .q (), +- +- // to register interface (read) +- .qs (classc_clren_qs) +- ); +- +- +- // R[classc_clr]: V(False) +- +- prim_subreg #( +- .DW (1), +- .SWACCESS("WO"), +- .RESVAL (1'h0) +- ) u_classc_clr ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_clr_we & classc_clren_qs), +- .wd (classc_clr_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (reg2hw.classc_clr.qe), +- .q (reg2hw.classc_clr.q ), +- +- .qs () +- ); +- +- +- // R[classc_accum_cnt]: V(True) +- +- prim_subreg_ext #( +- .DW (16) +- ) u_classc_accum_cnt ( +- .re (classc_accum_cnt_re), +- .we (1'b0), +- .wd ('0), +- .d (hw2reg.classc_accum_cnt.d), +- .qre (), +- .qe (), +- .q (), +- .qs (classc_accum_cnt_qs) +- ); +- +- +- // R[classc_accum_thresh]: V(False) +- +- prim_subreg #( +- .DW (16), +- .SWACCESS("RW"), +- .RESVAL (16'h0) +- ) u_classc_accum_thresh ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_accum_thresh_we & regen_qs), +- .wd (classc_accum_thresh_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_accum_thresh.q ), +- +- // to register interface (read) +- .qs (classc_accum_thresh_qs) +- ); +- +- +- // R[classc_timeout_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classc_timeout_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_timeout_cyc_we & regen_qs), +- .wd (classc_timeout_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_timeout_cyc.q ), +- +- // to register interface (read) +- .qs (classc_timeout_cyc_qs) +- ); +- +- +- // R[classc_phase0_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classc_phase0_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_phase0_cyc_we & regen_qs), +- .wd (classc_phase0_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_phase0_cyc.q ), +- +- // to register interface (read) +- .qs (classc_phase0_cyc_qs) +- ); +- +- +- // R[classc_phase1_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classc_phase1_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_phase1_cyc_we & regen_qs), +- .wd (classc_phase1_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_phase1_cyc.q ), +- +- // to register interface (read) +- .qs (classc_phase1_cyc_qs) +- ); +- +- +- // R[classc_phase2_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classc_phase2_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_phase2_cyc_we & regen_qs), +- .wd (classc_phase2_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_phase2_cyc.q ), +- +- // to register interface (read) +- .qs (classc_phase2_cyc_qs) +- ); +- +- +- // R[classc_phase3_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classc_phase3_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classc_phase3_cyc_we & regen_qs), +- .wd (classc_phase3_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classc_phase3_cyc.q ), +- +- // to register interface (read) +- .qs (classc_phase3_cyc_qs) +- ); +- +- +- // R[classc_esc_cnt]: V(True) +- +- prim_subreg_ext #( +- .DW (32) +- ) u_classc_esc_cnt ( +- .re (classc_esc_cnt_re), +- .we (1'b0), +- .wd ('0), +- .d (hw2reg.classc_esc_cnt.d), +- .qre (), +- .qe (), +- .q (), +- .qs (classc_esc_cnt_qs) +- ); +- +- +- // R[classc_state]: V(True) +- +- prim_subreg_ext #( +- .DW (3) +- ) u_classc_state ( +- .re (classc_state_re), +- .we (1'b0), +- .wd ('0), +- .d (hw2reg.classc_state.d), +- .qre (), +- .qe (), +- .q (), +- .qs (classc_state_qs) +- ); +- +- +- // R[classd_ctrl]: V(False) +- +- // F[en]: 0:0 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_classd_ctrl_en ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_ctrl_en_we & regen_qs), +- .wd (classd_ctrl_en_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_ctrl.en.q ), +- +- // to register interface (read) +- .qs (classd_ctrl_en_qs) +- ); +- +- +- // F[lock]: 1:1 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h0) +- ) u_classd_ctrl_lock ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_ctrl_lock_we & regen_qs), +- .wd (classd_ctrl_lock_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_ctrl.lock.q ), +- +- // to register interface (read) +- .qs (classd_ctrl_lock_qs) +- ); +- +- +- // F[en_e0]: 2:2 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classd_ctrl_en_e0 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_ctrl_en_e0_we & regen_qs), +- .wd (classd_ctrl_en_e0_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_ctrl.en_e0.q ), +- +- // to register interface (read) +- .qs (classd_ctrl_en_e0_qs) +- ); +- +- +- // F[en_e1]: 3:3 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classd_ctrl_en_e1 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_ctrl_en_e1_we & regen_qs), +- .wd (classd_ctrl_en_e1_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_ctrl.en_e1.q ), +- +- // to register interface (read) +- .qs (classd_ctrl_en_e1_qs) +- ); +- +- +- // F[en_e2]: 4:4 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classd_ctrl_en_e2 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_ctrl_en_e2_we & regen_qs), +- .wd (classd_ctrl_en_e2_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_ctrl.en_e2.q ), +- +- // to register interface (read) +- .qs (classd_ctrl_en_e2_qs) +- ); +- +- +- // F[en_e3]: 5:5 +- prim_subreg #( +- .DW (1), +- .SWACCESS("RW"), +- .RESVAL (1'h1) +- ) u_classd_ctrl_en_e3 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_ctrl_en_e3_we & regen_qs), +- .wd (classd_ctrl_en_e3_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_ctrl.en_e3.q ), +- +- // to register interface (read) +- .qs (classd_ctrl_en_e3_qs) +- ); +- +- +- // F[map_e0]: 7:6 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h0) +- ) u_classd_ctrl_map_e0 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_ctrl_map_e0_we & regen_qs), +- .wd (classd_ctrl_map_e0_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_ctrl.map_e0.q ), +- +- // to register interface (read) +- .qs (classd_ctrl_map_e0_qs) +- ); +- +- +- // F[map_e1]: 9:8 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h1) +- ) u_classd_ctrl_map_e1 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_ctrl_map_e1_we & regen_qs), +- .wd (classd_ctrl_map_e1_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_ctrl.map_e1.q ), +- +- // to register interface (read) +- .qs (classd_ctrl_map_e1_qs) +- ); +- +- +- // F[map_e2]: 11:10 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h2) +- ) u_classd_ctrl_map_e2 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_ctrl_map_e2_we & regen_qs), +- .wd (classd_ctrl_map_e2_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_ctrl.map_e2.q ), +- +- // to register interface (read) +- .qs (classd_ctrl_map_e2_qs) +- ); +- +- +- // F[map_e3]: 13:12 +- prim_subreg #( +- .DW (2), +- .SWACCESS("RW"), +- .RESVAL (2'h3) +- ) u_classd_ctrl_map_e3 ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_ctrl_map_e3_we & regen_qs), +- .wd (classd_ctrl_map_e3_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_ctrl.map_e3.q ), +- +- // to register interface (read) +- .qs (classd_ctrl_map_e3_qs) +- ); +- +- +- // R[classd_clren]: V(False) +- +- prim_subreg #( +- .DW (1), +- .SWACCESS("W1C"), +- .RESVAL (1'h1) +- ) u_classd_clren ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface +- .we (classd_clren_we), +- .wd (classd_clren_wd), +- +- // from internal hardware +- .de (hw2reg.classd_clren.de), +- .d (hw2reg.classd_clren.d ), +- +- // to internal hardware +- .qe (), +- .q (), +- +- // to register interface (read) +- .qs (classd_clren_qs) +- ); +- +- +- // R[classd_clr]: V(False) +- +- prim_subreg #( +- .DW (1), +- .SWACCESS("WO"), +- .RESVAL (1'h0) +- ) u_classd_clr ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_clr_we & classd_clren_qs), +- .wd (classd_clr_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (reg2hw.classd_clr.qe), +- .q (reg2hw.classd_clr.q ), +- +- .qs () +- ); +- +- +- // R[classd_accum_cnt]: V(True) +- +- prim_subreg_ext #( +- .DW (16) +- ) u_classd_accum_cnt ( +- .re (classd_accum_cnt_re), +- .we (1'b0), +- .wd ('0), +- .d (hw2reg.classd_accum_cnt.d), +- .qre (), +- .qe (), +- .q (), +- .qs (classd_accum_cnt_qs) +- ); +- +- +- // R[classd_accum_thresh]: V(False) +- +- prim_subreg #( +- .DW (16), +- .SWACCESS("RW"), +- .RESVAL (16'h0) +- ) u_classd_accum_thresh ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_accum_thresh_we & regen_qs), +- .wd (classd_accum_thresh_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_accum_thresh.q ), +- +- // to register interface (read) +- .qs (classd_accum_thresh_qs) +- ); +- +- +- // R[classd_timeout_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classd_timeout_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_timeout_cyc_we & regen_qs), +- .wd (classd_timeout_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_timeout_cyc.q ), +- +- // to register interface (read) +- .qs (classd_timeout_cyc_qs) +- ); +- +- +- // R[classd_phase0_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classd_phase0_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_phase0_cyc_we & regen_qs), +- .wd (classd_phase0_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_phase0_cyc.q ), +- +- // to register interface (read) +- .qs (classd_phase0_cyc_qs) +- ); +- +- +- // R[classd_phase1_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classd_phase1_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_phase1_cyc_we & regen_qs), +- .wd (classd_phase1_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_phase1_cyc.q ), +- +- // to register interface (read) +- .qs (classd_phase1_cyc_qs) +- ); +- +- +- // R[classd_phase2_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classd_phase2_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_phase2_cyc_we & regen_qs), +- .wd (classd_phase2_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_phase2_cyc.q ), +- +- // to register interface (read) +- .qs (classd_phase2_cyc_qs) +- ); +- +- +- // R[classd_phase3_cyc]: V(False) +- +- prim_subreg #( +- .DW (32), +- .SWACCESS("RW"), +- .RESVAL (32'h0) +- ) u_classd_phase3_cyc ( +- .clk_i (clk_i ), +- .rst_ni (rst_ni ), +- +- // from register interface (qualified with register enable) +- .we (classd_phase3_cyc_we & regen_qs), +- .wd (classd_phase3_cyc_wd), +- +- // from internal hardware +- .de (1'b0), +- .d ('0 ), +- +- // to internal hardware +- .qe (), +- .q (reg2hw.classd_phase3_cyc.q ), +- +- // to register interface (read) +- .qs (classd_phase3_cyc_qs) +- ); +- +- +- // R[classd_esc_cnt]: V(True) +- +- prim_subreg_ext #( +- .DW (32) +- ) u_classd_esc_cnt ( +- .re (classd_esc_cnt_re), +- .we (1'b0), +- .wd ('0), +- .d (hw2reg.classd_esc_cnt.d), +- .qre (), +- .qe (), +- .q (), +- .qs (classd_esc_cnt_qs) +- ); +- +- +- // R[classd_state]: V(True) +- +- prim_subreg_ext #( +- .DW (3) +- ) u_classd_state ( +- .re (classd_state_re), +- .we (1'b0), +- .wd ('0), +- .d (hw2reg.classd_state.d), +- .qre (), +- .qe (), +- .q (), +- .qs (classd_state_qs) +- ); +- +- +- +- + logic [58:0] addr_hit; + always_comb begin + addr_hit = '0; diff --git a/hw/top_earlgrey/ip/padctrl/rtl/autogen/padctrl_reg_top.sv b/hw/top_earlgrey/ip/padctrl/rtl/autogen/padctrl_reg_top.sv index 30f3ea44f..9a56d6721 100644 --- a/hw/top_earlgrey/ip/padctrl/rtl/autogen/padctrl_reg_top.sv diff --git a/uhdm-tests/opentitan/Makefile.in b/uhdm-tests/opentitan/Makefile.in index 64fd9d7c6..b60df4efe 100644 --- a/uhdm-tests/opentitan/Makefile.in +++ b/uhdm-tests/opentitan/Makefile.in @@ -38,7 +38,6 @@ prim_flop_2sync.sv \ prim_ram_1p.sv \ prim_lfsr.sv \ prim_intr_hw.sv \ -alert_handler_reg_top.sv \ ibex_icache.sv \ prim_dom_and_2share.sv \ prim_arbiter_fixed.sv \ @@ -69,7 +68,6 @@ tlul_err_resp.sv \ tlul_socket_1n.sv \ sram2tlul.sv \ debug_rom_one_scratch.sv \ -alert_handler_reg_wrap.sv \ alert_handler.sv \ jtag_mux.sv \ prim_secded_39_32_dec.sv \ @@ -123,6 +121,7 @@ rv_timer_reg_pkg.sv \ rv_plic_reg_pkg.sv \ hmac_reg_pkg.sv \ padctrl_reg_pkg.sv \ +alert_handler_reg_pkg.sv \ ibex_compressed_decoder.sv \ ibex_alu.sv \ ibex_controller.sv \ @@ -319,6 +318,8 @@ flash_mp.sv \ padctrl_reg_top.sv \ padctrl.sv \ padring.sv \ +alert_handler_reg_top.sv \ +alert_handler_reg_wrap.sv \ UHDM_FILES_FULL = \ $(shell \ @@ -441,6 +442,7 @@ ${UHDM_file}: ${SV2V_FILE} -top flash_ctrl \ -top padctrl \ -top padring \ + -top alert_handler_reg_wrap \ $(EARLGRAY_INCLUDE) \ $(UHDM_FILES_FULL) \ $(CUSTOM_FILES_UHDM) && \