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Merge python3-rc2 branch into master (#656)

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BrentHoltsclaw committed Aug 15, 2019
1 parent ee40421 commit 2efeda434594041371cd0337f95737924f4e1db2
Showing with 2,708 additions and 2,676 deletions.
  1. +14 −6 .travis.yml
  2. +1 −1 chipsec/VERSION
  3. +32 −32 chipsec/chipset.py
  4. +6 −0 chipsec/defines.py
  5. +7 −5 chipsec/file.py
  6. +45 −43 chipsec/hal/acpi.py
  7. +499 −499 chipsec/hal/acpi_tables.py
  8. +13 −13 chipsec/hal/cmos.py
  9. +17 −17 chipsec/hal/cpu.py
  10. +2 −2 chipsec/hal/cpuid.py
  11. +4 −4 chipsec/hal/ec.py
  12. +20 −18 chipsec/hal/igd.py
  13. +14 −12 chipsec/hal/interrupts.py
  14. +13 −13 chipsec/hal/io.py
  15. +15 −15 chipsec/hal/iobar.py
  16. +27 −27 chipsec/hal/iommu.py
  17. +29 −28 chipsec/hal/mmio.py
  18. +13 −11 chipsec/hal/msgbus.py
  19. +16 −24 chipsec/hal/msr.py
  20. +62 −53 chipsec/hal/paging.py
  21. +48 −48 chipsec/hal/pci.py
  22. +13 −13 chipsec/hal/physmem.py
  23. +11 −11 chipsec/hal/smbus.py
  24. +52 −52 chipsec/hal/spd.py
  25. +60 −59 chipsec/hal/spi.py
  26. +40 −39 chipsec/hal/spi_descriptor.py
  27. +8 −7 chipsec/hal/spi_uefi.py
  28. +42 −42 chipsec/hal/tpm.py
  29. +17 −13 chipsec/hal/tpm_eventlog.py
  30. +21 −20 chipsec/hal/ucode.py
  31. +22 −15 chipsec/hal/uefi.py
  32. +10 −9 chipsec/hal/uefi_common.py
  33. +94 −80 chipsec/hal/uefi_platform.py
  34. +15 −15 chipsec/hal/uefi_search.py
  35. +12 −12 chipsec/hal/virtmem.py
  36. +5 −5 chipsec/hal/vmm.py
  37. +1 −0 chipsec/helper/basehelper.py
  38. +13 −12 chipsec/helper/dal/dalhelper.py
  39. +3 −1 chipsec/helper/efi/__init__.py
  40. +8 −7 chipsec/helper/efi/efihelper.py
  41. +4 −3 chipsec/helper/file/__init__.py
  42. +7 −19 chipsec/helper/file/{helper.py → filehelper.py}
  43. +0 −3 chipsec/helper/helpers.py
  44. +4 −2 chipsec/helper/linux/__init__.py
  45. +62 −49 chipsec/helper/linux/{helper.py → linuxhelper.py}
  46. +13 −11 chipsec/helper/oshelper.py
  47. +4 −1 chipsec/helper/osx/__init__.py
  48. +8 −7 chipsec/helper/osx/{helper.py → osxhelper.py}
  49. +3 −2 chipsec/helper/rwe/__init__.py
  50. +96 −94 chipsec/helper/rwe/rwehelper.py
  51. +3 −2 chipsec/helper/win/__init__.py
  52. +36 −31 chipsec/helper/win/win32helper.py
  53. +32 −4 chipsec/logger.py
  54. +7 −7 chipsec/module.py
  55. +8 −14 chipsec/modules/common/bios_kbrd_buffer.py
  56. +2 −2 chipsec/modules/common/bios_smi.py
  57. +3 −3 chipsec/modules/common/bios_ts.py
  58. +1 −1 chipsec/modules/common/bios_wp.py
  59. +8 −8 chipsec/modules/common/cpu/spectre_v2.py
  60. +1 −1 chipsec/modules/common/ia32cfg.py
  61. +15 −15 chipsec/modules/common/secureboot/variables.py
  62. +37 −37 chipsec/modules/common/sgx_check.py
  63. +7 −7 chipsec/modules/common/smrr.py
  64. +1 −1 chipsec/modules/common/spi_desc.py
  65. +12 −12 chipsec/modules/common/uefi/access_uefispec.py
  66. +6 −6 chipsec/modules/common/uefi/s3bootscript.py
  67. +3 −3 chipsec/modules/memconfig.py
  68. +11 −11 chipsec/modules/remap.py
  69. +2 −2 chipsec/modules/smm_dma.py
  70. +5 −5 chipsec/modules/tools/cpu/sinkhole.py
  71. +23 −22 chipsec/modules/tools/secureboot/te.py
  72. +16 −16 chipsec/modules/tools/smm/rogue_mmio_bar.py
  73. +56 −56 chipsec/modules/tools/smm/smm_ptr.py
  74. +6 −6 chipsec/modules/tools/uefi/blacklist.py
  75. +31 −31 chipsec/modules/tools/uefi/s3script_modify.py
  76. +6 −6 chipsec/modules/tools/uefi/uefivar_fuzz.py
  77. +12 −12 chipsec/modules/tools/uefi/whitelist.py
  78. +27 −27 chipsec/modules/tools/vmm/common.py
  79. +12 −12 chipsec/modules/tools/vmm/cpuid_fuzz.py
  80. +1 −1 chipsec/modules/tools/vmm/hv/define.py
  81. +61 −61 chipsec/modules/tools/vmm/hv/hypercall.py
  82. +17 −17 chipsec/modules/tools/vmm/hv/hypercallfuzz.py
  83. +19 −19 chipsec/modules/tools/vmm/hv/synth_dev.py
  84. +12 −12 chipsec/modules/tools/vmm/hv/synth_kbd.py
  85. +47 −47 chipsec/modules/tools/vmm/hv/vmbus.py
  86. +3 −3 chipsec/modules/tools/vmm/hv/vmbusfuzz.py
  87. +24 −24 chipsec/modules/tools/vmm/hypercallfuzz.py
  88. +10 −10 chipsec/modules/tools/vmm/iofuzz.py
  89. +6 −6 chipsec/modules/tools/vmm/msr_fuzz.py
  90. +10 −10 chipsec/modules/tools/vmm/pcie_fuzz.py
  91. +4 −4 chipsec/modules/tools/vmm/pcie_overlap_fuzz.py
  92. +1 −1 chipsec/modules/tools/vmm/vbox/vbox_crash_apicbase.py
  93. +4 −4 chipsec/modules/tools/vmm/xen/define.py
  94. +24 −24 chipsec/modules/tools/vmm/xen/hypercall.py
  95. +5 −5 chipsec/modules/tools/vmm/xen/hypercallfuzz.py
  96. +4 −3 chipsec/result_deltas.py
  97. +1 −1 chipsec/testcase.py
  98. +5 −6 chipsec/utilcmd/acpi_cmd.py
  99. +1 −1 chipsec/utilcmd/chipset_cmd.py
  100. +2 −2 chipsec/utilcmd/cmos_cmd.py
  101. +30 −30 chipsec/utilcmd/cpu_cmd.py
  102. +9 −9 chipsec/utilcmd/decode_cmd.py
  103. +2 −2 chipsec/utilcmd/desc_cmd.py
  104. +11 −11 chipsec/utilcmd/ec_cmd.py
  105. +14 −12 chipsec/utilcmd/igd_cmd.py
  106. +19 −19 chipsec/utilcmd/interrupts_cmd.py
  107. +8 −8 chipsec/utilcmd/io_cmd.py
  108. +8 −8 chipsec/utilcmd/iommu_cmd.py
  109. +46 −72 chipsec/utilcmd/mem_cmd.py
  110. +7 −10 chipsec/utilcmd/mmcfg_cmd.py
  111. +10 −9 chipsec/utilcmd/mmio_cmd.py
  112. +12 −12 chipsec/utilcmd/msgbus_cmd.py
  113. +5 −5 chipsec/utilcmd/msr_cmd.py
  114. +17 −17 chipsec/utilcmd/pci_cmd.py
  115. +19 −19 chipsec/utilcmd/reg_cmd.py
  116. +9 −9 chipsec/utilcmd/smbus_cmd.py
  117. +9 −9 chipsec/utilcmd/spd_cmd.py
  118. +15 −15 chipsec/utilcmd/spi_cmd.py
  119. +4 −4 chipsec/utilcmd/spidesc_cmd.py
  120. +5 −5 chipsec/utilcmd/tpm_cmd.py
  121. +11 −11 chipsec/utilcmd/ucode_cmd.py
  122. +44 −44 chipsec/utilcmd/uefi_cmd.py
  123. +32 −85 chipsec/utilcmd/vmem_cmd.py
  124. +24 −24 chipsec/utilcmd/vmm_cmd.py
  125. +32 −26 chipsec_main.py
  126. +11 −11 chipsec_tools/edk2/PythonEFI/build/compilePythonEDK2.py
  127. +17 −14 chipsec_util.py
  128. +5 −5 scripts/build_exe_win7-amd64.py
  129. +5 −5 scripts/build_exe_win7-x86.py
  130. +28 −25 tests/software/mock_helper.py
  131. +32 −32 tests/software/test_acpi.py
  132. +1 −1 tests/software/test_desc.py
  133. +1 −1 tests/software/test_spi.py
  134. +5 −5 tests/software/test_tpm_eventlog.py
  135. +6 −7 tests/software/util.py
@@ -1,6 +1,4 @@
language: python
python:
- 2.7
sudo: required
install:
- sudo apt-get -qq update
@@ -9,12 +7,22 @@ install:

matrix:
include:
- name: "Trusty"
- name: "Trusty - python2"
os: linux
dist: trusty
- name: "Xenial"
python: 2.7
- name: "Xenial - python2"
os: linux
dist: xenial
dist: xenial
python: 2.7
- name: "Trusty - python3"
os: linux
dist: trusty
python: 3.5
- name: "Xenial - python3"
os: linux
dist: xenial
python: 3.5
- name: "MacOS Build"
os : osx
language: generic
@@ -23,4 +31,4 @@ matrix:
- brew install nasm

script:
- python setup.py test
- python setup.py test
@@ -1 +1 @@
1.3.8
1.3.8
@@ -338,7 +338,7 @@ def print_supported_chipsets():
logger().log( "-------------------------------------------------------------------------------------" )
for _code in sorted(codes_dict):
for _did in codes_dict[_code]:
logger().log( " %-#6x | %-14s | %-6s | %-40s" % (_did, Chipset_Dictionary[_did]['name'], _code.lower(), Chipset_Dictionary[_did]['longname']) )
logger().log( " {:-#6x} | {:14} | {:6} | {:40}".format(_did, Chipset_Dictionary[_did]['name'], _code.lower(), Chipset_Dictionary[_did]['longname']) )


def f_xml(self, x):
@@ -436,15 +436,15 @@ def init( self, platform_code, req_pch_code, start_driver, driver_exists=None, t

_unknown_platform = False
self.helper.start(start_driver, driver_exists, to_file, from_file)
logger().log( '[CHIPSEC] API mode: %s' % ('using OS native API (not using CHIPSEC kernel module)' if self.use_native_api() else 'using CHIPSEC kernel module API') )
logger().log( '[CHIPSEC] API mode: {}'.format('using OS native API (not using CHIPSEC kernel module)' if self.use_native_api() else 'using CHIPSEC kernel module API') )

self.vid, self.did, self.rid, self.pch_vid, self.pch_did, self.pch_rid = self.detect_platform()
if platform_code is None:
if VID_INTEL != self.vid:
_unknown_platform = True
else:
self.vid = VID_INTEL
if Chipset_Code.has_key( platform_code ):
if platform_code in Chipset_Code:
self.did = Chipset_Code[ platform_code ]
self.rid = 0x00
else:
@@ -453,7 +453,7 @@ def init( self, platform_code, req_pch_code, start_driver, driver_exists=None, t
self.did = 0xFFFF
self.rid = 0xFF

if Chipset_Dictionary.has_key( self.did ):
if self.did in Chipset_Dictionary:
data_dict = Chipset_Dictionary[ self.did ]
self.code = data_dict['code'].lower()
self.longname = data_dict['longname']
@@ -464,15 +464,15 @@ def init( self, platform_code, req_pch_code, start_driver, driver_exists=None, t

if req_pch_code is not None:
self.pch_vid = VID_INTEL
if pch_codes.has_key(req_pch_code):
if req_pch_code in pch_codes:
self.pch_did = pch_codes[req_pch_code]
self.pch_rid = 0x00
else:
self.pch_vid = 0xFFFF
self.pch_did = 0xFFFF
self.pch_rid = 0xFF

if self.pch_vid == VID_INTEL and pch_dictionary.has_key(self.pch_did):
if self.pch_vid == VID_INTEL and self.pch_did in pch_dictionary:
data_dict = pch_dictionary[self.pch_did]
self.pch_code = data_dict['code'].lower()
self.pch_longname = data_dict['longname']
@@ -484,7 +484,7 @@ def init( self, platform_code, req_pch_code, start_driver, driver_exists=None, t
if _unknown_platform and start_driver:
msg = 'Unsupported Platform: VID = 0x{:04X}, DID = 0x{:04X}, RID = 0x{:02X}'.format(self.vid,self.did,self.rid)
logger().error( msg )
raise UnknownChipsetError, msg
raise UnknownChipsetError (msg)


def destroy( self, start_driver ):
@@ -583,14 +583,14 @@ def init_xml_configuration( self ):
def init_cfg_xml(self, fxml, code, pch_code):
import xml.etree.ElementTree as ET
if not os.path.exists( fxml ): return
if logger().DEBUG: logger().log( "[*] looking for platform config in '%s'.." % fxml )
if logger().DEBUG: logger().log( "[*] looking for platform config in '{}'..".format(fxml) )
tree = ET.parse( fxml )
root = tree.getroot()
for _cfg in root.iter('configuration'):
if 'platform' not in _cfg.attrib:
if logger().DEBUG: logger().log( "[*] loading common platform config from '%s'.." % fxml )
if logger().DEBUG: logger().log( "[*] loading common platform config from '{}'..".format(fxml) )
elif code == _cfg.attrib['platform'].lower():
if logger().DEBUG: logger().log( "[*] loading '%s' platform config from '%s'.." % (code,fxml) )
if logger().DEBUG: logger().log( "[*] loading '{}' platform config from '{}'..".format(code,fxml) )
elif pch_code == _cfg.attrib['platform'].lower():
if logger().DEBUG: logger().log("[*] loading '{}' PCH config from '{}'..".format(pch_code,fxml))
else: continue
@@ -606,7 +606,7 @@ def init_cfg_xml(self, fxml, code, pch_code):
self.Cfg.CONFIG_PCI.pop(_name, None)
continue
self.Cfg.CONFIG_PCI[ _name ] = _device.attrib
if logger().DEBUG: logger().log( " + %-16s: %s" % (_name, _device.attrib) )
if logger().DEBUG: logger().log( " + {:16}: {}".format(_name, _device.attrib) )
if logger().DEBUG: logger().log( "[*] loading MMIO BARs.." )
for _mmio in _cfg.iter('mmio'):
for _bar in _mmio.iter('bar'):
@@ -618,7 +618,7 @@ def init_cfg_xml(self, fxml, code, pch_code):
self.Cfg.MMIO_BARS.pop(_name, None)
continue
self.Cfg.MMIO_BARS[ _name ] = _bar.attrib
if logger().DEBUG: logger().log( " + %-16s: %s" % (_name, _bar.attrib) )
if logger().DEBUG: logger().log( " + {:16}: {}".format(_name, _bar.attrib) )
if logger().DEBUG: logger().log( "[*] loading I/O BARs.." )
for _io in _cfg.iter('io'):
for _bar in _io.iter('bar'):
@@ -630,7 +630,7 @@ def init_cfg_xml(self, fxml, code, pch_code):
self.Cfg.IO_BARS.pop(_name, None)
continue
self.Cfg.IO_BARS[ _name ] = _bar.attrib
if logger().DEBUG: logger().log( " + %-16s: %s" % (_name, _bar.attrib) )
if logger().DEBUG: logger().log( " + {:16}: {}".format(_name, _bar.attrib) )
if logger().DEBUG: logger().log( "[*] loading memory ranges.." )
for _memory in _cfg.iter('memory'):
for _range in _memory.iter('range'):
@@ -642,7 +642,7 @@ def init_cfg_xml(self, fxml, code, pch_code):
self.Cfg.MEMORY_RANGES.pop(_name, None)
continue
self.Cfg.MEMORY_RANGES[ _name ] = _range.attrib
if logger().DEBUG: logger().log( " + %-16s: %s" % (_name, _range.attrib) )
if logger().DEBUG: logger().log( " + {:16}: {}".format(_name, _range.attrib) )
if logger().DEBUG: logger().log( "[*] loading configuration registers.." )
for _registers in _cfg.iter('registers'):
for _register in _registers.iter('register'):
@@ -664,7 +664,7 @@ def init_cfg_xml(self, fxml, code, pch_code):
reg_fields[ _field_name ] = _field.attrib
_register.attrib['FIELDS'] = reg_fields
self.Cfg.REGISTERS[ _name ] = _register.attrib
if logger().DEBUG: logger().log( " + %-16s: %s" % (_name, _register.attrib) )
if logger().DEBUG: logger().log( " + {:16}: {}".format(_name, _register.attrib) )
if logger().DEBUG: logger().log( "[*] loading controls.." )
for _controls in _cfg.iter('controls'):
for _control in _controls.iter('control'):
@@ -676,7 +676,7 @@ def init_cfg_xml(self, fxml, code, pch_code):
self.Cfg.CONTROLS.pop(_name, None)
continue
self.Cfg.CONTROLS[ _name ] = _control.attrib
if logger().DEBUG: logger().log( " + %-16s: %s" % (_name, _control.attrib) )
if logger().DEBUG: logger().log( " + {:16}: {}".format(_name, _control.attrib) )

def init_cfg_bus( self ):
if logger().DEBUG: logger().log( '[*] loading device buses..' )
@@ -703,10 +703,10 @@ def init_cfg(self):
try:
module_path = 'chipsec.cfg.' + self.code
module = importlib.import_module( module_path )
logger().log_good( "imported platform specific configuration: chipsec.cfg.%s" % self.code )
logger().log_good( "imported platform specific configuration: chipsec.cfg.{}".format(self.code) )
self.Cfg = getattr( module, self.code )()
except ImportError, msg:
if logger().DEBUG: logger().log( "[*] Couldn't import chipsec.cfg.%s\n%s" % ( self.code, str(msg) ) )
except ImportError as msg:
if logger().DEBUG: logger().log( "[*] Couldn't import chipsec.cfg.{}\n{}".format( self.code, str(msg) ) )

#
# Initialize platform configuration from XML files
@@ -727,7 +727,7 @@ def init_cfg(self):

def get_device_BDF( self, device_name ):
device = self.Cfg.CONFIG_PCI[ device_name ]
if device is None or device == {}: raise DeviceNotFoundError, ('DeviceNotFound: %s' % device_name)
if device is None or device == {}: raise DeviceNotFoundError ('DeviceNotFound: {}'.format(device_name))
b = int(device['bus'],16)
d = int(device['dev'],16)
f = int(device['fun'],16)
@@ -776,8 +776,8 @@ def is_register_defined(self, reg_name):
try:
return (self.Cfg.REGISTERS[reg_name] is not None)
except KeyError:
#if logger().DEBUG: logger().error( "'%s' register definition not found in XML config" % reg_name)
#raise RegisterNotFoundError, ('RegisterNotFound: %s' % reg_name)
#if logger().DEBUG: logger().error( "'{}' register definition not found in XML config".format(reg_name))
#raise RegisterNotFoundError, ('RegisterNotFound: {}'.format(reg_name))
return False

def get_register_def(self, reg_name, bus_index=0):
@@ -929,7 +929,7 @@ def read_register_field( self, reg_name, field_name, preserve_field_position=Fal
def write_register_field( self, reg_name, field_name, field_value, preserve_field_position=False, cpu_thread=0 ):
reg_value = self.read_register(reg_name, cpu_thread)
reg_value_new = self.set_register_field(reg_name, reg_value, field_name, field_value, preserve_field_position)
#logger().log("set register %s (0x%x) field %s = 0x%x ==> 0x%x" % (reg_name, reg_value, field_name, field_value, reg_value_new))
#logger().log("set register {} (0x{:x}) field {} = 0x{:x} ==> 0x{:x}".format(reg_name, reg_value, field_name, field_value, reg_value_new))
return self.write_register(reg_name, reg_value_new, cpu_thread)

def register_has_field( self, reg_name, field_name ):
@@ -953,7 +953,7 @@ def _register_fields_str(self, reg_def, reg_val):
field_mask = (field_mask << 1) | 1
field_value = (reg_val >> field_bit) & field_mask
field_desc = (' << ' + field_attrs['desc'] + ' ') if (field_attrs['desc'] != '') else ''
reg_fields_str += (" [%02d] %-16s = %X%s\n" % (field_bit,f[0],field_value,field_desc))
reg_fields_str += (" [{:02d}] {:16} = {:X}{}\n".format(field_bit,f[0],field_value,field_desc))

if '' != reg_fields_str: reg_fields_str = reg_fields_str[:-1]
return reg_fields_str
@@ -962,26 +962,26 @@ def print_register(self, reg_name, reg_val, bus_index=0):
reg = self.get_register_def( reg_name, bus_index )
rtype = reg['type']
reg_str = ''
reg_val_str = ("0x%0" + ("%dX" % (int(reg['size'],16)*2))) % reg_val
reg_val_str = "0x{:{width}X}".format(reg_val,width=(int(reg['size'],16)*2))
if RegisterType.PCICFG == rtype or RegisterType.MMCFG == rtype:
b = int(reg['bus'],16)
d = int(reg['dev'],16)
f = int(reg['fun'],16)
o = int(reg['offset'],16)
mmcfg_off_str = ''
if RegisterType.MMCFG == rtype:
mmcfg_off_str += ", MMCFG + 0x%X" % ((b*32*8 + d*8 + f) * 0x1000 + o)
reg_str = "[*] %s = %s << %s (b:d.f %02d:%02d.%d + 0x%X%s)" % (reg_name, reg_val_str, reg['desc'], b, d, f, o, mmcfg_off_str)
mmcfg_off_str += ", MMCFG + 0x{:X}".format((b*32*8 + d*8 + f) * 0x1000 + o)
reg_str = "[*] {} = {} << {} (b:d.f {:02d}:{:02d}.{:d} + 0x{:X}{})".format(reg_name, reg_val_str, reg['desc'], b, d, f, o, mmcfg_off_str)
elif RegisterType.MMIO == rtype:
reg_str = "[*] %s = %s << %s (%s + 0x%X)" % (reg_name, reg_val_str, reg['desc'], reg['bar'], int(reg['offset'],16))
reg_str = "[*] {} = {} << {} ({} + 0x{:X})".format(reg_name, reg_val_str, reg['desc'], reg['bar'], int(reg['offset'],16))
elif RegisterType.MSR == rtype:
reg_str = "[*] %s = %s << %s (MSR 0x%X)" % (reg_name, reg_val_str, reg['desc'], int(reg['msr'],16))
reg_str = "[*] {} = {} << {} (MSR 0x{:X})".format(reg_name, reg_val_str, reg['desc'], int(reg['msr'],16))
elif RegisterType.PORTIO == rtype:
reg_str = "[*] %s = %s << %s (I/O port 0x%X)" % (reg_name, reg_val_str, reg['desc'], int(reg['port'],16))
reg_str = "[*] {} = {} << {} (I/O port 0x{:X})".format(reg_name, reg_val_str, reg['desc'], int(reg['port'],16))
elif RegisterType.IOBAR == rtype:
reg_str = "[*] %s = %s << %s (I/O %s + 0x%X)" % (reg_name, reg_val_str, reg['desc'], reg['bar'], int(reg['offset'],16))
reg_str = "[*] {} = {} << {} (I/O {} + 0x{:X})".format(reg_name, reg_val_str, reg['desc'], reg['bar'], int(reg['offset'],16))
elif RegisterType.MSGBUS == rtype or RegisterType.MM_MSGBUS == rtype:
reg_str = "[*] %s = %s << %s (msgbus port 0x%X, off 0x%X)" % (reg_name, reg_val_str, reg['desc'], int(reg['port'],16), int(reg['offset'],16))
reg_str = "[*] {} = {} << {} (msgbus port 0x{:X}, off 0x{:X})".format(reg_name, reg_val_str, reg['desc'], int(reg['port'],16), int(reg['offset'],16))

reg_str += self._register_fields_str(reg, reg_val)
logger().log( reg_str )
@@ -166,6 +166,12 @@ def DQ(val):
8: 'Q'
}

def bytestostring(mbytes):
if type(mbytes) == type(bytes()):
return mbytes.decode("latin_1")
else:
return mbytes

def pack1(value, size):
"""Shortcut to pack a single value into a string based on its size."""
return struct.pack(SIZE2FORMAT[size], value)
@@ -53,7 +53,7 @@ def read_file( filename, size=0 ):
try:
f = open(filename, 'rb')
except:
logger().error( "Unable to open file '%.256s' for read access" % filename )
logger().error( "Unable to open file '{:.256}' for read access".format(filename) )
return 0

if size:
@@ -62,23 +62,25 @@ def read_file( filename, size=0 ):
_file = f.read()
f.close()

if logger().DEBUG: logger().log( "[file] read %d bytes from '%.256s'" % ( len(_file), filename ) )
if logger().DEBUG: logger().log( "[file] read {:d} bytes from '{:256}'".format( len(_file), filename ) )
return _file

def write_file( filename, buffer, append=False ):
#with open( filename, 'wb' ) as f:
# f.write( buffer )
#f.closed
perm = 'ab' if append else 'wb'
perm = 'a' if append else 'w'
if isinstance(buffer,bytes) or isinstance(buffer,bytearray):
perm += 'b'
try:
f = open(filename, perm)
except:
logger().error( "Unable to open file '%.256s' for write access" % filename )
logger().error( "Unable to open file '{:.256}' for write access".format(filename) )
return 0
f.write( buffer )
f.close()

if logger().DEBUG: logger().log( "[file] wrote %d bytes to '%.256s'" % ( len(buffer), filename ) )
if logger().DEBUG: logger().log( "[file] wrote {:d} bytes to '{:.256}'".format( len(buffer), filename ) )
return True


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