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Multi-objective Evolutionary Algorithm-Based Circuit Optimizer (Cmizer)

The phenomenon of doubling the number of transistors in Integrated Circuits (ICs) every 18 months, and the increase of the required circuit performance in accordance with the Moores law have created immense challenges for the electronic industries [30]. Optimization of circuit parameters is one of the key issues in circuit design, as frequent changes of circuit parameters to optimize the circuit performance and minimize the IC size are necessary to meet the demands and requirements of the global market in faster and smaller electronic products.


This project develops an intelligent Circuit optimizer, i.e., Cmizer, to provide decision support for electronic engineers to design circuits with a faster and easier manner, hence contributing towards the productivity of the electronic industries. Developed under the partnership between Universiti Malaysia Perlis (UniMAP) [40] and Myreka Sdn Bhd (Myreka) [25], and in collaboration with University of Science Malaysia (USM) [41] and Deakin University (Deakin) [10], the Cmizer software tool is targeted to optimize circuit design parameters based on the required circuit performance. It is used in conjunction with any open source circuit simulators, which can produce a netlist, in order to save the cost of circuit design. A Graphical User Interface is designed to allow the users to optimize circuit designs with plug-and-play Multi-Objective Evolutionary Algorithms (MOEAs) in a user-friendly manner. The overall validation results show that Cmizer is capable of saving time and cost required for electronic engineers to tackle circuit design tasks in the electronic industries.

Development Goals of Cmizer

Motivated by the market demand for rapid circuit products, and the competitiveness faced by the Small Medium Enterprises (SMEs) in the electronic industries, this project aims to develop a robust and user-friendly circuit optimizer that is flexible and capable of working in tandem with currently available free circuit simulators. Cmizer enables circuit designers to optimize circuit parameters and ensure the resulting circuit satisfies the design specifications in an easy and semi-automatic manner. This project has received a two-year financial assistance, i.e. Knowledge Transfer Program (KTP) Grant, from the Ministry of Higher Education (MoHE) Malaysia in 2012. Established under the partnership between Universiti Malaysia Perlis (UniMAP) and Myreka Sdn Bhd (Myreka), and in collaboration with University of Science Malaysia (USM) and Deakin University (Deakin), Cmizer is a step forward to assist the local electronic industries in increasing their competitiveness and meeting the challenges in the global market.

The current release of Cmizer , i.e. ver 2.0.x.x, works in tandem with LTSpice [21] (or any other simulators that produce a netlist), which is a free circuit simulation tool in order to reduce the cost needed for purchasing expensive licenses of commercial simulation software packages. Currently, work is in progress to produce the next release of Cmizer, i.e. ver 2.1.x.x, that will support another open source circuit simulator, i.e., NGSpice [12]. Indeed, circuit simulators such as Mentor-Graphic [24], Cadence [3], and Agilent Advanced Design System [39] (ADS) are too expensive for local SMEs. Besides that, not many commercial circuit simulators (let alone free circuit simulators) have built-in optimizers. Among the simulators, ADS is one of the circuit simulation tools that has a number of built-in optimizers, which include Gradient, Random Minimax, Gradient Minimax, Quasi-Newton, Least Path, Minimax, Random Max, Hybrid, Discrete, Genetic, and Simulated Annealing. But, the software cost is high, i.e. estimated about USD 9,000.

Conventionally, circuit parameter optimization is carried out based on the electronic engineers’ experiences, and is often conducted with a trial-and-error manner. The time required for circuit parameter optimization is subject to the complexity of the circuit, the specifications required, the constraints of the circuit parameters, and the number of parameters that need to be optimized. In the business world, time is of essence; therefore, having a circuit optimizer which could help the electronic engineers in optimizing their circuit design in a more convenient and straightforward way with accurate results is vital, especially for inexperienced electronic engineers.

Marketability and Plans of Cmizer

With the flexibility of the GUI of Cmizer, the user is allowed to modify the parameters, constraints and objective of the circuit design. This tool is capable of assisting electronic engineers in SMEs as well as educational and research institutions in circuit design tasks. In business, Cmizer contributes significantly towards time and cost savings in complex circuit design tasks. In academic institutions, it can be used to promote education and research on circuit design.

To validate the effectiveness of Cmizer, a real-world evaluation study had been conducted. A total of 3 practicing engineers from an SME involved in circuit design were invited to design a circuit that should meet certain specifications (e.g. gain and phase margins) based on their experience without assistance of any circuit optimization tools. During the 3-hour evaluation session, the engineers were given a circuit design in LTspice (that comes with no built-in optimizers), and were asked to tune the circuit parameters based on their experience, or knowledge from books. Two engineers spent more than 2 hours to meet the circuit specifications, while one engineer was not able to do so within the maximum 3-hour time frame. As compared with the use of Cmizer, the required specifications were able to be fulfilled within 15-20 minutes. As a result, it is evidenced that Cmizer contributes significantly towards saving of engineering time in circuit design tasks, which is equivalent to the value of profit return to the company.

In terms of the marketability plan, we encourage researchers and practitioners from all over the world to contribute newly developed optimization algorithms into Cmizer so that it becomes more flexible, practical, and robust from time to time. All contributed personnels can be provided with loyalty through the amount of charges gained from the number of downloads in the web. In the real world, there are a lot of engineering problems which involve parameter optimizations such as chemical process, instrumental design, manufacturing planning, etc. As the MOEA optimization techniques are generic in nature (and not just tailored to circuit parameter optimization), Cmizer can be further developed to work with other types of engineering problems that required optimization so as to extend the usability and marketability of Cmizer.

Besides LTSpice/NGSpice, we are currently developing the software for plug-and-play features in other free simulators. The aim is to increase the robustness of the MOEA optimization techniques from time to time so as to increase the flexibility to meet the requirements of various applications. As an example, a case study on chemical process optimization has been conducted and exhibited in the Invention and New Product Exposition (INPEX 2012) at Pittsburgh, USA as well as in the Cyber International Genius Inventor Fair (CIGIF 2012) at South Korea.


The software distribution is based on GNU General Public License, version 3 (GPL-3.0), see more details at URL

Cmizer Video Clip

Refer to Section [ here]

Personnel and Work Assignment of Cmizer

There are five members in our Cmizer team as follows.

  • Mr. Choo Jun TAN, the team lead: student of USM;
  • Mr. Wei Jer LIM, the team member: student of UniMAP;
  • Mr. Kian Meng TEY, the industry mentor: circuit design expert of Myreka;
  • Dr. Siew Chin NEOH, the academic mentor: lecturer of UniMAP; and
  • Professor Dr. Chee Peng LIM, the academic mentor: lecturer of USM/Deakin.

Cmizer Team

Mr Lim, Dr Neoh, Mr Tan, Mr Tey, and Professor Lim (from left to right)

Professor Lim and Dr Neoh are the coordinator cum mentor between academic and industrial organisations. Both of them also act as researchers in contributing state-of-the-art knowledge pertaining to MOEA techniques in this project. Mr Tey is the contributor industrial partner for the development of Cmizer. Together with Myreka staff, he provides useful technical and knowledge support from industrial perspective for the development of Cmizer.

The main development tasks of Cmizer are carried out by Mr Tan and Mr Lim. Mr Tan resumes the key role as the technical developer and system analyst for the Software Development Life Cycle (SDLC). Circuit design optimization is one of his current research interests, especially in MOEA techniques and their application to undertaking real-world MOPs. Mr Lim contributes towards the development tasks of SDLC for various operating systems using Java programming language for circuit design and analysis tasks using circuit simulators.


Bronze Medal for CIGIF 2012 - The 3rd Cyber International Genius Inventor Fair 2012 in South Korea


Obtain the selected per-built binary from here. The details of each release are as follows.

  • Cmizer new2 2013-10-31: version 2.x.5.7 ** Release for OSS competition (the Revision 21 tagged in [ SVN]) ** Enhanced the GUI presentation with 3D Scatter chart (rotating 360 degree with triple left-clicks) for showing optimized objectives. This release requires [ JZY3D] platform dependent library from [ here] [ (local)]. ** Bug fixed for inheriting wrong value for Passband Ripple (lower and upper ranges) ** The default checkout source code from SVN (watch [ demo] with [ VLC Player]) is running on NGSpice with sample circuit [ '''negblpf''']. This release has been tested on Linux 64 bit box (as shown in demo). ** image: cmizer. ** In this release, the optimized solutions from target MOEA is presented using a 3D scatter chart. All yellow points are solutions that satisfy the constraints. Those black dots are solutions that do not satisfy the constraints. The blue, red, and green are best 3 solutions with respect to the given objectives, i.e. Voltage Gain, Cutoff Frequency, and Passband Ripple.

  • 2013-10-05: version 2.x.4.6 ** Release for OSS competition (the Revision 8 tagged in [ SVN]) ** The default checkout source code from SVN (watch [ demo] with [ VLC Player]) is running on NGSpice with sample circuit [ '''negblpf'''].

  • 2013-08-10: version 2.x.3.6 ** Recorded duration time for simulator and overall ** Recorded the matched position (against the given objectives' range) for non-dominated solutions ** Critical bug fixed for satisfying the objective range (in file )

  • 2013-05-29: version 2.x.2.5 ** Critical bug fixed for satisfying the objective range (in file

  • 2013-05-22: version 2.x.2.4 ** Critical bug fixed for noise computation; ** Critical bug fixed for entering the installation path with space, e.g. simulatorPath=C:\Program Files\LTC\LTspiceIV\

  • 2013-05-14: version 2.x.2.3 ** Critical bug fixed for halting after the 'give up' event

  • 2013-05-14: version 2.x.2.2 ** Critical bug fixed for the predefined LTSpice installation path, and the path is configurable via the GUI, with the content saved in 'moea.txt'; ** Critical bug fixed for the same output values for cutoff, ripple, and phase of MOEA evolution; ** The waiting time for LTSpice is configurable via the GUI, the default is 29 seconds; ** Added system print line in console for user level debugging; and ** Avoided executing the same content of netlist (gain, cutoff, ripple and phase), this mechanism accelerates the process of finding optimized solutions.

  • 2013-05-13: version 2.x.2.1 ** Randomized value limit for the input variables is set to 2 decimal points.

  • 2013-05-11: version 2.x.1.1 ** Critical bug fixed for the negative value of Cutoff.

  • 2013-05-10: version 2.x.1.0 ** Bundled with 6 sample circuit designs (in Spice-based netlist file).

  • 2013-05-09: version 2.x.0.0, hereby showed 1.x.x.x obsolete ** Integrated with 5 MOEA: NSGAII, SPEA2, IBEA, FastPGA, PAES ** The range of input variables are editable using GUI ** The objective optimization can exist in range value or single value (i.e. same value for lower and upper limit) ** MOEA is configurable (via parameters in Setting) using GUI ** Computed results (intermediate and final optimized results) are in TextArea panel (ease for copy and paste with scrolling) ** Cmizer's window (the GUI) can be maximized (ease for use) but need minimum screen resolution 1024 x 800. ** The MOEA's setting & the range of Input-Objective are auto-backup (if any changes found) in the directory 'log' ** With the new looks of GUI in design ** Auto detect Input variable based on given netlist file (netlist's file name and parameter need to follow certain naming convention) ** Dynamic loading type of objectives, i.e. currently supported gain, cutoff, ripple, and noise, to MOEA. ** Ease in sharing the same setting for particular circuit design, i.e. saved in file cmizer.txt and moea.txt, in your current Cmizer with others. Just simply copy these two files from directory data/circuit/ and overwrite them in other Cmizer in another computer. ** Bundled with 5 sample circuit designs (in Spice-based netlist file).


If you would like to cite Cmizer, cite the following info:

Choo Jun Tan and Wei Jer Lim and Siew Chin Neoh, Chee Peng Lim and Kian Meng Tey, Cmizer: Multi-objective Evolutionary Algorithm-Based Circuit Optimizer, 2013, software available at

The bibtex format is as follows

    author =	 {Choo Jun Tan and Wei Jer Lim and Siew Chin Neoh and Chee Peng Lim and Kian Meng Tey},
    title =	 {{Cmizer}: Multi-objective Evolutionary Algorithm-Based Circuit Optimizer},
    year =	 {2013},
    note =	 {Software available at \url{}}
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