Improve logic gate shapes (American OR/AND/XOR) to match standard symbols

[jason-s]

Please improve the OR/AND/XOR symbols in circuitikz. Right now they are not consistent with the symbols used in international standards, semiconductor manufacturer datasheets for these gates, or the standard schematic capture symbols. The circuitikz versions look more stylized, like Star Trek insignia.

Suggestions for reputable sources:

• International standards

  • IEEE Std 91-1973 -- see Appendix A
    

  • IEEE Std 91/91a-1984 and IEEE Std 91/91a-1991 (as mentioned in Wikipedia ) -- see Annex A
    

• Semiconductor manufacturers of logic gates

  • TI
  • Nexperia (formerly Philips)
  • On Semi (formerly Motorola) -- possibly; the logic gates from ON Semi / Fairchild / Harris / etc. have symbols that look clunky compared to TI and Nexperia.

• Schematic capture programs

  • Altium
  • OrCAD
  • Mentor Graphics / DxDesigner

In particular:

AND gate

circuitikz (as of 1.0.2)

IEEE 91-1973:

IEEE 91-1984:

You will note:

• the input side of the AND gate is three sides of a rectangle, with two horizontal straight sections, Recommended ratio of height to width is 20:15 in IEEE 91-1973 and 26:19 in IEEE 91-1984. (The circuitikz symbol has no horizontal sections)
• the output side of the AND gate is a half-circle (The circuitikz's curved section looks like a parabola)

OR gate

circuitikz:

IEEE 91-1973:

IEEE 91-1984:

TI SN74HC32

Nexperia 74HC32

You will note:

• the OR gate has two horizontal straight sections, roughly forming a rectangle. Ratio of height to width as recommended by the IEEE standards is approximately 2.005 (exact: 6.5 / (14.5 - 6.5×sqrt(3)) ) per IEEE 91-1984 and roughly 1.93:1 (exact: 20/(45-20×sqrt(3)) per IEEE 91-1973 although that drawing is overdetermined and I have ignored the "8". I would probably just pick 2.0 (The circuitikz symbol has no horizontal sections)
• the front part of the OR gate is a pair of 60 degree circular arcs connecting the points of an equilateral triangle, as recommended by the IEEE standards (The circuitikz symbol has an acuminate or apiculate point; it should be an obtuse point.)
• the back part of the OR gate is a 60 degree circular arc, as recommended by the two IEEE standards
• the line joins of the OR gate are inconsistent; TI uses a round join, not a miter join; Nexperia uses a miter join; the Appendix/Annex A of the standards look like a miter join

XOR gate

circuitikz:

IEEE 91-1973:

IEEE 91-1984:

TI SN74HC86

Nexperia 74HC86

You will note:

• the XOR gate symbol is identical to the OR gate except for the extra curve which is identical to the input-side curve of the OR gate, but it is offset horizontally. (IEEE 91-1973 recommends a horizontal shift that is 3/20 = 15% of the height; IEEE 91-1984 recommends 5/26 = approx 19.2% of the height)

• The TI and Nexperia datasheets show input lines stopping at the main OR gate core, and crossing over the extra curve of the XOR gate. This looks weird to me but it is consistent with IEEE 91-1973; here's the relevant section of Appendix C:

  

  and IEEE 91-1984 Annex C:

  

Other issues

• Negation indicator ("dot"/"bubble")
  • IEEE 91-1973 recommends a radius R = 1/20 of the height of the symbol
  • IEEE 91-1984 recommends a radius R = 1/13 of the height of the symbol = (0.5H) / (6.5H)
• Line width of symbol outline
  • No clear recommendation from the IEEE standards, some sources show slightly thicker symbol outlines than wire thickness
• Location of input lines
  • No clear recommendation from the IEEE standards, all these examples show 2-input gates with input terminals that are about 1/5 - 1/3 of the way from top to center -- in other words, distance from top to input terminal in 1 = 1/10 - 1/6 of gate height.

[Rmano]

Very nice research work, thanks.

I think I can try a shoot at this when I have some time (really swamped now with the coronavirus emergency and the on-line shift of classes and everything). Obviously this must be done under a style flag because the change in proportions is quite big.

I think that we can leave the position of terminals like now (more or less it matches) and the thickness is already configurable.

I have a couple of doubts about implementation.

1. now the size of "not" circles is the same as poles in the circuits --- to match the rest of them (and the circle in PMOS transistors). I am thinking of leaving them alone.
2. in current gates the output "not" circle in included into the width of the gate, so that stacking vertically the gates with labels at the output has that labels naturally align. In the specs above the dot is sticking out --- having the two things at the same time (dot sticking out and label alignment) is going to be very complex. I do not know where to give here.
3. (more important) I do not know how to scale the ports for a lot of input ports (say 16, which is the maximum now). The current design has independent width and height, so you can do tricks with vertically stretched gates (not standard but understandable); this spec has just one dimension (the usage of circles and not splines in the definitions of shapes clearly forces that) and so a 16-input port with a standard input pin distance will be unbearably wide (see the example on the manual around page 101 and 103).

I will mention the co-authors and recent contributors here so that they can chime in --- @mredaelli @sistlind @asinghvi17 @der-stefan @jesseopdenbrouw

BTW any help and contribution is clearly welcome! ;-)

[jason-s]

see https://gist.github.com/jason-s/ebea0a9d5fae9a7d7f5eae2f9620f98e

I don't know how to properly make circuitikz shapes, there were a couple of fudged (empirical) numbers I put in to make it look ok. Otherwise I have something for my purposes and I am fine with circuitikz using it in whichever way you wish.

[jason-s]

I think I can try a shoot at this when I have some time (really swamped now with the coronavirus emergency and the on-line shift of classes and everything). Obviously this must be done under a style flag because the change in proportions is quite big.

yeah, I'm in no hurry; again, I have what I need to make my own diagrams.

I'd suggest ieee as a style flag.

in current gates the output "not" circle in included into the width of the gate, so that stacking vertically the gates with labels at the output has that labels naturally align. In the specs above the dot is sticking out --- having the two things at the same time (dot sticking out and label alignment) is going to be very complex. I do not know where to give here.

Not sure what to recommend. (I didn't implement any of the dotted variants.) Let me see if I can find an example in corporate datasheets; the IEEE standards don't show the labels.

The XOR input curve is a related issue; it's not clear whether to extend the input terminals so they protrude a consistent length from the gate, or whether the overall width should be the same for all three. (I favor the latter, so I used it in my implementation.)

(more important) I do not know how to scale the ports for a lot of input ports (say 16, which is the maximum now). The current design has independent width and height, so you can do tricks with vertically stretched gates (not standard but understandable); this spec has just one dimension (the usage of circles and not splines in the definitions of shapes clearly forces that) and so a 16-input port with a standard input pin distance will be unbearably wide (see the example on the manual around page 101 and 103).

Not sure what to do here; I don't know a lot of examples from industry of wide-input gates.

IEEE 91-1984 suggests the following in Annex C:

[jason-s]

I will mention the co-authors and recent contributors here so that they can chime in --- @mredaelli @sistlind @asinghvi17 @der-stefan @jesseopdenbrouw

Is there an online channel (gitter or Teams or discord or Google Groups or whatever) for tikz or circuitikz development? I'd like to lurk there so that I can see what's going on, rather than watch all the github issues. I had no idea that #340 was in progress, and if I had been aware of it then, I would have spoken up.

[jason-s]

OK, for examples of wide-input gates in industry, see the following. The short answer is that the outline proportions don't change.

• 74xx133 13-input NAND gate
  • TI SN74ALS133
  • National Semiconductor MM74HC133
• 74xx30 8-input NAND gate
  • ON Semi MC74HC30A
  • Nexperia 74LVC30A
• 74xx4078 or CD4078 8-input NOR gate
  • ST M74HC4078
  • Harris CD4078B
• Other:
  • Motorola 1988 CMOS Logic Data book page 6-6

SN74ALS133

MM74HC133

MC74HC30A

74LVC30A

M74HC4078 (crowded together)

CD4078B (crowded together)
)

Motorola 1988 CMOS guide

[Rmano]

Wow! Nice information (and thanks for the code, it'll be useful). I'll look into it; the extension for several inputs is not a bad idea...

Yes, ieee logic ports would be a nice option to have. Well. I'll see what I can do. Maybe the not dot can be added after the fact, as the input ones --- I could just use your code in this case. Maybe they could just be a different family of components that can have matched pin widths similar to what muxdemuxes are.

Is there an online channel (gitter or Teams or discord or Google Groups or whatever) for tikz or circuitikz development? I'd like to lurk there so that I can see what's going on, rather than watch all the github issues. I had no idea that #340 was in progress, and if I had been aware of it then, I would have spoken up.

No, there isn't; basically everything goes through this GitHub page. I lurk often on TeX.sx chat room (depending on the available time).

[jason-s]

As far as the logic bubbles / shape widths go, here are some examples in the wild showing that in the majority of cases, the inversion bubbles do not change the geometry, and can be inserted/removed without changes:

Motorola 74LS138 -- 1992 data book p. 5-130

TI SN74LVC1G99

NXP 2016 Logic Selection Guide

Nexperia 74LVC1G99 -- the text/connections have geometry independent of the bubbles, but note the Schmitt trigger symbol which moves to be as close to the symbol outline as possible... and it looks weird to me.

[jason-s]

the extension for several inputs is not a bad idea...

that wasn't from me, that was from John Kormylo's tex.stackexchange.com post which I thought had been incorporated into circuitikz already. I'd suggest doing a diff between my gist and the original (i'll add it to the gist) -- I didn't change much.

[Rmano]

the extension for several inputs is not a bad idea...

that wasn't from me, that was from John Kormylo's tex.stackexchange.com post which I thought had been incorporated into circuitikz already. I'd suggest doing a diff between my gist and the original (i'll add it to the gist) -- I didn't change much.

Yes --- I have incorporated it (with minor changes) since 0.9.0 I think. I was referring to the vertical bar used for more than two o three inputs that you posted from the datasheets:

[Rmano]

I will assign this to me. Trying to tackle it during Easter (...nowhere to go...)

[Rmano]

@jason-s --- any special way you prefer for citing you in the code and documentation? Jason Sachs<any email here>?

[Rmano]

One thing. In the table the NOT port seems more or less the same height than a 2-inputs NOR:

...but it seems quite big to me. Have you any example with 2-inputs and NOT ports togheter?

[jason-s]

@jason-s --- any special way you prefer for citing you in the code and documentation? Jason Sachs?

Jason Sachs jmsachs@gmail.com

[jason-s]

One thing. In the table the NOT port seems more or less the same height than a 2-inputs NOR:

...but it seems quite big to me. Have you any example with 2-inputs and NOT ports togheter?

Neither IEEE 91-1973 nor IEEE 91-1984 recommends dimensions for a NOT gate, which is kind of odd, but see the examples I posted above for the 1G99 gates from Nexperia and TI, where the NOT gate is the same height.

Nexperia 1G99:

TI 1G99

[Rmano]

Yes, I think that the standard is the same height. Also, my Sedra-Smith follows this norm. Thanks!

When I have something test-able, I'll post here.

[Rmano]

I am at a good point. I have

and anchors do work...

...stay tuned!

[Rmano]

@JoseDanielMunozFrias --- do you like them?

[JoseDanielMunozFrias]

¡They are prefect!

¡Great work!

[Rmano]

Current state of the manual:

ieeeports-manual.pdf

[jesseopdenbrouw]

Perfect & marvelous!

[Rmano]

I think that the not-ports should be equilateral triangles... will check. Not too difficult to change ;-).

[jason-s]

Current state of the manual: [ieeeports-manual.pdf]

Two suggested corrections:

In addition to the legacy ports, since release 1.0.3, also logic port conforming (more or less) to
IEEE Std 91/91a-1984 and IEEE Std 91/91a-1991 are available. The suggestion and a first shot
at the code is bt Jason Sachs (jmsachs@gmail.com); you can see it on this GitHub issue

The IEEE standards don't have requirements of how these basic symbols should look, only recommendations. The requirements of these standards have more to do with annotations on digital logic, like certain designators: BI = borrow input, BO = borrow output, CI = carry input, CO = carry output, D/J/K/R/S for flip-flops and latches and what they are supposed to mean, etc. And the vast majority of the standard applies to the Rectangular-shape symbols, not the Distinctive-shape symbols. The "Annex A" (Recommended symbol proportions) just covers recommended geometric dimensions for the both the Rectangular- and distinctive-shape symbols.

The rectangular-shape symbols you will see in datasheets also, especially when there are more complex behaviors; here's from the TI 74LS138:

So I would remove the word conforming and instead suggest this wording:

In addition to the legacy ports, since release 1.0.3, logic ports following the recommended geometry of distinctive-shape symbols in IEEE Std 91a-1991 Annex A (Recommended symbol proportions) are also available.

Second issue: I appreciate the credit but please don't put my name/address there in the body of the document; in the release notes or in the contributors list is fine.

[jason-s]

I think that the not-ports should be equilateral triangles... will check. Not too difficult to change ;-).

Yeah, it looks that way to me, although the IEEE Std 91-1984 and 91-1973 don't include not gates in their Appendix/Annex A for some reason. (Amplifiers are included, and they are equilateral triangles somewhat larger than the logic gate symbols.)

[Rmano]

So I would remove the word conforming and instead suggest this wording:

In addition to the legacy ports, since release 1.0.3, logic ports following the recommended geometry of distinctive-shape symbols in IEEE Std 91a-1991 Annex A (Recommended symbol proportions) are also available.

Second issue: I appreciate the credit but please don't put my name/address there in the body of the document; in the release notes or in the contributors list is fine.

Done; I'll do this:

In addition to the legacy ports, since release 1.0.3, logic ports following the recommended geometry 
of distinctive-shape symbols in IEEE Std 91a-1991 Annex A (Recommended symbol proportions) 
are also available\footnote{Thanks to Jason for proposing it and digging out the info, see this 
\href{https://github.com/circuitikz/circuitikz/issues/383}{GitHub issue}.}.

is it ok for you?

[Rmano]

ieeeports-manual.pdf

I think it's more or less ready. Will start to prepare the PR...

[Rmano]

Force-pushed to correct a typo in a commit (I hate them) and I will merge it --- It's easier to test that way. I hope there is no big bug left...

[Rmano]

Ok --- Please test and reopen if needed

[shirriff]

@jason-s: I was looking for "official" information on gate symbols and your research here was very helpful.