VHDL and Verilog minimal examples. IC design and synthesis tutorials. Asserts used wherever possible.
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interactive
verilog
vhdl
.gitignore
.gtkwaverc
README.md
applications.md
behavioural-vs-structural.md
bibliography.md
cadence.md
clock-tree.md
cpu.md
design.md
fpga.md
genus.md
getting-started.md
ghdl.md
glossary.md
graywolf-cfree.patch
gtkwave.md
history.md
incisive.md
introduction.md
language.md
latch.md
memory-model.md
microchip-fabrication.md
motivation.md
open-cpus.md
qflow-setup
risc-v.md
simulators.md
simvision.md
smp.md
standard-cell-library.md
standards.md
synopsys.md
synthesis.md
timing.md
vcd.md
vcs.md
vendors.md
wave-files.md
y86.md
yosys.md